sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

usbdebug: Put ehci_debug_info in CAR_GLOBAL

Browse Source 
Store EHCI Debug Port runtime variables in CAR_GLOBAL.
For platforms without CAR_MIGRATION, logging on EHCI Debug Port is
temporarily lost when CAR is torn down at end of romstage.

On model_2065x and model_206ax ehci_debug_info was overlapping the MRC
variable region and additionally migration used incorrect size for
the structure.

Change-Id: I5e6c613b8a4b1dda43d5b69bd437753108760fca
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/3475
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Kyösti Mälkki
2013-07-06 11:41:09 +03:00
committed by Stefan Reinauer
parent 41c10cd2d7
commit 8ee04d784c
6 changed files with 7 additions and 48 deletions
Download Patch File Download Diff File Expand all files Collapse all files

5
src/cpu/intel/car/cache_as_ram_ht.inc
View File

@@ -334,12 +334,7 @@ no_msr_11e:
post_code(0x2e)
/* Set up the stack pointer. */
#if CONFIG_USBDEBUG
/* Leave some space for the struct ehci_debug_info. */
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %esp
#else
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %esp
#endif
/* Restore the BIST result. */
movl %ebp, %eax

9
src/cpu/intel/haswell/cache_as_ram.inc
View File

@@ -190,15 +190,6 @@ before_romstage:
post_code(0x2f)
/* Copy global variable space (for USBDEBUG) to memory */
#if CONFIG_USBDEBUG
cld
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi
movl $(CONFIG_RAMTOP - 24), %edi
movl $24, %ecx
rep movsb
#endif
post_code(0x30)
/* Disable cache. */

9
src/cpu/intel/model_2065x/cache_as_ram.inc
View File

@@ -182,15 +182,6 @@ before_romstage:
post_code(0x2f)
/* Copy global variable space (for USBDEBUG) to memory */
#if CONFIG_USBDEBUG
cld
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi
movl $(CONFIG_RAMTOP - 24), %edi
movl $24, %ecx
rep movsb
#endif
post_code(0x30)
/* Disable cache. */

9
src/cpu/intel/model_206ax/cache_as_ram.inc
View File

@@ -182,15 +182,6 @@ before_romstage:
post_code(0x2f)
/* Copy global variable space (for USBDEBUG) to memory */
#if CONFIG_USBDEBUG
cld
movl $(CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - 24), %esi
movl $(CONFIG_RAMTOP - 24), %edi
movl $24, %ecx
rep movsb
#endif
post_code(0x30)
/* Disable cache. */

5
src/cpu/intel/model_6ex/cache_as_ram.inc
View File

@@ -126,12 +126,7 @@ clear_mtrrs:
movl %eax, %cr0
/* Set up the stack pointer. */
#if CONFIG_USBDEBUG
/* Leave some space for the struct ehci_debug_info. */
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4 - 128), %eax
#else
movl $(CACHE_AS_RAM_BASE + CACHE_AS_RAM_SIZE - 4), %eax
#endif
movl %eax, %esp
/* Restore the BIST result. */