diff --git a/src/mainboard/system76/gaze17/variants/3050/overridetree.cb b/src/mainboard/system76/gaze17/variants/3050/overridetree.cb
index 86ea246c88..94b03cdb02 100644
--- a/src/mainboard/system76/gaze17/variants/3050/overridetree.cb
+++ b/src/mainboard/system76/gaze17/variants/3050/overridetree.cb
@@ -17,13 +17,15 @@ chip soc/intel/alderlake
 				.clk_req = 0,
 				.flags = PCIE_RP_LTR,
 			}"
-			chip soc/intel/common/block/pcie/rtd3
-				# XXX: Enable tied to 3.3VS?
-				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
-				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
-				register "srcclk_pin" = "0" # SSD0_CLKREQ#
-				device generic 0 on end
-			end
+			#chip soc/intel/common/block/pcie/rtd3
+			#	# XXX: Enable tied to 3.3VS?
+			#	#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SATA_M2_PWR_EN2
+			#	register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+			#	register "reset_delay_ms" = "100"
+			#	register "reset_off_delay_ms" = "100"
+			#	register "srcclk_pin" = "0" # SSD0_CLKREQ#
+			#	device generic 0 on end
+			#end
 		end
 		device ref xhci on
 			# USB2
@@ -51,6 +53,7 @@ chip soc/intel/alderlake
 				# XXX: Enable tied to 3.3VS?
 				#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
 				register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
+				register "disable_l23" = "true"
 				register "srcclk_pin" = "1" # SSD1_CLKREQ#
 				device generic 0 on end
 			end