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amd/stoneyridge: Add S3 support to POST

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Add/update the romstage and ramstage paths to check for S3 resume
and call the appropriate AGESA functions.

TEST=Suspend/Resume Kahlee with full S3 patch stack
BUG=b:69614064

Change-Id: Ie6ae66f88b888fff3a800b4ed55dd1f6fed712b2
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/22731
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
This commit is contained in:
Marshall Dawson
2017-11-01 11:44:48 -06:00
committed by Martin Roth
parent bb6c3f59d1
commit 8f2a7e073b
4 changed files with 58 additions and 38 deletions
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18
src/soc/amd/stoneyridge/chip.c
View File

@@ -21,6 +21,7 @@
#include <device/device.h>
#include <device/pci.h>
#include <drivers/i2c/designware/dw_i2c.h>
#include <romstage_handoff.h>
#include <soc/cpu.h>
#include <soc/northbridge.h>
#include <soc/pci_devs.h>
@@ -110,12 +111,19 @@ struct chip_operations soc_amd_stoneyridge_ops = {
static void earliest_ramstage(void *unused)
{
post_code(0x46);
if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2");
if (!romstage_handoff_is_resume()) {
post_code(0x46);
if (IS_ENABLED(CONFIG_SOC_AMD_PSP_SELECTABLE_SMU_FW))
psp_load_named_blob(MBOX_BIOS_CMD_SMU_FW2, "smu_fw2");
post_code(0x47);
do_agesawrapper(agesawrapper_amdinitenv, "amdinitenv");
post_code(0x47);
do_agesawrapper(agesawrapper_amdinitenv, "amdinitenv");
} else {
/* Complete the initial system restoration */
post_code(0x46);
do_agesawrapper(agesawrapper_amds3laterestore,
"amds3laterestore");
}
}
BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, earliest_ramstage, NULL);