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No warnings day, next round.

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Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5359 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Stefan Reinauer
2010-04-06 21:50:21 +00:00
committed by Stefan Reinauer
parent 233f186e95
commit 8f2c616dbc
28 changed files with 98 additions and 104 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/cpu/amd/model_10xxx/init_cpus.c
View File

@@ -91,7 +91,7 @@ static void set_pci_mmio_conf_reg(void)
wrmsr(0xc0010058, msr); // MMIO Config Base Address Reg
//mtrr for that range?
// set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
// set_var_mtrr_x(7, PCI_MMIO_BASE<<8, PCI_MMIO_BASE>>(32-8), 0x00000000, 0x01, MTRR_TYPE_UNCACHEABLE);
set_wrap32dis();
@@ -293,7 +293,7 @@ static void enable_apic_ext_id(u32 node)
}
static void STOP_CAR_AND_CPU()
static void STOP_CAR_AND_CPU(void)
{
msr_t msr;
@@ -529,7 +529,7 @@ static void setup_remote_node(u8 node)
}
#endif /* CONFIG_MAX_PHYSICAL_CPUS > 1 */
void AMD_Errata281(u8 node, u32 revision, u32 platform)
static void AMD_Errata281(u8 node, u32 revision, u32 platform)
{
/* Workaround for Transaction Scheduling Conflict in
* Northbridge Cross Bar. Implement XCS Token adjustment
@@ -591,7 +591,7 @@ void AMD_Errata281(u8 node, u32 revision, u32 platform)
}
void AMD_Errata298(void)
static void AMD_Errata298(void)
{
/* Workaround for L2 Eviction May Occur during operation to
* set Accessed or dirty bit.

3
src/cpu/amd/model_fxx/model_fxx_init.c
View File

@@ -244,7 +244,6 @@ static inline void clear_2M_ram(unsigned long basek, struct mtrr_state *mtrr_sta
static void init_ecc_memory(unsigned node_id)
{
unsigned long startk, begink, endk;
unsigned long hole_startk = 0;
unsigned long basek;
struct mtrr_state mtrr_state;
@@ -291,6 +290,8 @@ static void init_ecc_memory(unsigned node_id)
endk = ((pci_read_config32(f1_dev, 0x44 + (node_id*8)) & 0xffff0000) >> 2) + 0x4000;
#if CONFIG_HW_MEM_HOLE_SIZEK != 0
unsigned long hole_startk = 0;
#if CONFIG_K8_REV_F_SUPPORT == 0
if (!is_cpu_pre_e0())
{

2
src/cpu/amd/model_lx/cpureginit.c
View File

@@ -25,7 +25,7 @@
;* SetDelayControl
;*
;*************************************************************************/
void SetDelayControl(void)
static void SetDelayControl(void)
{
unsigned int msrnum, glspeed;
unsigned char spdbyte0, spdbyte1;

35
src/cpu/x86/mtrr/earlymtrr.c
View File

@@ -4,37 +4,7 @@
#include <cpu/x86/mtrr.h>
#include <cpu/x86/msr.h>
/* Validate CONFIG_XIP_ROM_SIZE and CONFIG_XIP_ROM_BASE */
#if defined(CONFIG_XIP_ROM_SIZE) && !defined(CONFIG_XIP_ROM_BASE)
# error "CONFIG_XIP_ROM_SIZE without CONFIG_XIP_ROM_BASE"
#endif
#if defined(CONFIG_XIP_ROM_BASE) && !defined(CONFIG_XIP_ROM_SIZE)
# error "CONFIG_XIP_ROM_BASE without CONFIG_XIP_ROM_SIZE"
#endif
#if !defined(CONFIG_RAMTOP)
# error "CONFIG_RAMTOP not defined"
#endif
#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_SIZE & (CONFIG_XIP_ROM_SIZE -1)) != 0)
# error "CONFIG_XIP_ROM_SIZE is not a power of 2"
#endif
#if defined(CONFIG_XIP_ROM_SIZE) && ((CONFIG_XIP_ROM_BASE % CONFIG_XIP_ROM_SIZE) != 0)
# error "CONFIG_XIP_ROM_BASE is not a multiple of CONFIG_XIP_ROM_SIZE"
#endif
#if (CONFIG_RAMTOP & (CONFIG_RAMTOP -1)) != 0
# error "CONFIG_RAMTOP must be a power of 2"
#endif
#if defined(CONFIG_XIP_ROM_SIZE)
# if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
extern unsigned long AUTO_XIP_ROM_BASE;
# define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
# else
# define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
# endif
#endif
#if 0
static void disable_var_mtrr(unsigned reg)
{
/* The invalid bit is kept in the mask so we simply
@@ -45,6 +15,7 @@ static void disable_var_mtrr(unsigned reg)
zero.lo = zero.hi = 0;
wrmsr(MTRRphysMask_MSR(reg), zero);
}
#endif
static void set_var_mtrr(
unsigned reg, unsigned base, unsigned size, unsigned type)
@@ -61,6 +32,7 @@ static void set_var_mtrr(
wrmsr(MTRRphysMask_MSR(reg), maskm);
}
#if 0
static void set_var_mtrr_x(
unsigned reg, uint32_t base_lo, uint32_t base_hi, uint32_t size_lo, uint32_t size_hi, unsigned type)
@@ -79,6 +51,7 @@ static void set_var_mtrr_x(
}
wrmsr(MTRRphysMask_MSR(reg), maskm);
}
#endif
static void cache_lbmem(int type)
{