sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

nb/intel/x4x: Refactor decode_pcie_bar

Browse Source 
Constify and eliminate local variables where possible to ease reading.

Tested with BUILD_TIMELESS=1, Asus P5QL PRO does not change.

Change-Id: I6d2937146a4764823cfc45c69a09f734b2525860
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Angel Pons
2020-08-03 15:53:20 +02:00
parent ce3e6380b9
commit 8f917b1d4b
1 changed files with 5 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

14
src/northbridge/intel/x4x/memmap.c
View File

@@ -61,11 +61,7 @@ int decode_pcie_bar(u32 *const base, u32 *const len)
{
*base = 0;
*len = 0;
const pci_devfn_t dev = PCI_DEV(0, 0, 0);
u32 pciexbar = 0;
u32 pciexbar_reg;
u32 reg32;
int max_buses;
const struct {
u16 num_buses;
u32 addr_mask;
@@ -76,16 +72,16 @@ int decode_pcie_bar(u32 *const base, u32 *const len)
{0, 0},
};
pciexbar_reg = pci_read_config32(dev, D0F0_PCIEXBAR_LO);
const u32 pciexbar_reg = pci_read_config32(PCI_DEV(0, 0, 0), D0F0_PCIEXBAR_LO);
if (!(pciexbar_reg & 1)) {
printk(BIOS_WARNING, "WARNING: MMCONF not set\n");
return 0;
}
reg32 = (pciexbar_reg >> 1) & 3;
pciexbar = pciexbar_reg & busmask[reg32].addr_mask;
max_buses = busmask[reg32].num_buses;
const u32 index = (pciexbar_reg >> 1) & 3;
const u32 pciexbar = pciexbar_reg & busmask[index].addr_mask;
const int max_buses = busmask[index].num_buses;
if (!pciexbar) {
printk(BIOS_WARNING, "WARNING: pciexbar invalid\n");