riscv-spike: support for Spike emulation of riscv

Spike support: QEMU RISCV is broken, and the maintainers at Berkeley
are working on it, but at the moment spike is the only way to  test
on riscv. Add support for spike console output for debugging.

Privileged ISA: Update to privileged ISA in RISCV (machine,
supervisor, hypervisor, user modes) broke exisitng RISCV asm, and
bootblock.S was updated to match the new spec. Clean old assembly

[pg: things build with gcc 4.9 now, but don't expect them to work.
Hardcoding register names into the assembler language may not be the smartest
idea of the RISCV folks.]

Change-Id: Ie2c109d3c26712c207512f74f28ce1a925e6e181
Signed-off-by: Thaminda Edirisooriya <thaminda@google.com>
Reviewed-on: http://review.coreboot.org/11078
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/arch/riscv/bootblock.S

@@ -22,30 +22,33 @@
 
 .section ".text._start", "ax", %progbits
 // Maybe there's a better way.
-.space 0x2000
+.space 0x200
 .globl _start
 _start:
 
 	// pending figuring out this f-ing toolchain. Hardcode what we know works.
-  la sp, 0x4ef0 // .stacktop
-//  la a0, trap_entry
+//  la sp, 0x4ef0 // .stacktop
+//  la sp, 0x40000 // from src/mainboard/emulation/qemu-riscv
+  la sp, 0x7FF00 // stack start + stack size
+
+  // make room for HLS
+  addi sp, sp, -64 // MENTRY_FRAME_SIZE
+
+
+  //poison the stack
+  la t1, 0x40000
+  li t0, 0xdeadbeef
+  sd t0, 0(t1)
+
 //  la gp, _gp
-//  csrw evec, a0
 
   # clear any pending interrupts
+#if __GNUC__ < 5
   csrwi clear_ipi, 0
+#else
+  csrwi sip, 0
+#endif
 
-  li a0, SR_S | SR_PS | SR_EI | SR_S64 | SR_U64
-  or a1, a0, SR_EF | SR_EA
-  csrw status, a1
-  csrr a1, status
-  csrw status, a0
-
-//  and a2, a1, SR_EF
-//  sw a2, have_fp, t0
-
-//  and   a2, a1, SR_EA
-//  sw a2, have_accelerator, t0
   call main
 .=0x4000
 .stack:

src/arch/riscv/include/arch/atomic.h

@@ -1,75 +0,0 @@
-// See LICENSE for license details.
-
-#ifndef _RISCV_ATOMIC_H
-#define _RISCV_ATOMIC_H
-
-#include <arch/encoding.h>
-
-typedef struct { volatile long val; } atomic_t;
-typedef struct { atomic_t lock; } spinlock_t;
-#define SPINLOCK_INIT {{0}}
-
-#define mb() __sync_synchronize()
-
-static inline void atomic_set(atomic_t* a, long val)
-{
-  a->val = val;
-}
-
-static inline long atomic_read(atomic_t* a)
-{
-  return a->val;
-}
-
-static inline long atomic_add(atomic_t* a, long inc)
-{
-  long ret = atomic_read(a);
-  atomic_set(a, ret + inc);
-  return ret;
-}
-
-static inline long atomic_swap(atomic_t* a, long val)
-{
-  long ret = atomic_read(a);
-  atomic_set(a, val);
-  return ret;
-}
-
-static inline long atomic_cas(atomic_t* a, long compare, long swap)
-{
-  long ret = atomic_read(a);
-  if (ret == compare)
-    atomic_set(a, swap);
-  return ret;
-}
-
-static inline void spinlock_lock(spinlock_t* lock)
-{
-  do
-  {
-    while (atomic_read(&lock->lock))
-      ;
-  } while (atomic_swap(&lock->lock, -1));
-  mb();
-}
-
-static inline void spinlock_unlock(spinlock_t* lock)
-{
-  mb();
-  atomic_set(&lock->lock,0);
-}
-
-static inline long spinlock_lock_irqsave(spinlock_t* lock)
-{
-  long flags = clear_csr(status, SR_EI);
-  spinlock_lock(lock);
-  return flags;
-}
-
-static inline void spinlock_unlock_irqrestore(spinlock_t* lock, long flags)
-{
-  spinlock_unlock(lock);
-  set_csr(status, flags & SR_EI);
-}
-
-#endif

src/arch/riscv/include/atomic.h

@@ -0,0 +1,73 @@
+// See LICENSE for license details.
+
+#ifndef _RISCV_ATOMIC_H
+#define _RISCV_ATOMIC_H
+
+//#include "config.h"
+#include <arch/encoding.h>
+
+#define disable_irqsave() clear_csr(sstatus, SSTATUS_IE)
+#define enable_irqrestore(flags) set_csr(sstatus, (flags) & SSTATUS_IE)
+
+typedef struct { int lock; } spinlock_t;
+#define SPINLOCK_INIT {0}
+
+#define mb() __sync_synchronize()
+#define atomic_set(ptr, val) (*(volatile typeof(*(ptr)) *)(ptr) = val)
+#define atomic_read(ptr) (*(volatile typeof(*(ptr)) *)(ptr))
+
+#ifdef PK_ENABLE_ATOMICS
+# define atomic_add(ptr, inc) __sync_fetch_and_add(ptr, inc)
+# define atomic_swap(ptr, swp) __sync_lock_test_and_set(ptr, swp)
+# define atomic_cas(ptr, cmp, swp) __sync_val_compare_and_swap(ptr, cmp, swp)
+#else
+# define atomic_add(ptr, inc) ({ \
+  long flags = disable_irqsave(); \
+  typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
+  *(volatile typeof(ptr))(ptr) = res + (inc); \
+  enable_irqrestore(flags); \
+  res; })
+# define atomic_swap(ptr, swp) ({ \
+  long flags = disable_irqsave(); \
+  typeof(*ptr) res = *(volatile typeof(ptr))(ptr); \
+  *(volatile typeof(ptr))(ptr) = (swp); \
+  enable_irqrestore(flags); \
+  res; })
+# define atomic_cas(ptr, cmp, swp) ({ \
+  long flags = disable_irqsave(); \
+  typeof(ptr) res = *(volatile typeof(ptr))(ptr); \
+  if (res == (cmp)) *(volatile typeof(ptr))(ptr) = (swp); \
+  enable_irqrestore(flags); \
+  res; })
+#endif
+
+static inline void spinlock_lock(spinlock_t* lock)
+{
+  do
+  {
+    while (atomic_read(&lock->lock))
+      ;
+  } while (atomic_swap(&lock->lock, -1));
+  mb();
+}
+
+static inline void spinlock_unlock(spinlock_t* lock)
+{
+  mb();
+  atomic_set(&lock->lock,0);
+}
+
+static inline long spinlock_lock_irqsave(spinlock_t* lock)
+{
+  long flags = disable_irqsave();
+  spinlock_lock(lock);
+  return flags;
+}
+
+static inline void spinlock_unlock_irqrestore(spinlock_t* lock, long flags)
+{
+  spinlock_unlock(lock);
+  enable_irqrestore(flags);
+}
+
+#endif

src/arch/riscv/include/spike_util.h

@@ -0,0 +1,73 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 The ChromiumOS Authors
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _SPIKE_UTIL_H
+#define _SPIKE_UTIL_H
+
+#include <stdint.h>
+//#include <string.h>
+//#include <errno.h>
+#include <arch/encoding.h>
+#include <atomic.h>
+
+#define LOG_REGBYTES 3
+#define REGBYTES (1 << LOG_REGBYTES)
+#define STORE    sd
+#define HLS_SIZE 64
+#define MENTRY_FRAME_SIZE HLS_SIZE
+
+#define TOHOST_CMD(dev, cmd, payload) \
+    (((uint64_t)(dev) << 56) | ((uint64_t)(cmd) << 48) | (uint64_t)(payload))
+
+#define FROMHOST_DEV(fromhost_value) ((uint64_t)(fromhost_value) >> 56)
+#define FROMHOST_CMD(fromhost_value) ((uint64_t)(fromhost_value) << 8 >> 56)
+#define FROMHOST_DATA(fromhost_value) ((uint64_t)(fromhost_value) << 16 >> 16)
+
+typedef struct {
+  unsigned long dev;
+  unsigned long cmd;
+  unsigned long data;
+  unsigned long sbi_private_data;
+} sbi_device_message;
+
+
+typedef struct {
+  sbi_device_message* device_request_queue_head;
+  unsigned long device_request_queue_size;
+  sbi_device_message* device_response_queue_head;
+  sbi_device_message* device_response_queue_tail;
+
+  int hart_id;
+  int ipi_pending;
+} hls_t;
+
+#define MACHINE_STACK_TOP() ({ \
+  register uintptr_t sp asm ("sp"); \
+  (void*)((sp + RISCV_PGSIZE) & -RISCV_PGSIZE); })
+
+// hart-local storage, at top of stack
+#define HLS() ((hls_t*)(MACHINE_STACK_TOP() - HLS_SIZE))
+
+#define MACHINE_STACK_SIZE RISCV_PGSIZE
+
+uintptr_t htif_interrupt(uintptr_t mcause, uintptr_t* regs);
+uintptr_t mcall_console_putchar(uint8_t ch);
+void testPrint(void);
+
+#endif