sb,soc/intel: Add wake source fields in GNVS

For the moment, these are most not used but become a necessity
for a unified <soc/nvs.h> approach.

They would be required for the implementation of _SWS method
for OSPM to determine the reason for system waking up. The related
hardware registers are present with these platforms.

It's expected that ACPI power-management related GNVS entries are
grouped together to form a single struct in later works.

Change-Id: I6d31d39ac1017cd6fdf0ac66b418d1fbb1edf8e0
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50193
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/baytrail/acpi/globalnvs.asl

@@ -25,6 +25,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	TLVL,	 8,	/* 0x13 - Throttle Level */
 	PPCM,	 8,	/* 0x14 - Maximum P-state usable by OS */
 	PM1I,	 32,	/* 0x15 - System Wake Source - PM1 Index */
+	GPEI,	 32,	/* 0x19 - GPE Wake Source */
 
 	/* Device Config */
 	Offset (0x20),

src/soc/intel/baytrail/include/soc/nvs.h

@@ -25,7 +25,8 @@ struct __packed global_nvs {
 	u8	tlvl; /* 0x13 - Throttle Level */
 	u8	ppcm; /* 0x14 - Maximum P-state usable by OS */
 	u32	pm1i; /* 0x15 - System Wake Source - PM1 Index */
-	u8	rsvd1[7];
+	u32	gpei; /* 0x19 - GPE Wake Source */
+	u8	rsvd1[3];
 
 	/* Device Config */
 	u8	s5u0; /* 0x20 - Enable USB0 in S5 */

src/soc/intel/quark/include/soc/nvs.h

@@ -8,6 +8,10 @@
 struct __packed global_nvs {
 	uint32_t	cbmc; /* 0x00 - 0x03 - coreboot Memory Console */
 	uint8_t		pwrs; /* 0x4 - Power state (AC = 1) */
+
+	/* Required for future unified acpi_save_wake_source. */
+	uint32_t	pm1i;
+	uint32_t	gpei;
 };
 
 #endif /* SOC_INTEL_QUARK_NVS_H */

src/southbridge/intel/bd82x6x/acpi/globalnvs.asl

@@ -100,6 +100,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	Offset (0xb2),
 	XHCI,	 8,
 
+	PM1I,	32,	// System Wake Source - PM1 Index
+	GPEI,	32,	// GPE Wake Source
+
 	Offset (0xf5),
 	TPIQ,	 8,	// 0xf5 - trackpad IRQ value
 	CBMC,	32,

src/southbridge/intel/bd82x6x/include/soc/nvs.h

@@ -97,7 +97,11 @@ struct __packed global_nvs {
 	u8	rsvd11[6];
 	/* XHCI */
 	u8	xhci;
-	u8	rsvd12[65];
+
+	/* Required for future unified acpi_save_wake_source. */
+	u32	pm1i;
+	u32	gpei;
+	u8	rsvd12[57];
 
 	u8	tpiq; /* 0xf5 - trackpad IRQ value */
 	u32     cbmc;

src/southbridge/intel/i82801gx/acpi/globalnvs.asl

@@ -101,4 +101,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	DOCK,	 8,	// 0xf0 - Docking Status
 	BTEN,	 8,	// 0xf1 - Bluetooth Enable
 	CBMC,	32,
+	PM1I,	32,	// System Wake Source - PM1 Index
+	GPEI,	32,	// GPE Wake Source
 }

src/southbridge/intel/i82801gx/include/soc/nvs.h

@@ -98,6 +98,10 @@ struct __packed global_nvs {
 	u8	bten;
 
 	u32     cbmc;
+
+	/* Required for future unified acpi_save_wake_source. */
+	u32	pm1i;
+	u32	gpei;
 };
 
 #endif /* SOUTHBRIDGE_INTEL_I82801GX_NVS_H */

src/southbridge/intel/i82801ix/acpi/globalnvs.asl

@@ -103,4 +103,7 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	DOCK,	 8,	// 0xf0 - Docking Status
 	BTEN,	 8,	// 0xf1 - Bluetooth Enable
 	CBMC,	32,
+	PM1I,	32,	// System Wake Source - PM1 Index
+	GPEI,	32,	// GPE Wake Source
+
 }

src/southbridge/intel/i82801ix/include/soc/nvs.h

@@ -98,6 +98,10 @@ struct __packed global_nvs {
 	u8	bten;
 
 	u32     cbmc;
+
+	/* Required for future unified acpi_save_wake_source. */
+	u32	pm1i;
+	u32	gpei;
 };
 
 #endif /* SOUTHBRIDGE_INTEL_I82801IX_NVS_H */

src/southbridge/intel/i82801jx/acpi/globalnvs.asl

@@ -103,4 +103,6 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	DOCK,	 8,	// 0xf0 - Docking Status
 	BTEN,	 8,	// 0xf1 - Bluetooth Enable
 	CBMC,	32,
+	PM1I,	32,	// System Wake Source - PM1 Index
+	GPEI,	32,	// GPE Wake Source
 }

src/southbridge/intel/i82801jx/include/soc/nvs.h

@@ -97,6 +97,10 @@ struct __packed global_nvs {
 	u8	bten;
 
 	u32     cbmc;
+
+	/* Required for future unified acpi_save_wake_source. */
+	u32	pm1i;
+	u32	gpei;
 };
 
 #endif /* SOUTHBRIDGE_INTEL_I82801JX_NVS_H */

src/southbridge/intel/ibexpeak/acpi/globalnvs.asl

@@ -100,6 +100,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	Offset (0xb2),
 	XHCI,	 8,
 	CBMC,	32,
+	PM1I,	32,	// System Wake Source - PM1 Index
+	GPEI,	32,	// GPE Wake Source
+
 }
 
 /* Set flag to enable USB charging in S3 */

src/southbridge/intel/ibexpeak/include/soc/nvs.h

@@ -100,6 +100,10 @@ struct __packed global_nvs {
 	u8	xhci;
 
 	u32     cbmc;
+
+	/* Required for future unified acpi_save_wake_source. */
+	u32	pm1i;
+	u32	gpei;
 };
 
 #endif /* SOUTHBRIDGE_INTEL_IBEXPEAK_NVS_H */

src/southbridge/intel/lynxpoint/acpi/globalnvs.asl

@@ -93,6 +93,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 
 	Offset (0xa0),
 	CBMC, 32,	// 0xa0 - coreboot mem console pointer
+
+	PM1I,	32,	// System Wake Source - PM1 Index
+	GPEI,	32,	// GPE Wake Source
 }
 
 /* Set flag to enable USB charging in S3 */

src/southbridge/intel/lynxpoint/include/soc/nvs.h

@@ -73,6 +73,10 @@ struct __packed global_nvs {
 	u32	s0b[8]; /* 0x60 - 0x7f - BAR0 */
 	u32	s1b[8]; /* 0x80 - 0x9f - BAR1 */
 	u32	cbmc;   /* 0xa0 - 0xa3 - coreboot memconsole */
+
+	/* Required for future unified acpi_save_wake_source. */
+	u32	pm1i;
+	u32	gpei;
 };
 
 #endif /* SOUTHBRIDGE_INTEL_LYNXPOINT_NVS_H */