mb/system76/kbl-u: Add System76 Galago Pro 3 Rev B
Change-Id: I25464d3a2dd02e613a8392db90b1eaf0f9b3ca70 Signed-off-by: Jeremy Soller <jeremy@system76.com> Signed-off-by: Tim Crawford <tcrawford@system76.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/52217 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Jeremy Soller
committed by
Patrick Georgi
Patrick Georgi
parent
e747bdda1b
commit
9037f0a831
191
src/mainboard/system76/kbl-u/devicetree.cb
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191
src/mainboard/system76/kbl-u/devicetree.cb
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chip soc/intel/skylake
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# Send an extra VR mailbox command for the PS4 exit issue
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register "SendVrMbxCmd" = "2"
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# Power limit
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register "power_limits_config" = "{
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.tdp_pl1_override = 20,
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.tdp_pl2_override = 30,
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}"
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# Enable Enhanced Intel SpeedStep
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register "eist_enable" = "1"
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# Serial I/O
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register "SerialIoDevMode" = "{
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[PchSerialIoIndexUart2] = PchSerialIoSkipInit, // LPSS UART
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}"
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# Serial IRQ
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register "serirq_mode" = "SERIRQ_CONTINUOUS"
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# Power
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register "PmConfigSlpS3MinAssert" = "2" # 50ms
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register "PmConfigSlpS4MinAssert" = "1" # 1s
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register "PmConfigSlpSusMinAssert" = "3" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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# FSP Configuration
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register "SkipExtGfxScan" = "1"
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register "SaGv" = "SaGv_Enabled"
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# VR Settings Configuration for 4 Domains
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#+----------------+-----------+-----------+-------------+----------+
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#| Domain/Setting | SA | IA | GT Unsliced | GT |
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#+----------------+-----------+-----------+-------------+----------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 |
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#| IccMax | 5A | 64A | 31A | 31A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-----------+-----------+-------------+----------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(4),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 0,
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.psi4enable = 0,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(5),
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.voltage_limit = 1520,
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.ac_loadline = 1030,
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.dc_loadline = 1030,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 0,
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.psi4enable = 0,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(64),
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.voltage_limit = 1520,
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.ac_loadline = 240,
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.dc_loadline = 240,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 0,
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.psi4enable = 0,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(31),
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.voltage_limit = 1520,
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.ac_loadline = 310,
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.dc_loadline = 310,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 0,
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.psi4enable = 0,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(31),
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.voltage_limit = 1520,
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.ac_loadline = 310,
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.dc_loadline = 310,
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}"
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device cpu_cluster 0 on
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device lapic 0 on end
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end
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device domain 0 on
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device ref system_agent on end
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device ref igpu on end
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device ref sa_thermal on end
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device ref south_xhci on
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# USB2
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register "usb2_ports[0]" = "USB2_PORT_MID(OC_SKIP)" # Type-A port right
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register "usb2_ports[1]" = "USB2_PORT_FLEX(OC_SKIP)" # 3G / LTE
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register "usb2_ports[2]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right
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register "usb2_ports[3]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
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register "usb2_ports[4]" = "USB2_PORT_FLEX(OC_SKIP)" # Bluetooth
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register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Type-A port left
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register "usb2_ports[7]" = "USB2_PORT_TYPE_C(OC_SKIP)" # Type-C port right
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# USB3
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register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port right
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register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # 4G
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register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type C port right
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register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # Type-A port left
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end
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device ref thermal on end
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device ref sata on
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register "SataSalpSupport" = "0"
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register "SataPortsEnable[0]" = "1"
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register "SataPortsEnable[2]" = "1"
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register "SataSpeedLimit" = "2"
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end
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device ref pcie_rp1 on
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# Root port #1 x4 (TBT)
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register "PcieRpEnable[0]" = "1"
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register "PcieRpClkReqSupport[0]" = "1"
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register "PcieRpClkReqNumber[0]" = "4"
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register "PcieRpClkSrcNumber[0]" = "4"
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register "PcieRpAdvancedErrorReporting[0]" = "1"
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register "PcieRpLtrEnable[0]" = "1"
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register "PcieRpHotPlug[0]" = "1"
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end
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device ref pcie_rp5 on
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# Root port #5 x1 (LAN)
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register "PcieRpEnable[4]" = "1"
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register "PcieRpClkReqSupport[4]" = "1"
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register "PcieRpClkReqNumber[4]" = "3"
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register "PcieRpClkSrcNumber[4]" = "3"
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register "PcieRpAdvancedErrorReporting[4]" = "1"
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register "PcieRpLtrEnable[4]" = "1"
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end
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device ref pcie_rp6 on
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# Root port #6 x1 (WLAN)
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register "PcieRpEnable[5]" = "1"
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register "PcieRpClkReqSupport[5]" = "1"
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register "PcieRpClkReqNumber[5]" = "2"
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register "PcieRpClkSrcNumber[5]" = "2"
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register "PcieRpAdvancedErrorReporting[5]" = "1"
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register "PcieRpLtrEnable[5]" = "1"
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end
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device ref pcie_rp9 on
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# Root port #9 x4 (NVMe)
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register "PcieRpEnable[8]" = "1"
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register "PcieRpClkReqSupport[8]" = "1"
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register "PcieRpClkReqNumber[8]" = "5"
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register "PcieRpClkSrcNumber[8]" = "5"
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register "PcieRpAdvancedErrorReporting[8]" = "1"
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register "PcieRpLtrEnable[8]" = "1"
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end
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device ref lpc_espi on
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register "gen1_dec" = "0x000c0681"
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register "gen2_dec" = "0x000c1641"
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register "gen3_dec" = "0x00040069"
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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end
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device ref p2sb off end
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device ref pmc on
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register "gpe0_dw0" = "GPP_C"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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end
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device ref hda on end
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device ref smbus on end
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device ref fast_spi on end
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end
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end
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