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soc/intel: Replace uses of dev_find_slot()

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To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.

Replace this with method that relies on bus topology
that walks the root bus only.

Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
2019-07-03 07:25:59 +03:00
committed by Nico Huber
parent 9c0e14e7c4
commit 903b40a8a4
32 changed files with 70 additions and 70 deletions
Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/intel/apollolake/acpi.c
View File

@@ -186,7 +186,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
static unsigned long soc_fill_dmar(unsigned long current)
{
struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK;
bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
@@ -219,7 +219,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
* get the info and hide it again when done.
*/
p2sb_unhide();
struct device *p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB);
struct device *p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB);
uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF);
uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF);
p2sb_hide();

6
src/soc/intel/apollolake/chip.c
View File

@@ -256,7 +256,7 @@ static void pcie_update_device_tree(unsigned int devfn0, int num_funcs)
int i;
unsigned int inc = PCI_DEVFN(0, 1);
func0 = dev_find_slot(0, devfn0);
func0 = pcidev_path_on_root(devfn0);
if (func0 == NULL)
return;
@@ -272,7 +272,7 @@ static void pcie_update_device_tree(unsigned int devfn0, int num_funcs)
* as that port was move to func0.
*/
for (i = 1; i < num_funcs; i++, devfn += inc) {
struct device *dev = dev_find_slot(0, devfn);
struct device *dev = pcidev_path_on_root(devfn);
if (dev == NULL)
continue;
@@ -760,7 +760,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
apl_fsp_silicon_init_params_cb(cfg, silconfig);
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = dev_find_slot(0, PCH_DEVFN_XDCI);
dev = pcidev_path_on_root(PCH_DEVFN_XDCI);
if (!xdci_can_enable())
dev->enabled = 0;
silconfig->UsbOtg = dev->enabled;

4
src/soc/intel/apollolake/include/soc/pci_devs.h
View File

@@ -22,8 +22,8 @@
#if !defined(__SIMPLE_DEVICE__)
#include <device/device.h>
#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))
#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot))
#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func))
#else
#define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
#define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)

2
src/soc/intel/apollolake/memmap.c
View File

@@ -35,7 +35,7 @@ void *cbmem_top(void)
if (!CONFIG(SOC_INTEL_GLK))
return tolum;
dev = dev_find_slot(0, PCH_DEVFN_LPC);
dev = pcidev_path_on_root(PCH_DEVFN_LPC);
assert(dev != NULL);
config = dev->chip_info;

2
src/soc/intel/apollolake/pmutil.c
View File

@@ -149,7 +149,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
DEVTREE_CONST struct soc_intel_apollolake_config *config;
/* Look up the device in devicetree */
DEVTREE_CONST struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
DEVTREE_CONST struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
if (!dev || !dev->chip_info) {
printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
return;

6
src/soc/intel/apollolake/romstage.c
View File

@@ -100,7 +100,7 @@ static void soc_early_romstage_init(void)
/* Thermal throttle activation offset */
static void configure_thermal_target(void)
{
const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
if (!dev) {
printk(BIOS_ERR, "Could not find SOC devicetree config\n");
return;
@@ -320,7 +320,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
{
#if CONFIG(SOC_INTEL_GLK)
/* Only for GLK */
const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
assert(dev != NULL);
const config_t *config = dev->chip_info;
FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
@@ -350,7 +350,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
static void parse_devicetree_setting(FSPM_UPD *m_upd)
{
#if CONFIG(SOC_INTEL_GLK)
DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_NPK);
DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK);
if (!dev)
return;