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soc/intel: Replace uses of dev_find_slot()

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To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.

Replace this with method that relies on bus topology
that walks the root bus only.

Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Kyösti Mälkki
2019-07-03 07:25:59 +03:00
committed by Nico Huber
parent 9c0e14e7c4
commit 903b40a8a4
32 changed files with 70 additions and 70 deletions
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6
src/soc/intel/apollolake/chip.c
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@@ -256,7 +256,7 @@ static void pcie_update_device_tree(unsigned int devfn0, int num_funcs)
int i;
unsigned int inc = PCI_DEVFN(0, 1);
func0 = dev_find_slot(0, devfn0);
func0 = pcidev_path_on_root(devfn0);
if (func0 == NULL)
return;
@@ -272,7 +272,7 @@ static void pcie_update_device_tree(unsigned int devfn0, int num_funcs)
* as that port was move to func0.
*/
for (i = 1; i < num_funcs; i++, devfn += inc) {
struct device *dev = dev_find_slot(0, devfn);
struct device *dev = pcidev_path_on_root(devfn);
if (dev == NULL)
continue;
@@ -760,7 +760,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
apl_fsp_silicon_init_params_cb(cfg, silconfig);
/* Enable xDCI controller if enabled in devicetree and allowed */
dev = dev_find_slot(0, PCH_DEVFN_XDCI);
dev = pcidev_path_on_root(PCH_DEVFN_XDCI);
if (!xdci_can_enable())
dev->enabled = 0;
silconfig->UsbOtg = dev->enabled;