soc/intel: Replace uses of dev_find_slot()

To call dev_find_slot(0, xx) in romstage can produce
invalid results since PCI bus enumeration has not
been progressed yet.

Replace this with method that relies on bus topology
that walks the root bus only.

Change-Id: I2883610059bb9fa860bba01179e7d5c58cae00e5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33996
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/soc/intel/apollolake/acpi.c

@@ -186,7 +186,7 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 
 static unsigned long soc_fill_dmar(unsigned long current)
 {
-	struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+	struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 	uint64_t defvtbar = MCHBAR64(DEFVTBAR) & VTBAR_MASK;
 	bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
@@ -219,7 +219,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
 		 * get the info and hide it again when done.
 		 */
 		p2sb_unhide();
-		struct device *p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB);
+		struct device *p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB);
 		uint16_t ibdf = pci_read_config16(p2sb_dev, PCH_P2SB_IBDF);
 		uint16_t hbdf = pci_read_config16(p2sb_dev, PCH_P2SB_HBDF);
 		p2sb_hide();

src/soc/intel/apollolake/chip.c

@@ -256,7 +256,7 @@ static void pcie_update_device_tree(unsigned int devfn0, int num_funcs)
 	int i;
 	unsigned int inc = PCI_DEVFN(0, 1);
 
-	func0 = dev_find_slot(0, devfn0);
+	func0 = pcidev_path_on_root(devfn0);
 	if (func0 == NULL)
 		return;
 
@@ -272,7 +272,7 @@ static void pcie_update_device_tree(unsigned int devfn0, int num_funcs)
 	 * as that port was move to func0.
 	 */
 	for (i = 1; i < num_funcs; i++, devfn += inc) {
-		struct device *dev = dev_find_slot(0, devfn);
+		struct device *dev = pcidev_path_on_root(devfn);
 		if (dev == NULL)
 			continue;
 
@@ -760,7 +760,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *silupd)
 		apl_fsp_silicon_init_params_cb(cfg, silconfig);
 
 	/* Enable xDCI controller if enabled in devicetree and allowed */
-	dev = dev_find_slot(0, PCH_DEVFN_XDCI);
+	dev = pcidev_path_on_root(PCH_DEVFN_XDCI);
 	if (!xdci_can_enable())
 		dev->enabled = 0;
 	silconfig->UsbOtg = dev->enabled;

src/soc/intel/apollolake/include/soc/pci_devs.h

@@ -22,8 +22,8 @@
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
+#define _SA_DEV(slot)		pcidev_path_on_root(_SA_DEVFN(slot))
-#define _PCH_DEV(slot, func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _PCH_DEV(slot, func)	pcidev_path_on_root(_PCH_DEVFN(slot, func))
 #else
 #define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)

src/soc/intel/apollolake/memmap.c

@@ -35,7 +35,7 @@ void *cbmem_top(void)
 	if (!CONFIG(SOC_INTEL_GLK))
 		return tolum;
 
-	dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	dev = pcidev_path_on_root(PCH_DEVFN_LPC);
 	assert(dev != NULL);
 	config = dev->chip_info;
 

src/soc/intel/apollolake/pmutil.c

@@ -149,7 +149,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 	DEVTREE_CONST struct soc_intel_apollolake_config *config;
 
 	/* Look up the device in devicetree */
-	DEVTREE_CONST struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
+	DEVTREE_CONST struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 	if (!dev || !dev->chip_info) {
 		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
 		return;

src/soc/intel/apollolake/romstage.c

@@ -100,7 +100,7 @@ static void soc_early_romstage_init(void)
 /* Thermal throttle activation offset */
 static void configure_thermal_target(void)
 {
-	const struct device *dev = dev_find_slot(0, SA_DEVFN_ROOT);
+	const struct device *dev = pcidev_path_on_root(SA_DEVFN_ROOT);
 	if (!dev) {
 		printk(BIOS_ERR, "Could not find SOC devicetree config\n");
 		return;
@@ -320,7 +320,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
 {
 #if CONFIG(SOC_INTEL_GLK)
 	/* Only for GLK */
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
 	assert(dev != NULL);
 	const config_t *config = dev->chip_info;
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
@@ -350,7 +350,7 @@ static void soc_memory_init_params(FSPM_UPD *mupd)
 static void parse_devicetree_setting(FSPM_UPD *m_upd)
 {
 #if CONFIG(SOC_INTEL_GLK)
-	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_NPK);
+	DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_NPK);
 	if (!dev)
 		return;
 

src/soc/intel/broadwell/acpi.c

@@ -580,7 +580,7 @@ void generate_cpu_entries(struct device *device)
 
 static unsigned long acpi_fill_dmar(unsigned long current)
 {
-	struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+	struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	const u32 gfxvtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
 	const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
 	const bool gfxvten = MCHBAR32(GFXVTBAR) & 0x1;

src/soc/intel/broadwell/include/soc/pci_devs.h

@@ -25,8 +25,8 @@
 #else
 #include <device/device.h>
 #include <device/pci_def.h>
-#define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
+#define _SA_DEV(slot)		pcidev_path_on_root(_SA_DEVFN(slot))
-#define _PCH_DEV(slot, func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _PCH_DEV(slot, func)	pcidev_path_on_root(_PCH_DEVFN(slot, func))
 #endif
 
 /* System Agent Devices */

src/soc/intel/broadwell/romstage/pch.c

@@ -79,7 +79,7 @@ static void pch_enable_lpc(void)
 	const struct device *dev;
 	const config_t *config;
 
-	dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+	dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
 	if (!dev || !dev->chip_info)
 		return;
 	config = dev->chip_info;

src/soc/intel/cannonlake/acpi.c

@@ -293,7 +293,7 @@ int acpigen_soc_clear_tx_gpio(unsigned int gpio_num)
 
 static unsigned long soc_fill_dmar(unsigned long current)
 {
-	struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+	struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	uint64_t gfxvtbar = MCHBAR64(GFXVTBAR) & VTBAR_MASK;
 	bool gfxvten = MCHBAR32(GFXVTBAR) & VTBAR_ENABLED;
 
@@ -306,7 +306,7 @@ static unsigned long soc_fill_dmar(unsigned long current)
 		acpi_dmar_drhd_fixup(tmp, current);
 	}
 
-	struct device *const ipu_dev = dev_find_slot(0, SA_DEVFN_IPU);
+	struct device *const ipu_dev = pcidev_path_on_root(SA_DEVFN_IPU);
 	uint64_t ipuvtbar = MCHBAR64(IPUVTBAR) & VTBAR_MASK;
 	bool ipuvten = MCHBAR32(IPUVTBAR) & VTBAR_ENABLED;
 

src/soc/intel/cannonlake/fsp_params.c

@@ -51,7 +51,7 @@ static uint8_t get_param_value(const config_t *config, uint32_t dev_offset)
 {
 	struct device *dev;
 
-	dev = dev_find_slot(0, serial_io_dev[dev_offset]);
+	dev = pcidev_path_on_root(serial_io_dev[dev_offset]);
 	if (!dev || !dev->enabled)
 		return PCH_SERIAL_IO_INDEX(PchSerialIoDisabled);
 
@@ -178,7 +178,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->PchLockDownRtcMemoryLock = 0;
 
 	/* SATA */
-	dev = dev_find_slot(0, PCH_DEVFN_SATA);
+	dev = pcidev_path_on_root(PCH_DEVFN_SATA);
 	if (!dev)
 		params->SataEnable = 0;
 	else {
@@ -192,7 +192,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	}
 
 	/* Lan */
-	dev = dev_find_slot(0, PCH_DEVFN_GBE);
+	dev = pcidev_path_on_root(PCH_DEVFN_GBE);
 	if (!dev)
 		params->PchLanEnable = 0;
 	else {
@@ -275,7 +275,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	}
 
 	/* Enable xDCI controller if enabled in devicetree and allowed */
-	dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
 	if (dev) {
 		if (!xdci_can_enable())
 			dev->enabled = 0;
@@ -287,7 +287,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	params->SerialIoDebugUartNumber = CONFIG_UART_FOR_CONSOLE;
 
 	/* Enable CNVi Wifi if enabled in device tree */
-	dev = dev_find_slot(0, PCH_DEVFN_CNViWIFI);
+	dev = pcidev_path_on_root(PCH_DEVFN_CNViWIFI);
 #if CONFIG(SOC_INTEL_COMETLAKE)
 	if (dev)
 		params->CnviMode = dev->enabled;
@@ -314,7 +314,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	       sizeof(config->PcieRpHotPlug));
 
 	/* eMMC and SD */
-	dev = dev_find_slot(0, PCH_DEVFN_EMMC);
+	dev = pcidev_path_on_root(PCH_DEVFN_EMMC);
 	if (!dev)
 		params->ScsEmmcEnabled = 0;
 	else {
@@ -329,7 +329,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		}
 	}
 
-	dev = dev_find_slot(0, PCH_DEVFN_SDCARD);
+	dev = pcidev_path_on_root(PCH_DEVFN_SDCARD);
 	if (!dev) {
 		params->ScsSdCardEnabled = 0;
 	} else {
@@ -338,7 +338,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 			CONFIG(MB_HAS_ACTIVE_HIGH_SD_PWR_ENABLE);
 	}
 
-	dev = dev_find_slot(0, PCH_DEVFN_UFS);
+	dev = pcidev_path_on_root(PCH_DEVFN_UFS);
 	if (!dev)
 		params->ScsUfsEnabled = 0;
 	else

src/soc/intel/cannonlake/include/soc/pci_devs.h

@@ -24,8 +24,8 @@
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
+#define _SA_DEV(slot)		pcidev_path_on_root(_SA_DEVFN(slot))
-#define _PCH_DEV(slot, func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _PCH_DEV(slot, func)	pcidev_path_on_root(_PCH_DEVFN(slot, func))
 #else
 #define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)

src/soc/intel/cannonlake/memmap.c

@@ -219,7 +219,7 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size)
 	uintptr_t dram_base;
 	const struct device *dev;
 
-	dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
+	dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0);
 	if (!dev)
 		die_with_post_code(POST_HW_INIT_FAILURE,
 			"ERROR - IGD device not found!");

src/soc/intel/cannonlake/pmutil.c

@@ -177,7 +177,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 	DEVTREE_CONST struct soc_intel_cannonlake_config *config;
 
 	/* Look up the device in devicetree */
-	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
+	DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
 	if (!dev || !dev->chip_info) {
 		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
 		return;

src/soc/intel/cannonlake/romstage/fsp_params.c

@@ -30,7 +30,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 {
 	unsigned int i;
 	uint32_t mask = 0;
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_ISH);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_ISH);
 
 	/* Set IGD stolen size to 64MB. */
 	m_cfg->IgdDvmt50PreAlloc = 2;
@@ -85,7 +85,7 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 		m_cfg->PchIshEnable = dev->enabled;
 
 	/* If HDA is enabled, enable HDA elements */
-	dev = dev_find_slot(0, PCH_DEVFN_HDA);
+	dev = pcidev_path_on_root(PCH_DEVFN_HDA);
 	if (!dev)
 		m_cfg->PchHdaEnable = 0;
 	else
@@ -100,8 +100,8 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg, const config_t *config)
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 {
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
-	const struct device *smbus = dev_find_slot(0, PCH_DEVFN_SMBUS);
+	const struct device *smbus = pcidev_path_on_root(PCH_DEVFN_SMBUS);
 	assert(dev != NULL);
 	const config_t *config = dev->chip_info;
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;

src/soc/intel/cannonlake/smihandler.c

@@ -78,7 +78,7 @@ static void pch_disable_heci(void)
 void smihandler_soc_at_finalize(void)
 {
 	const struct soc_intel_cannonlake_config *config;
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE);
 
 	if (!dev || !dev->chip_info) {
 		printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",

src/soc/intel/denverton_ns/include/soc/pci_devs.h

@@ -27,8 +27,8 @@
 #if ENV_RAMSTAGE
 #include <device/device.h>
 #include <device/pci_def.h>
-#define _SA_DEV(slot) dev_find_slot(0, _SA_DEVFN(slot))
+#define _SA_DEV(slot) pcidev_path_on_root(_SA_DEVFN(slot))
-#define _PCH_DEV(slot, func) dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _PCH_DEV(slot, func) pcidev_path_on_root(_PCH_DEVFN(slot, func))
 #else
 #define _SA_DEV(slot) PCI_DEV(0, SA_DEV_SLOT_##slot, 0)
 #define _PCH_DEV(slot, func) PCI_DEV(0, PCH_DEV_SLOT_##slot, func)

src/soc/intel/denverton_ns/soc_util.c

@@ -37,7 +37,7 @@ pci_devfn_t get_hostbridge_dev(void)
 #else
 struct device *get_hostbridge_dev(void)
 {
-	return dev_find_slot(0, PCI_DEVFN(SA_DEV, SA_FUNC));
+	return pcidev_on_root(SA_DEV, SA_FUNC);
 }
 #endif
 
@@ -49,7 +49,7 @@ pci_devfn_t get_lpc_dev(void)
 #else
 struct device *get_lpc_dev(void)
 {
-	return dev_find_slot(0, PCI_DEVFN(LPC_DEV, LPC_FUNC));
+	return pcidev_on_root(LPC_DEV, LPC_FUNC);
 }
 #endif
 
@@ -61,7 +61,7 @@ pci_devfn_t get_pmc_dev(void)
 #else
 struct device *get_pmc_dev(void)
 {
-	return dev_find_slot(0, PCI_DEVFN(PMC_DEV, PMC_FUNC));
+	return pcidev_on_root(PMC_DEV, PMC_FUNC);
 }
 #endif
 
@@ -73,7 +73,7 @@ pci_devfn_t get_smbus_dev(void)
 #else
 struct device *get_smbus_dev(void)
 {
-	return dev_find_slot(0, PCI_DEVFN(SMBUS_DEV, SMBUS_FUNC));
+	return pcidev_on_root(SMBUS_DEV, SMBUS_FUNC);
 }
 #endif
 

src/soc/intel/denverton_ns/uart.c

@@ -76,7 +76,7 @@ static void hide_hsuarts(void)
 	   last one. */
 	for (i = DENVERTON_UARTS_TO_INI - 1; i >= 0; i--) {
 		struct device *uart_dev;
-		uart_dev = dev_find_slot(0, PCI_DEVFN(HSUART_DEV, i));
+		uart_dev = pcidev_on_root(HSUART_DEV, i);
 		if (uart_dev == NULL)
 			continue;
 		pci_or_config32(uart_dev, PCI_FUNC_RDCFG_HIDE, 1);

src/soc/intel/icelake/include/soc/pci_devs.h

@@ -23,8 +23,8 @@
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
+#define _SA_DEV(slot)		pcidev_path_on_root(_SA_DEVFN(slot))
-#define _PCH_DEV(slot, func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _PCH_DEV(slot, func)	pcidev_path_on_root(_PCH_DEVFN(slot, func))
 #else
 #define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)

src/soc/intel/icelake/memmap.c

@@ -218,7 +218,7 @@ static uintptr_t calculate_dram_base(size_t *reserved_mem_size)
 	uintptr_t dram_base;
 	const struct device *dev;
 
-	dev = dev_find_slot(0, PCI_DEVFN(SA_DEV_SLOT_IGD, 0));
+	dev = pcidev_on_root(SA_DEV_SLOT_IGD, 0);
 	if (!dev)
 		die_with_post_code(POST_HW_INIT_FAILURE,
 				   "ERROR - IGD device not found!");

src/soc/intel/icelake/pmutil.c

@@ -176,7 +176,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 	DEVTREE_CONST struct soc_intel_icelake_config *config;
 
 	/* Look up the device in devicetree */
-	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
+	DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
 	if (!dev || !dev->chip_info) {
 		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
 		return;

src/soc/intel/icelake/smihandler.c

@@ -76,7 +76,7 @@ static void pch_disable_heci(void)
 void smihandler_soc_at_finalize(void)
 {
 	const struct soc_intel_icelake_config *config;
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_CSE);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_CSE);
 
 	if (!dev || !dev->chip_info) {
 		printk(BIOS_ERR, "%s: Could not find SoC devicetree config!\n",

src/soc/intel/skylake/acpi.c

@@ -174,7 +174,7 @@ static int get_cores_per_package(void)
 
 static void acpi_create_gnvs(global_nvs_t *gnvs)
 {
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
 	const struct soc_intel_skylake_config *config = dev->chip_info;
 
 	/* Set unknown wake source */
@@ -561,7 +561,7 @@ void generate_cpu_entries(struct device *device)
 
 static unsigned long acpi_fill_dmar(unsigned long current)
 {
-	struct device *const igfx_dev = dev_find_slot(0, SA_DEVFN_IGD);
+	struct device *const igfx_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	const u32 gfx_vtbar = MCHBAR32(GFXVTBAR) & ~0xfff;
 	const bool gfxvten = MCHBAR32(GFXVTBAR) & 1;
 
@@ -584,7 +584,7 @@ static unsigned long acpi_fill_dmar(unsigned long current)
 		acpi_dmar_rmrr_fixup(tmp, current);
 	}
 
-	struct device *const p2sb_dev = dev_find_slot(0, PCH_DEVFN_P2SB);
+	struct device *const p2sb_dev = pcidev_path_on_root(PCH_DEVFN_P2SB);
 	const u32 vtvc0bar = MCHBAR32(VTVC0BAR) & ~0xfff;
 	const bool vtvc0en = MCHBAR32(VTVC0BAR) & 1;
 
@@ -695,7 +695,7 @@ void southbridge_inject_dsdt(struct device *device)
 /* Save wake source information for calculating ACPI _SWS values */
 int soc_fill_acpi_wake(uint32_t *pm1, uint32_t **gpe0)
 {
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
 	const struct soc_intel_skylake_config *config = dev->chip_info;
 	struct chipset_power_state *ps;
 	static uint32_t gpe0_sts[GPE0_REG_MAX];

src/soc/intel/skylake/chip.c

@@ -92,7 +92,7 @@ struct chip_operations soc_intel_skylake_ops = {
 /* UPD parameters to be initialized before SiliconInit */
 void soc_silicon_init_params(SILICON_INIT_UPD *params)
 {
-	struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
 	const struct soc_intel_skylake_config *config = dev->chip_info;
 	int i;
 
@@ -152,7 +152,7 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 	params->ScsSdCardEnabled = config->ScsSdCardEnabled;
 
 	/* Enable ISH if device is on */
-	dev = dev_find_slot(0, PCH_DEVFN_ISH);
+	dev = pcidev_path_on_root(PCH_DEVFN_ISH);
 	if (dev)
 		params->IshEnable = dev->enabled;
 	else
@@ -219,11 +219,11 @@ void soc_silicon_init_params(SILICON_INIT_UPD *params)
 		fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
 
 	/* Show SPI controller if enabled in devicetree.cb */
-	dev = dev_find_slot(0, PCH_DEVFN_SPI);
+	dev = pcidev_path_on_root(PCH_DEVFN_SPI);
 	params->ShowSpiController = dev->enabled;
 
 	/* Enable xDCI controller if enabled in devicetree and allowed */
-	dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
 	if (!xdci_can_enable())
 		dev->enabled = 0;
 	params->XdciEnable = dev->enabled;

src/soc/intel/skylake/chip_fsp20.c

@@ -102,7 +102,7 @@ static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group,
 
 	for (group = 0; group < pci_groups; group++) {
 		devfn0 = pcie_rp_group[group].devfn;
-		func0 = dev_find_slot(0, devfn0);
+		func0 = pcidev_path_on_root(devfn0);
 		if (func0 == NULL)
 			continue;
 
@@ -119,7 +119,7 @@ static void pcie_update_device_tree(const struct pcie_entry *pcie_rp_group,
 		 */
 		for (i = 1; i < pcie_rp_group[group].func_count;
 				i++, devfn += inc) {
-			struct device *dev = dev_find_slot(0, devfn);
+			struct device *dev = pcidev_path_on_root(devfn);
 			if (dev == NULL || !dev->enabled)
 				continue;
 
@@ -354,7 +354,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 	}
 
 	/* If ISH is enabled, enable ISH elements */
-	dev = dev_find_slot(0, PCH_DEVFN_ISH);
+	dev = pcidev_path_on_root(PCH_DEVFN_ISH);
 	if (dev)
 		params->PchIshEnable = dev->enabled;
 	else
@@ -433,11 +433,11 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 		fill_vr_domain_config(params, i, &config->domain_vr_config[i]);
 
 	/* Show SPI controller if enabled in devicetree.cb */
-	dev = dev_find_slot(0, PCH_DEVFN_SPI);
+	dev = pcidev_path_on_root(PCH_DEVFN_SPI);
 	params->ShowSpiController = dev->enabled;
 
 	/* Enable xDCI controller if enabled in devicetree and allowed */
-	dev = dev_find_slot(0, PCH_DEVFN_USBOTG);
+	dev = pcidev_path_on_root(PCH_DEVFN_USBOTG);
 	if (!xdci_can_enable())
 		dev->enabled = 0;
 	params->XdciEnable = dev->enabled;

src/soc/intel/skylake/include/soc/pci_devs.h

@@ -24,8 +24,8 @@
 
 #if !defined(__SIMPLE_DEVICE__)
 #include <device/device.h>
-#define _SA_DEV(slot)		dev_find_slot(0, _SA_DEVFN(slot))
+#define _SA_DEV(slot)		pcidev_path_on_root(_SA_DEVFN(slot))
-#define _PCH_DEV(slot, func)	dev_find_slot(0, _PCH_DEVFN(slot, func))
+#define _PCH_DEV(slot, func)	pcidev_path_on_root(_PCH_DEVFN(slot, func))
 #else
 #define _SA_DEV(slot)		PCI_DEV(0, SA_DEV_SLOT_ ## slot, 0)
 #define _PCH_DEV(slot, func)	PCI_DEV(0, PCH_DEV_SLOT_ ## slot, func)
@@ -39,7 +39,7 @@
 
 #define SA_DEV_SLOT_PEG		0x01
 #define  SA_DEVFN_PEG(func)	PCI_DEVFN(SA_DEV_SLOT_PEG, func)
-#define  SA_DEV_PEG(func)	dev_find_slot(0, SA_DEVFN_PEG(func))
+#define  SA_DEV_PEG(func)	pcidev_path_on_root(SA_DEVFN_PEG(func))
 #define  SA_DEV_PEG0		SA_DEV_PEG(0)
 #define  SA_DEV_PEG1		SA_DEV_PEG(1)
 #define  SA_DEV_PEG2		SA_DEV_PEG(2)

src/soc/intel/skylake/irq.c

@@ -223,7 +223,7 @@ void soc_irq_settings(FSP_SIL_UPD *params)
 
 	uint32_t i, intdeventry;
 	u8 irq_config[PCH_MAX_IRQ_CONFIG];
-	const struct device *dev = dev_find_slot(0, PCH_DEVFN_LPC);
+	const struct device *dev = pcidev_path_on_root(PCH_DEVFN_LPC);
 	const struct soc_intel_skylake_config *config = dev->chip_info;
 
 	/* Get Device Int Count */

src/soc/intel/skylake/pmutil.c

@@ -178,7 +178,7 @@ void soc_get_gpi_gpe_configs(uint8_t *dw0, uint8_t *dw1, uint8_t *dw2)
 	DEVTREE_CONST struct soc_intel_skylake_config *config;
 
 	/* Look up the device in devicetree */
-	DEVTREE_CONST struct device *dev = dev_find_slot(0, PCH_DEVFN_PMC);
+	DEVTREE_CONST struct device *dev = pcidev_path_on_root(PCH_DEVFN_PMC);
 	if (!dev || !dev->chip_info) {
 		printk(BIOS_ERR, "BUG! Could not find SOC devicetree config\n");
 		return;

src/soc/intel/skylake/romstage/romstage.c

@@ -57,7 +57,7 @@ void soc_memory_init_params(struct romstage_params *params,
 	const struct soc_intel_skylake_config *config;
 
 	/* Set the parameters for MemoryInit */
-	dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+	dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
 	config = dev->chip_info;
 
 	/*

src/soc/intel/skylake/romstage/romstage_fsp20.c

@@ -301,7 +301,7 @@ static void soc_primary_gfx_config_params(FSP_M_CONFIG *m_cfg,
 {
 	const struct device *dev;
 
-	dev = dev_find_slot(0, SA_DEVFN_IGD);
+	dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	if (!dev || !dev->enabled) {
 		/*
 		 * If iGPU is disabled or not defined in the devicetree.cb,
@@ -331,7 +331,7 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	FSP_M_CONFIG *m_cfg = &mupd->FspmConfig;
 	FSP_M_TEST_CONFIG *m_t_cfg = &mupd->FspmTestConfig;
 
-	dev = dev_find_slot(0, PCI_DEVFN(PCH_DEV_SLOT_LPC, 0));
+	dev = pcidev_on_root(PCH_DEV_SLOT_LPC, 0);
 	config = dev->chip_info;
 
 	soc_memory_init_params(m_cfg, config);

src/soc/intel/skylake/romstage/systemagent.c

@@ -26,8 +26,8 @@
 
 static void systemagent_vtd_init(void)
 {
-	const struct device *const root_dev = dev_find_slot(0, SA_DEVFN_ROOT);
+	const struct device *const root_dev = pcidev_path_on_root(SA_DEVFN_ROOT);
-	const struct device *const igd_dev = dev_find_slot(0, SA_DEVFN_IGD);
+	const struct device *const igd_dev = pcidev_path_on_root(SA_DEVFN_IGD);
 	const struct soc_intel_skylake_config *config = NULL;
 
 	if (root_dev)