From 90857b7381d6fcccc9a03757f2b22de64baf0785 Mon Sep 17 00:00:00 2001 From: Nicholas Chin Date: Tue, 13 Feb 2024 21:16:24 +0100 Subject: [PATCH] mb/asrock: Add Z87E-ITX (Haswell) This was done using Haswell autoport, with manual fixes to get the output to build against current main. I do not physically have this board; I was sent the output of autoport with some fixes on top of which I added additional changes. The VBT was copied from /sys/kernel/debug/dri/0/i915_vbt on version 2.70 of the vendor firmware. The flash chip is 8MiB in a socketed DIP8 package, making it easy to externally flash to recover from a brick. Working: - Haswell MRC.bin - S3 suspend and resume - Libgfxinit - HDMI - DVI-I (including passive DVI to VGA adapter) - DisplayPort - SATA ports - mSATA SSD - mPCIe WiFi slot - Rear USB ports - USB 3.0 header - Audio header - Ethernet - x16 PCIe slot - EHCI debug with the CH347 (top USB 2.0 port by the PS/2 connector) - edk2 (MrChromebox uefipayload_202309) Not Tested: - PS/2 keyboard/mouse - eSATA - USB 2.0 header Change-Id: I56c22d8f5505f9a4da25f8b4406b00978af1a586 Signed-off-by: Nicholas Chin Reviewed-on: https://review.coreboot.org/c/coreboot/+/81022 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/asrock/z87e-itx/Kconfig | 27 +++ src/mainboard/asrock/z87e-itx/Kconfig.name | 4 + src/mainboard/asrock/z87e-itx/Makefile.mk | 5 + src/mainboard/asrock/z87e-itx/acpi/ec.asl | 3 + .../asrock/z87e-itx/acpi/platform.asl | 10 + .../asrock/z87e-itx/acpi/superio.asl | 3 + src/mainboard/asrock/z87e-itx/board_info.txt | 7 + src/mainboard/asrock/z87e-itx/bootblock.c | 23 +++ src/mainboard/asrock/z87e-itx/data.vbt | Bin 0 -> 6144 bytes src/mainboard/asrock/z87e-itx/devicetree.cb | 132 +++++++++++++ src/mainboard/asrock/z87e-itx/dsdt.asl | 27 +++ .../asrock/z87e-itx/gma-mainboard.ads | 19 ++ src/mainboard/asrock/z87e-itx/gpio.c | 183 ++++++++++++++++++ src/mainboard/asrock/z87e-itx/hda_verb.c | 24 +++ src/mainboard/asrock/z87e-itx/romstage.c | 42 ++++ 15 files changed, 509 insertions(+) create mode 100644 src/mainboard/asrock/z87e-itx/Kconfig create mode 100644 src/mainboard/asrock/z87e-itx/Kconfig.name create mode 100644 src/mainboard/asrock/z87e-itx/Makefile.mk create mode 100644 src/mainboard/asrock/z87e-itx/acpi/ec.asl create mode 100644 src/mainboard/asrock/z87e-itx/acpi/platform.asl create mode 100644 src/mainboard/asrock/z87e-itx/acpi/superio.asl create mode 100644 src/mainboard/asrock/z87e-itx/board_info.txt create mode 100644 src/mainboard/asrock/z87e-itx/bootblock.c create mode 100644 src/mainboard/asrock/z87e-itx/data.vbt create mode 100644 src/mainboard/asrock/z87e-itx/devicetree.cb create mode 100644 src/mainboard/asrock/z87e-itx/dsdt.asl create mode 100644 src/mainboard/asrock/z87e-itx/gma-mainboard.ads create mode 100644 src/mainboard/asrock/z87e-itx/gpio.c create mode 100644 src/mainboard/asrock/z87e-itx/hda_verb.c create mode 100644 src/mainboard/asrock/z87e-itx/romstage.c diff --git a/src/mainboard/asrock/z87e-itx/Kconfig b/src/mainboard/asrock/z87e-itx/Kconfig new file mode 100644 index 0000000000..9eebc90e68 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/Kconfig @@ -0,0 +1,27 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +if BOARD_ASROCK_Z87E_ITX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select BOARD_ROMSIZE_KB_8192 + select GFX_GMA_ANALOG_I2C_HDMI_B + select HAVE_ACPI_RESUME + select HAVE_ACPI_TABLES + select INTEL_GMA_HAVE_VBT + select MAINBOARD_HAS_LIBGFXINIT + select MAINBOARD_USES_IFD_GBE_REGION + select NORTHBRIDGE_INTEL_HASWELL + select SERIRQ_CONTINUOUS_MODE + select SOUTHBRIDGE_INTEL_LYNXPOINT + select SUPERIO_NUVOTON_NCT6776 + +config MAINBOARD_DIR + default "asrock/z87e-itx" + +config MAINBOARD_PART_NUMBER + default "Z87E-ITX" + +config USBDEBUG_HCD_INDEX + default 1 # This is the top most of the USB-2.0-only ports +endif diff --git a/src/mainboard/asrock/z87e-itx/Kconfig.name b/src/mainboard/asrock/z87e-itx/Kconfig.name new file mode 100644 index 0000000000..f152649b5c --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/Kconfig.name @@ -0,0 +1,4 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +config BOARD_ASROCK_Z87E_ITX + bool "Z87E-ITX" diff --git a/src/mainboard/asrock/z87e-itx/Makefile.mk b/src/mainboard/asrock/z87e-itx/Makefile.mk new file mode 100644 index 0000000000..058a390189 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/Makefile.mk @@ -0,0 +1,5 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +bootblock-y += bootblock.c +romstage-y += gpio.c +ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads diff --git a/src/mainboard/asrock/z87e-itx/acpi/ec.asl b/src/mainboard/asrock/z87e-itx/acpi/ec.asl new file mode 100644 index 0000000000..16990d45f4 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/acpi/ec.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: CC-PDDC */ + +/* Please update the license if adding licensable material. */ diff --git a/src/mainboard/asrock/z87e-itx/acpi/platform.asl b/src/mainboard/asrock/z87e-itx/acpi/platform.asl new file mode 100644 index 0000000000..aff432b6f4 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/acpi/platform.asl @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +Method(_WAK, 1) +{ + Return(Package() {0, 0}) +} + +Method(_PTS, 1) +{ +} diff --git a/src/mainboard/asrock/z87e-itx/acpi/superio.asl b/src/mainboard/asrock/z87e-itx/acpi/superio.asl new file mode 100644 index 0000000000..ee2eabeb75 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/acpi/superio.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include diff --git a/src/mainboard/asrock/z87e-itx/board_info.txt b/src/mainboard/asrock/z87e-itx/board_info.txt new file mode 100644 index 0000000000..4b2f887d5e --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/board_info.txt @@ -0,0 +1,7 @@ +Category: desktop +Board URL: https://www.asrock.com/mb/intel/z87e-itx/ +ROM protocol: SPI +Flashrom support: y +ROM package: DIP-8 +ROM socketed: y +Release year: 2013 diff --git a/src/mainboard/asrock/z87e-itx/bootblock.c b/src/mainboard/asrock/z87e-itx/bootblock.c new file mode 100644 index 0000000000..a64cdfb723 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/bootblock.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include + +void mainboard_config_superio(void) +{ + const pnp_devfn_t GLOBAL_PSEUDO_DEV = PNP_DEV(0x2e, 0); + const pnp_devfn_t SERIAL_DEV = PNP_DEV(0x2e, NCT6776_SP1); + const pnp_devfn_t ACPI_DEV = PNP_DEV(0x2e, NCT6776_ACPI); + + nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); + + nuvoton_pnp_enter_conf_state(GLOBAL_PSEUDO_DEV); + + /* Power RAM in S3 and let the PCH handle power failure actions. */ + pnp_set_logical_device(ACPI_DEV); + pnp_write_config(ACPI_DEV, 0xe4, 0x70); + + nuvoton_pnp_exit_conf_state(GLOBAL_PSEUDO_DEV); +} diff --git a/src/mainboard/asrock/z87e-itx/data.vbt b/src/mainboard/asrock/z87e-itx/data.vbt new file mode 100644 index 0000000000000000000000000000000000000000..4bb86662ce3fbb2ab2545e9c266a4d6114827ced GIT binary patch literal 6144 zcmeHKUu+a*5TEaM?{05z_inpIIF8Z`$e(NNpY2hbT5H^EuXtCE_WFlX36U1=P(p!H zim3^)r&fe$$R!#?gQPDeg!q6lA--sc57?+7ga3-K&O5IW)YCqN})p;FyLcNqWgSmOLq6|h{yV4JK9p+?VIp@ zSPI9q+t&dyj4f574bexF`^U2*k=`my^lin>2X^im$=1iShxU#i7{zpZ5@Wk|Wk<4O z!{gZu_6SnFzOqk^--gt0qIdoV{^*} zLzUwl?cJNx$yBUA+1-WRy%Hn*jo#&mCYBH5Pg?})2%aUbmmMqe1)^Xzlu z7-_G(d(?pMKE9k{;Zr}xmBm!BNrGWXheL!{ z32zfVkYu<(xJdYd@HOE(!cT;s30|KJWrP)kwS;=YV}y3XX2Mp&Fkvs@FkzB#obV>$ zJ%Z;j+$y+o6nsuO=I}C`gC@d>D#)F7^rs!Y?}l}xAUoXeaLY*vw?e_|h1-S86pMoN z1Ydzk9w>Y)?s!T#JY{h~NITCXl(_t?S)b2E#=ogRw%IsWerlyc~#<|0U~Q+7UX0Vuqt3NQh3 zzz1x#XB)iesfFO{K&gJ;$Y(XclHF@l)NgrzF#)JKQcq+eZ;?y_X3`@-DnxoDf@A`c z62T;yrkKETK&@VsKr}&gfy68`>k%1CE-)FG61OJf&nsoE?2Ox>%t$HKL1C$MA+QX{1Kv4V`_3LrJ+~vn{zkbv&=lyuWuh019tA6~&ugi+O zM8OtCPbu<%f=3kngd(3(@KZ&L*osTE$DM{*5Ys zuc8#t!vT3s06PQv_JF)QfNuo!GXeQ*051ph*?@dKfLc&r9h7T=YV{2<=bB}?GD>wy zC}~Wggcx)w7Qe|f;_l#j`tHt;B;}x!mnaOn?(JbZh|n-tfsx!2J0z7&lP-!EkwPgf z+}p$aqT;n-*8%;k6uF1i1$QyO2zgD}^)ulPm*imrd%~Kj&6P2)MXRMNrFocN_S}Q@ zn^rMB=Sx__{5HY6fYrT}0e2~p+`VexTn|(l8}rUtgea1EtHsk&N{Pdfy8QG|xY9Jx zX>fF!VxB%7becJDDZ7ZY=B7u_KTIB~`78kP;LgijQl{NgCFH}qRnu2`rdAv2cb4&4 zmInd+T%t&p;=!mkXNIOSMySWi0mp;Y1^#JH(k=v0tu=rfOW4KrFifX$nV}f%e3re2 zJk_HW$!04b7OqWKOD=Sj zJuqgE90X6NwjKu0b + +DefinitionBlock( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x20141018 /* OEM revision */ +) +{ + #include + #include "acpi/platform.asl" + #include + #include + /* global NVS and variables. */ + #include + #include + + Device (\_SB.PCI0) + { + #include + #include + } +} diff --git a/src/mainboard/asrock/z87e-itx/gma-mainboard.ads b/src/mainboard/asrock/z87e-itx/gma-mainboard.ads new file mode 100644 index 0000000000..cd05ae2fb8 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/gma-mainboard.ads @@ -0,0 +1,19 @@ +-- SPDX-License-Identifier: GPL-2.0-or-later + +with HW.GFX.GMA; +with HW.GFX.GMA.Display_Probing; + +use HW.GFX.GMA; +use HW.GFX.GMA.Display_Probing; + +private package GMA.Mainboard is + + ports : constant Port_List := + (DP2, -- DP + HDMI1, -- DVI-I + HDMI2, -- DP + HDMI3, -- HDMI + Analog, -- DVI-I + others => Disabled); + +end GMA.Mainboard; diff --git a/src/mainboard/asrock/z87e-itx/gpio.c b/src/mainboard/asrock/z87e-itx/gpio.c new file mode 100644 index 0000000000..ff9a21db35 --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/gpio.c @@ -0,0 +1,183 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +static const struct pch_gpio_set1 pch_gpio_set1_mode = { + .gpio0 = GPIO_MODE_GPIO, + .gpio1 = GPIO_MODE_GPIO, + .gpio2 = GPIO_MODE_NATIVE, + .gpio3 = GPIO_MODE_NATIVE, + .gpio4 = GPIO_MODE_NATIVE, + .gpio5 = GPIO_MODE_NATIVE, + .gpio6 = GPIO_MODE_GPIO, + .gpio7 = GPIO_MODE_GPIO, + .gpio8 = GPIO_MODE_NATIVE, + .gpio9 = GPIO_MODE_NATIVE, + .gpio10 = GPIO_MODE_NATIVE, + .gpio11 = GPIO_MODE_NATIVE, + .gpio12 = GPIO_MODE_NATIVE, + .gpio13 = GPIO_MODE_GPIO, + .gpio14 = GPIO_MODE_NATIVE, + .gpio15 = GPIO_MODE_GPIO, + .gpio16 = GPIO_MODE_NATIVE, + .gpio17 = GPIO_MODE_GPIO, + .gpio18 = GPIO_MODE_NATIVE, + .gpio19 = GPIO_MODE_NATIVE, + .gpio20 = GPIO_MODE_NATIVE, + .gpio21 = GPIO_MODE_NATIVE, + .gpio22 = GPIO_MODE_NATIVE, + .gpio23 = GPIO_MODE_NATIVE, + .gpio24 = GPIO_MODE_GPIO, + .gpio25 = GPIO_MODE_NATIVE, + .gpio26 = GPIO_MODE_NATIVE, + .gpio27 = GPIO_MODE_GPIO, + .gpio28 = GPIO_MODE_GPIO, + .gpio29 = GPIO_MODE_NATIVE, + .gpio30 = GPIO_MODE_NATIVE, + .gpio31 = GPIO_MODE_GPIO, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_direction = { + .gpio0 = GPIO_DIR_INPUT, + .gpio1 = GPIO_DIR_INPUT, + .gpio6 = GPIO_DIR_INPUT, + .gpio7 = GPIO_DIR_INPUT, + .gpio13 = GPIO_DIR_INPUT, + .gpio15 = GPIO_DIR_OUTPUT, + .gpio17 = GPIO_DIR_INPUT, + .gpio24 = GPIO_DIR_OUTPUT, + .gpio27 = GPIO_DIR_INPUT, + .gpio28 = GPIO_DIR_OUTPUT, + .gpio31 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_level = { + .gpio15 = GPIO_LEVEL_LOW, + .gpio24 = GPIO_LEVEL_LOW, + .gpio28 = GPIO_LEVEL_LOW, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_reset = { + .gpio8 = GPIO_RESET_RSMRST, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_invert = { + .gpio13 = GPIO_INVERT, +}; + +static const struct pch_gpio_set1 pch_gpio_set1_blink = { +}; + +static const struct pch_gpio_set2 pch_gpio_set2_mode = { + .gpio32 = GPIO_MODE_GPIO, + .gpio33 = GPIO_MODE_GPIO, + .gpio34 = GPIO_MODE_GPIO, + .gpio35 = GPIO_MODE_GPIO, + .gpio36 = GPIO_MODE_NATIVE, + .gpio37 = GPIO_MODE_NATIVE, + .gpio38 = GPIO_MODE_NATIVE, + .gpio39 = GPIO_MODE_NATIVE, + .gpio40 = GPIO_MODE_NATIVE, + .gpio41 = GPIO_MODE_NATIVE, + .gpio42 = GPIO_MODE_NATIVE, + .gpio43 = GPIO_MODE_NATIVE, + .gpio44 = GPIO_MODE_NATIVE, + .gpio45 = GPIO_MODE_GPIO, + .gpio46 = GPIO_MODE_NATIVE, + .gpio47 = GPIO_MODE_NATIVE, + .gpio48 = GPIO_MODE_NATIVE, + .gpio49 = GPIO_MODE_GPIO, + .gpio50 = GPIO_MODE_GPIO, + .gpio51 = GPIO_MODE_GPIO, + .gpio52 = GPIO_MODE_GPIO, + .gpio53 = GPIO_MODE_GPIO, + .gpio54 = GPIO_MODE_GPIO, + .gpio55 = GPIO_MODE_GPIO, + .gpio56 = GPIO_MODE_NATIVE, + .gpio57 = GPIO_MODE_GPIO, + .gpio58 = GPIO_MODE_NATIVE, + .gpio59 = GPIO_MODE_NATIVE, + .gpio60 = GPIO_MODE_NATIVE, + .gpio61 = GPIO_MODE_NATIVE, + .gpio62 = GPIO_MODE_NATIVE, + .gpio63 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_direction = { + .gpio32 = GPIO_DIR_OUTPUT, + .gpio33 = GPIO_DIR_OUTPUT, + .gpio34 = GPIO_DIR_INPUT, + .gpio35 = GPIO_DIR_OUTPUT, + .gpio45 = GPIO_DIR_OUTPUT, + .gpio49 = GPIO_DIR_INPUT, + .gpio50 = GPIO_DIR_INPUT, + .gpio51 = GPIO_DIR_OUTPUT, + .gpio52 = GPIO_DIR_INPUT, + .gpio53 = GPIO_DIR_OUTPUT, + .gpio54 = GPIO_DIR_INPUT, + .gpio55 = GPIO_DIR_OUTPUT, + .gpio57 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_level = { + .gpio32 = GPIO_LEVEL_HIGH, + .gpio33 = GPIO_LEVEL_HIGH, + .gpio35 = GPIO_LEVEL_LOW, + .gpio45 = GPIO_LEVEL_HIGH, + .gpio51 = GPIO_LEVEL_HIGH, + .gpio53 = GPIO_LEVEL_HIGH, + .gpio55 = GPIO_LEVEL_HIGH, +}; + +static const struct pch_gpio_set2 pch_gpio_set2_reset = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_mode = { + .gpio64 = GPIO_MODE_NATIVE, + .gpio65 = GPIO_MODE_NATIVE, + .gpio66 = GPIO_MODE_NATIVE, + .gpio67 = GPIO_MODE_NATIVE, + .gpio68 = GPIO_MODE_GPIO, + .gpio69 = GPIO_MODE_GPIO, + .gpio70 = GPIO_MODE_NATIVE, + .gpio71 = GPIO_MODE_NATIVE, + .gpio72 = GPIO_MODE_GPIO, + .gpio73 = GPIO_MODE_NATIVE, + .gpio74 = GPIO_MODE_NATIVE, + .gpio75 = GPIO_MODE_NATIVE, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_direction = { + .gpio68 = GPIO_DIR_INPUT, + .gpio69 = GPIO_DIR_INPUT, + .gpio72 = GPIO_DIR_INPUT, +}; + +static const struct pch_gpio_set3 pch_gpio_set3_level = { +}; + +static const struct pch_gpio_set3 pch_gpio_set3_reset = { +}; + +const struct pch_gpio_map mainboard_gpio_map = { + .set1 = { + .mode = &pch_gpio_set1_mode, + .direction = &pch_gpio_set1_direction, + .level = &pch_gpio_set1_level, + .blink = &pch_gpio_set1_blink, + .invert = &pch_gpio_set1_invert, + .reset = &pch_gpio_set1_reset, + }, + .set2 = { + .mode = &pch_gpio_set2_mode, + .direction = &pch_gpio_set2_direction, + .level = &pch_gpio_set2_level, + .reset = &pch_gpio_set2_reset, + }, + .set3 = { + .mode = &pch_gpio_set3_mode, + .direction = &pch_gpio_set3_direction, + .level = &pch_gpio_set3_level, + .reset = &pch_gpio_set3_reset, + }, +}; diff --git a/src/mainboard/asrock/z87e-itx/hda_verb.c b/src/mainboard/asrock/z87e-itx/hda_verb.c new file mode 100644 index 0000000000..8330dcdede --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/hda_verb.c @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include + +const u32 cim_verb_data[] = { + 0x10ec0900, /* Codec Vendor / Device ID: Realtek */ + 0x18491150, /* Subsystem ID */ + 11, /* Number of 4 dword sets */ + AZALIA_SUBVENDOR(0, 0x18491150), + AZALIA_PIN_CFG(0, 0x11, 0x40000000), + AZALIA_PIN_CFG(0, 0x14, 0x01014010), + AZALIA_PIN_CFG(0, 0x15, 0x01011012), + AZALIA_PIN_CFG(0, 0x16, 0x01016011), + AZALIA_PIN_CFG(0, 0x17, 0x411111f0), + AZALIA_PIN_CFG(0, 0x18, 0x01a19040), + AZALIA_PIN_CFG(0, 0x19, 0x02a19050), + AZALIA_PIN_CFG(0, 0x1a, 0x0181304f), + AZALIA_PIN_CFG(0, 0x1b, 0x02214020), + AZALIA_PIN_CFG(0, 0x1e, 0x01451130), +}; + +const u32 pc_beep_verbs[0] = {}; + +AZALIA_ARRAY_SIZES; diff --git a/src/mainboard/asrock/z87e-itx/romstage.c b/src/mainboard/asrock/z87e-itx/romstage.c new file mode 100644 index 0000000000..b50390e67c --- /dev/null +++ b/src/mainboard/asrock/z87e-itx/romstage.c @@ -0,0 +1,42 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include + +void mainboard_config_rcba(void) +{ +} + +void mb_get_spd_map(struct spd_info *spdi) +{ + spdi->addresses[0] = 0x50; + spdi->addresses[2] = 0x52; +} + +const struct usb2_port_config mainboard_usb2_ports[MAX_USB2_PORTS] = { + /* Length, Enable, OCn#, Location */ + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 0, USB_PORT_FLEX }, + { 0x0040, 1, 1, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, USB_OC_PIN_SKIP, USB_PORT_FLEX }, + { 0x0040, 1, 2, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 3, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 4, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 5, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, + { 0x0040, 1, 6, USB_PORT_FLEX }, +}; + +const struct usb3_port_config mainboard_usb3_ports[MAX_USB3_PORTS] = { + { 1, 0 }, + { 1, 0 }, + { 1, 1 }, + { 1, 1 }, + { 1, 2 }, + { 1, 2 }, +};