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soc/intel/apollolake: Hook up UfsEnabled to devicetree

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Hook up FSP S UfsEnabled UPD (1d.0) to devicetree.

UFS only exist on GLK, and has been there since its
initial releases.

Signed-off-by: Sean Rhodes <sean@starlabs.systems>
Change-Id: I1976bfd340c728c64aaf36d296ac41dcd47bfc61
Reviewed-on: https://review.coreboot.org/c/coreboot/+/65044
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Sean Rhodes
2022-06-08 21:41:53 +01:00
committed by Felix Held
parent ae64b6e5db
commit 9088b681f5
4 changed files with 9 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/octopus/variants/baseboard/devicetree.cb
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@@ -263,6 +263,7 @@ chip soc/intel/apollolake
device pci 19.2 on end # - SPI 2 device pci 19.2 on end # - SPI 2
device pci 1a.0 on end # - PWM device pci 1a.0 on end # - PWM
device pci 1c.0 on end # - eMMC device pci 1c.0 on end # - eMMC
device pci 1d.0 on end # - UFS
device pci 1e.0 off end # - SDIO device pci 1e.0 off end # - SDIO
device pci 1f.0 on device pci 1f.0 on
chip ec/google/chromeec chip ec/google/chromeec

1
src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb
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@@ -177,6 +177,7 @@ chip soc/intel/apollolake
device pci 1a.0 on end # - PWM device pci 1a.0 on end # - PWM
device pci 1b.0 on end # - SDCARD device pci 1b.0 on end # - SDCARD
device pci 1c.0 on end # - eMMC device pci 1c.0 on end # - eMMC
device pci 1d.0 on end # - UFS
device pci 1e.0 off end # - SDIO device pci 1e.0 off end # - SDIO
device pci 1f.0 on # - LPC device pci 1f.0 on # - LPC
chip drivers/pc80/tpm chip drivers/pc80/tpm

3
src/soc/intel/apollolake/chip.c
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@@ -449,6 +449,9 @@ static void disable_dev(struct device *dev, FSP_S_CONFIG *silconfig)
case PCH_DEVFN_CNVI: case PCH_DEVFN_CNVI:
silconfig->CnviMode = 0; silconfig->CnviMode = 0;
break; break;
case PCH_DEVFN_UFS:
silconfig->UfsEnabled = 0;
break;
#endif #endif
case PCH_DEVFN_HDA: case PCH_DEVFN_HDA:
silconfig->HdaEnable = 0; silconfig->HdaEnable = 0;

4
src/soc/intel/apollolake/include/soc/pci_devs.h
View File

@@ -148,6 +148,10 @@
#define PCH_DEVFN_EMMC _PCH_DEVFN(EMMC, 0) #define PCH_DEVFN_EMMC _PCH_DEVFN(EMMC, 0)
#define PCH_DEV_EMMC _PCH_DEV(EMMC, 0) #define PCH_DEV_EMMC _PCH_DEV(EMMC, 0)
#define PCH_DEV_SLOT_UFS 0x1d
#define PCH_DEVFN_UFS _PCH_DEVFN(UFS, 0)
#define PCH_DEV_UFS _PCH_DEV(UFS, 0)
#define PCH_DEV_SLOT_SDIO 0x1e #define PCH_DEV_SLOT_SDIO 0x1e
#define PCH_DEVFN_SDIO _PCH_DEVFN(SDIO, 0) #define PCH_DEVFN_SDIO _PCH_DEVFN(SDIO, 0)
#define PCH_DEV_SDIO _PCH_DEV(SDIO, 0) #define PCH_DEV_SDIO _PCH_DEV(SDIO, 0)