mainboard/intel: Add Mohon Peak CRB for Intel's atom c2000
Add the Mohon Peak CRB. Updates to come. Change-Id: I0a8496d502bab905c6f35eff9fcd7eda266831ed Signed-off-by: Martin Roth <gaumless@gmail.com> Reviewed-on: http://review.coreboot.org/6371 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Martin Roth
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src/mainboard/intel/mohonpeak/gpio.h
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178
src/mainboard/intel/mohonpeak/gpio.h
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2011 The Chromium OS Authors. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef MOHONPEAK_GPIO_H
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#define MOHONPEAK_GPIO_H
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#include "southbridge/intel/fsp_rangeley/gpio.h"
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/* Core GPIO */
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const struct soc_gpio soc_gpio_mode = {
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.gpio15 = GPIO_MODE_GPIO, /* Board ID GPIO */
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.gpio17 = GPIO_MODE_GPIO, /* Board ID GPIO */
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};
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const struct soc_gpio soc_gpio_direction = {
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.gpio15 = GPIO_DIR_INPUT, /* Board ID GPIO */
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.gpio17 = GPIO_DIR_INPUT, /* Board ID GPIO */
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};
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const struct soc_gpio soc_gpio_level = {
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};
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const struct soc_gpio soc_gpio_tpe = {
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};
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const struct soc_gpio soc_gpio_tne = {
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};
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const struct soc_gpio soc_gpio_ts = {
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};
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/* Keep the CFIO struct in register order, not gpio order. */
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const struct soc_cfio soc_cfio_core[] = {
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{ 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_28 */
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{ 0x8000, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_27 */
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{ 0x8500, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_26 */
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{ 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_21 */
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{ 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_22 */
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{ 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_23 */
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{ 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO gpios_25 */
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{ 0x8480, 0x0000, 0x0002, 0x040c }, /* CFIO gpios_24 */
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{ 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_19 */
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{ 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_20 */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_18 */
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{ 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_17 */
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{ 0x80c028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_7 */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_4 */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_5 */
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{ 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_6 */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_1 */
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{ 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_2 */
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{ 0xc028, 0x20002, 0x0004, 0x040c }, /* CFIO gpios_3 */
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{ 0xc528, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_0 */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_10 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_13 */
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{ 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_14 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_11 */
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{ 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_8 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_9 */
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{ 0xc4a8, 0x30003, 0x0000, 0x040c }, /* CFIO gpios_12 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_29 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_30 */
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{ 0x04a9, 0x30003, 0x0002, 0x040c }, /* CFIO gpios_15 */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO gpios_16 */
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};
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/* SUS GPIO */
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const struct soc_gpio soc_gpio_sus_mode = {
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.gpio2 = GPIO_MODE_GPIO,
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};
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const struct soc_gpio soc_gpio_sus_direction = {
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.gpio2 = GPIO_DIR_INPUT,
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};
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const struct soc_gpio soc_gpio_sus_level = {
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};
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const struct soc_gpio soc_gpio_sus_tpe = {
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};
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const struct soc_gpio soc_gpio_sus_tne = {
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};
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const struct soc_gpio soc_gpio_sus_ts = {
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};
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const struct soc_gpio soc_gpio_sus_we = {
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};
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/* Keep the CFIO struct in register order, not gpio order. */
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const struct soc_cfio soc_cfio_sus[] = {
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_21 */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_20 */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_19 */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_22 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_17 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_18 */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_14 */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_13 */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_15 */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_16 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_25 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_24 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_26 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_27 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_23 */
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{ 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_2 */
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{ 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_1 */
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{ 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_7 */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_3 */
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{ 0xc4a8, 0x30003, 0x0003, 0x040c }, /* CFIO SUS gpios_0 */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0x8000, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_12 */
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{ 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_6 */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_10 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_9 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_8 */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0x8050, 0x0000, 0x0004, 0x040c }, /* CFIO SUS gpios_4 */
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{ 0xc4a8, 0x30003, 0x0002, 0x040c }, /* CFIO SUS gpios_11 */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0x0000, 0x0000, 0x0000, 0x0000 }, /* CFIO Reserved */
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{ 0xc028, 0x30003, 0x0004, 0x040c }, /* CFIO SUS gpios_5 */
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};
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const struct soc_gpio_map gpio_map = {
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.core = {
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.mode = &soc_gpio_mode,
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.direction = &soc_gpio_direction,
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.level = &soc_gpio_level,
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.tpe = &soc_gpio_tpe,
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.tne = &soc_gpio_tne,
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.ts = &soc_gpio_ts,
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.cfio_init = &soc_cfio_core[0],
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.cfio_entrynum = sizeof(soc_cfio_core) / sizeof(struct soc_cfio),
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},
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.sus = {
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.mode = &soc_gpio_sus_mode,
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.direction = &soc_gpio_sus_direction,
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.level = &soc_gpio_sus_level,
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.tpe = &soc_gpio_sus_tpe,
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.tne = &soc_gpio_sus_tne,
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.ts = &soc_gpio_sus_ts,
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.we = &soc_gpio_sus_we,
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.cfio_init = &soc_cfio_sus[0],
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.cfio_entrynum = sizeof(soc_cfio_sus) / sizeof(struct soc_cfio),
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},
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};
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#endif
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