diff --git a/src/mainboard/system76/addw2/devicetree.cb b/src/mainboard/system76/addw2/devicetree.cb
index e561607cee..f348e7d807 100644
--- a/src/mainboard/system76/addw2/devicetree.cb
+++ b/src/mainboard/system76/addw2/devicetree.cb
@@ -29,7 +29,7 @@ chip soc/intel/cannonlake
 		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
 		.tdp_pl1_override = 45,
 		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
-		.tdp_pl2_override = 68,
+		.tdp_pl2_override = 90,
 	}"
 
 	# Enable "Intel Speed Shift Technology"
diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb
index 10d7f1d02a..c50577707e 100644
--- a/src/mainboard/system76/gaze15/devicetree.cb
+++ b/src/mainboard/system76/gaze15/devicetree.cb
@@ -29,7 +29,7 @@ chip soc/intel/cannonlake
 		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
 		.tdp_pl1_override = 45,
 		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
-		.tdp_pl2_override = 68,
+		.tdp_pl2_override = 90,
 	}"
 
 	# Enable "Intel Speed Shift Technology"
diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb
index 092338ac6f..ea8e0b4093 100644
--- a/src/mainboard/system76/oryp6/devicetree.cb
+++ b/src/mainboard/system76/oryp6/devicetree.cb
@@ -29,7 +29,7 @@ chip soc/intel/cannonlake
 		// /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw
 		.tdp_pl1_override = 45,
 		// /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw
-		.tdp_pl2_override = 68,
+		.tdp_pl2_override = 90,
 	}"
 
 	# Enable "Intel Speed Shift Technology"