From 90a93a8a32297c886d1dfc0247ada14a3aed2b27 Mon Sep 17 00:00:00 2001 From: Jeremy Soller Date: Wed, 17 Jun 2020 11:52:14 -0600 Subject: [PATCH] Update cml-h pl2 to 90W Change-Id: Ibc1c142c4191334308eb02c5dee65d38c51b34e8 --- src/mainboard/system76/addw2/devicetree.cb | 2 +- src/mainboard/system76/gaze15/devicetree.cb | 2 +- src/mainboard/system76/oryp6/devicetree.cb | 2 +- 3 files changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/system76/addw2/devicetree.cb b/src/mainboard/system76/addw2/devicetree.cb index e561607cee..f348e7d807 100644 --- a/src/mainboard/system76/addw2/devicetree.cb +++ b/src/mainboard/system76/addw2/devicetree.cb @@ -29,7 +29,7 @@ chip soc/intel/cannonlake // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw .tdp_pl1_override = 45, // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw - .tdp_pl2_override = 68, + .tdp_pl2_override = 90, }" # Enable "Intel Speed Shift Technology" diff --git a/src/mainboard/system76/gaze15/devicetree.cb b/src/mainboard/system76/gaze15/devicetree.cb index 10d7f1d02a..c50577707e 100644 --- a/src/mainboard/system76/gaze15/devicetree.cb +++ b/src/mainboard/system76/gaze15/devicetree.cb @@ -29,7 +29,7 @@ chip soc/intel/cannonlake // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw .tdp_pl1_override = 45, // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw - .tdp_pl2_override = 68, + .tdp_pl2_override = 90, }" # Enable "Intel Speed Shift Technology" diff --git a/src/mainboard/system76/oryp6/devicetree.cb b/src/mainboard/system76/oryp6/devicetree.cb index 092338ac6f..ea8e0b4093 100644 --- a/src/mainboard/system76/oryp6/devicetree.cb +++ b/src/mainboard/system76/oryp6/devicetree.cb @@ -29,7 +29,7 @@ chip soc/intel/cannonlake // /sys/class/powercap/intel-rapl:0/constraint_0_power_limit_uw .tdp_pl1_override = 45, // /sys/class/powercap/intel-rapl:0/constraint_1_power_limit_uw - .tdp_pl2_override = 68, + .tdp_pl2_override = 90, }" # Enable "Intel Speed Shift Technology"