Add initial inteltool support for Intel 440BX/440LX and 82371AB/EB/MB.
Signed-off-by: Maciej Pijanka <maciej.pijanka@gmail.com> Acked-by: Uwe Hermann <uwe@hermann-uwe.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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Uwe Hermann
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2583dd2095
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90d17407d8
@@ -203,6 +203,50 @@ static const io_register_t ich0_pm_registers[] = {
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{ 0x7c, 4, "RESERVED" },
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};
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static const io_register_t i82371xx_pm_registers[] = {
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{ 0x00, 2, "PMSTS" },
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{ 0x02, 2, "PMEN" },
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{ 0x04, 2, "PMCNTRL" },
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{ 0x06, 2, "RESERVED" },
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{ 0x08, 1, "PMTMR" },
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{ 0x09, 1, "RESERVED" },
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{ 0x0A, 1, "RESERVED" },
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{ 0x0B, 1, "RESERVED" },
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{ 0x0C, 2, "GPSTS" },
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{ 0x0E, 2, "GPEN" },
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{ 0x10, 4, "PCNTRL" },
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#if DANGEROUS_REGISTERS
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/*
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* This register returns 0 on read, but reading it may cause
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* the system to enter C2 state, which might hang the system.
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*/
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{ 0x14, 1, "PLVL2" },
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{ 0x15, 1, "PLVL3" },
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{ 0x16, 2, "RESERVED" },
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#endif
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{ 0x18, 2, "GLBSTS" },
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{ 0x1A, 2, "RESERVED" },
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{ 0x1c, 4, "DEVSTS" },
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{ 0x20, 2, "GLBEN" },
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{ 0x22, 1, "RESERVED" },
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{ 0x23, 1, "RESERVED" },
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{ 0x24, 1, "RESERVED" },
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{ 0x25, 1, "RESERVED" },
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{ 0x26, 1, "RESERVED" },
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{ 0x27, 1, "RESERVED" },
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{ 0x28, 4, "GLBCTL" },
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{ 0x2C, 4, "DEVCTL" },
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/* The registers 0x30-0x33 and 0x34-0x37 allow byte-wise reads only. */
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{ 0x30, 1, "GPIREG 0" },
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{ 0x31, 1, "GPIREG 1" },
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{ 0x32, 1, "GPIREG 2" },
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{ 0x33, 1, "GPIREG 3" },
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{ 0x34, 1, "GPOREG 0" },
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{ 0x35, 1, "GPOREG 1" },
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{ 0x36, 1, "GPOREG 2" },
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{ 0x37, 1, "GPOREG 3" },
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};
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int print_pmbase(struct pci_dev *sb)
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{
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int i, size;
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@@ -230,6 +274,11 @@ int print_pmbase(struct pci_dev *sb)
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pm_registers = ich0_pm_registers;
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size = ARRAY_SIZE(ich0_pm_registers);
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break;
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case PCI_DEVICE_ID_INTEL_82371XX:
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pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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pm_registers = i82371xx_pm_registers;
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size = ARRAY_SIZE(i82371xx_pm_registers);
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break;
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case 0x1234: // Dummy for non-existent functionality
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printf("This southbridge does not have PMBASE.\n");
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return 1;
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