sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

AGESA f12 f15: Add OEM customisation

Browse Source 
Follow-up on commits a5d72a3 and 53052fe for f12 and f15.
OEM Hooks are not BiosCallOuts.

Change-Id: Iab22b0d73282a5a1a5d1344397b4430c0ebb81b5
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/14888
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Kyösti Mälkki
2016-05-16 07:50:58 +03:00
parent 5003632407
commit 90e63deeba
20 changed files with 287 additions and 535 deletions
Download Patch File Download Diff File Expand all files Collapse all files

120
src/mainboard/tyan/s8226/buildOpts.c
View File

@@ -18,7 +18,6 @@
#include "AGESA.h"
#include "CommonReturns.h"
#include "AdvancedApi.h"
#include <PlatformMemoryConfiguration.h>
#include "Filecode.h"
#define FILECODE PLATFORM_SPECIFIC_OPTIONS_FILECODE
@@ -449,122 +448,3 @@ CONST AP_MTRR_SETTINGS ROMDATA s8226_ap_mtrr_list[] =
#include "SanMarinoInstall.h"
/*----------------------------------------------------------------------------------------
* CUSTOMER OVERIDES MEMORY TABLE
*----------------------------------------------------------------------------------------
*/
//reference BKDG Table87: works
#define F15_WL_SEED 0x3B //family15 BKDG recommand 3B RDIMM, 1A UDIMM.
#define SEED_A 0x54
#define SEED_B 0x4D
#define SEED_C 0x45
#define SEED_D 0x40
#define F10_WL_SEED 0x3B //family10 BKDG recommand 3B RDIMM, 1A UDIMM.
//4B 41 51
/*
* Platform Specific Overriding Table allows IBV/OEM to pass in platform information to AGESA
* (e.g. MemClk routing, the number of DIMM slots per channel,...). If PlatformSpecificTable
* is populated, AGESA will base its settings on the data from the table. Otherwise, it will
* use its default conservative settings.
*/
CONST PSO_ENTRY ROMDATA DefaultPlatformMemoryConfiguration[] = {
//
// The following macros are supported (use comma to separate macros):
//
// MEMCLK_DIS_MAP(SocketID, ChannelID, MemClkDisBit0CSMap,..., MemClkDisBit7CSMap)
// The MemClk pins are identified based on BKDG definition of Fn2x88[MemClkDis] bitmap.
// AGESA will base on this value to disable unused MemClk to save power.
// Example:
// BKDG definition of Fn2x88[MemClkDis] bitmap for AM3 package is like below:
// Bit AM3/S1g3 pin name
// 0 M[B,A]_CLK_H/L[0]
// 1 M[B,A]_CLK_H/L[1]
// 2 M[B,A]_CLK_H/L[2]
// 3 M[B,A]_CLK_H/L[3]
// 4 M[B,A]_CLK_H/L[4]
// 5 M[B,A]_CLK_H/L[5]
// 6 M[B,A]_CLK_H/L[6]
// 7 M[B,A]_CLK_H/L[7]
// And platform has the following routing:
// CS0 M[B,A]_CLK_H/L[4]
// CS1 M[B,A]_CLK_H/L[2]
// CS2 M[B,A]_CLK_H/L[3]
// CS3 M[B,A]_CLK_H/L[5]
// Then platform can specify the following macro:
// MEMCLK_DIS_MAP(ANY_SOCKET, ANY_CHANNEL, 0x00, 0x00, 0x02, 0x04, 0x01, 0x08, 0x00, 0x00)
//
// CKE_TRI_MAP(SocketID, ChannelID, CKETriBit0CSMap, CKETriBit1CSMap)
// The CKE pins are identified based on BKDG definition of Fn2x9C_0C[CKETri] bitmap.
// AGESA will base on this value to tristate unused CKE to save power.
//
// ODT_TRI_MAP(SocketID, ChannelID, ODTTriBit0CSMap,..., ODTTriBit3CSMap)
// The ODT pins are identified based on BKDG definition of Fn2x9C_0C[ODTTri] bitmap.
// AGESA will base on this value to tristate unused ODT pins to save power.
//
// CS_TRI_MAP(SocketID, ChannelID, CSTriBit0CSMap,..., CSTriBit7CSMap)
// The Chip select pins are identified based on BKDG definition of Fn2x9C_0C[ChipSelTri] bitmap.
// AGESA will base on this value to tristate unused Chip select to save power.
//
// NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel)
// Specifies the number of DIMM slots per channel.
//
// NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel)
// Specifies the number of Chip selects per channel.
//
// NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket)
// Specifies the number of channels per socket.
//
// OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, USER_MEMORY_TIMING_MODE, MEMORY_BUS_SPEED)
// Specifies DDR bus speed of channel ChannelID on socket SocketID.
//
// DRAM_TECHNOLOGY(SocketID, TECHNOLOGY_TYPE)
// Specifies the DRAM technology type of socket SocketID (DDR2, DDR3,...)
//
// WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed,
// Byte6Seed, Byte7Seed, ByteEccSeed)
// Specifies the write leveling seed for a channel of a socket.
//
/* Specifies the write leveling seed for a channel of a socket.
* WRITE_LEVELING_SEED(SocketID, ChannelID, DimmID,
* Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
* Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed,
* ByteEccSeed)
*/
WRITE_LEVELING_SEED(
ANY_SOCKET, ANY_CHANNEL, ALL_DIMMS,
F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
F15_WL_SEED, F15_WL_SEED, F15_WL_SEED, F15_WL_SEED,
F15_WL_SEED),
/* HW_RXEN_SEED(SocketID, ChannelID, DimmID,
* Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed,
* Byte4Seed, Byte5Seed, Byte6Seed, Byte7Seed, ByteEccSeed)
*/
HW_RXEN_SEED(
ANY_SOCKET, CHANNEL_A, ALL_DIMMS,
SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A, SEED_A,
SEED_A),
HW_RXEN_SEED(
ANY_SOCKET, CHANNEL_B, ALL_DIMMS,
SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B, SEED_B,
SEED_B),
HW_RXEN_SEED(
ANY_SOCKET, CHANNEL_C, ALL_DIMMS,
SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C, SEED_C,
SEED_C),
HW_RXEN_SEED(
ANY_SOCKET, CHANNEL_D, ALL_DIMMS,
SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D, SEED_D,
SEED_D),
NUMBER_OF_DIMMS_SUPPORTED (ANY_SOCKET, ANY_CHANNEL, 3), //max 3
PSO_END
};
/*
* These tables are optional and may be used to adjust memory timing settings
*/