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AMD Kabini: Modify Hudson southbridge to support new AMD processor

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Yangtze uses Hudson AGESA wrapper code but has some changes.
The changes are necessary and have no effects on Hudson.

Change-Id: Iada90d34fdc2025bd14f566488ee12810a28ac0d
Signed-off-by: Siyuan Wang <SiYuan.Wang@amd.com>
Signed-off-by: Siyuan Wang <wangsiyuanbuaa@gmail.com>
Signed-off-by: Bruce Griffith <Bruce.Griffith@se-eng.com>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
Tested-by: Bruce Griffith <bruce.griffith@se-eng.com>
Reviewed-on: http://review.coreboot.org/3783
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martin.roth@se-eng.com>
This commit is contained in:
Siyuan Wang
2013-07-09 17:32:42 +08:00
committed by Bruce Griffith
parent 3e32cc00d1
commit 915714501b
6 changed files with 38 additions and 5 deletions
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9
src/southbridge/amd/agesa/hudson/spi.c
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@@ -61,7 +61,9 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
/* First byte is cmd which can not being sent through FIFO. */
u8 cmd = *(u8 *)dout++;
u8 readoffby1;
#if !CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
u8 readwrite;
#endif
u8 bytesout, bytesin;
u8 count;
@@ -71,8 +73,15 @@ int spi_xfer(struct spi_slave *slave, const void *dout,
readoffby1 = bytesout ? 0 : 1;
#if CONFIG_SOUTHBRIDGE_AMD_AGESA_YANGTZE
write8(spibar + 0x1E, 5);
write8(spibar + 0x1F, bytesout); /* SpiExtRegIndx [5] - TxByteCount */
write8(spibar + 0x1E, 6);
write8(spibar + 0x1F, bytesin); /* SpiExtRegIndx [6] - RxByteCount */
#else
readwrite = (bytesin + readoffby1) << 4 | bytesout;
write8(spibar + 1, readwrite);
#endif
write8(spibar + 0, cmd);
reset_internal_fifo_pointer();