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soc/amd/common: Allow AGESA file split for pre- and post-memory

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By splitting the binary files for platform initialization, the
post-memory code can be modified to stop executing in place (--xip).

This change creates two separate sections in CBFS for AGESA and loads
the appropriate file at the correct stage.

BUG=b:68141063
TEST=Booted kahlee with split agesa enabled.

Change-Id: I2fa423df164037bc3738476fd2a34522df279e34
Signed-off-by: Justin TerAvest <teravest@chromium.org>
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/22974
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Justin TerAvest
2017-12-22 15:15:02 -07:00
committed by Martin Roth
parent a71c66a52e
commit 922619512d
3 changed files with 67 additions and 2 deletions
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23
src/vendorcode/amd/pi/00670F00/Makefile.inc
View File

@ -123,8 +123,27 @@ ramstage-libs += $(agesa_output_path)/libagesa.a
#######################################################################
ifeq ($(CONFIG_AGESA_SPLIT_MEMORY_FILES), y)
cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)
$(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-file := $(CONFIG_AGESA_PRE_MEMORY_BINARY_PI_FILE)
$(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-type := stage
$(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-options := --xip
# 4KiB alignment to handle any interior alignment. Current AGESA only has
# 64 byte alignment.
$(CONFIG_AGESA_PRE_MEMORY_CBFS_NAME)-align := 4096
cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)
$(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-file := $(CONFIG_AGESA_POST_MEMORY_BINARY_PI_FILE)
$(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-type := stage
$(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-options := --xip
# 4KiB alignment to handle any interior alignment. Current AGESA only has
# 64 byte alignment.
$(CONFIG_AGESA_POST_MEMORY_CBFS_NAME)-align := 4096
else
cbfs-files-$(CONFIG_CPU_AMD_AGESA_BINARY_PI) += $(CONFIG_AGESA_CBFS_NAME)
$(CONFIG_AGESA_CBFS_NAME)-file := $(CONFIG_AGESA_BINARY_PI_FILE)
ifeq ($(CONFIG_AGESA_BINARY_PI_AS_STAGE),y)
$(CONFIG_AGESA_CBFS_NAME)-type := stage
$(CONFIG_AGESA_CBFS_NAME)-options := --xip
@ -134,6 +153,8 @@ $(CONFIG_AGESA_CBFS_NAME)-align := 4096
else
$(CONFIG_AGESA_CBFS_NAME)-type := raw
$(CONFIG_AGESA_CBFS_NAME)-position := $(CONFIG_AGESA_BINARY_PI_LOCATION)
endif
endif # CONFIG_AGESA_BINARY_PI_AS_STAGE
endif # CONFIG_AGESA_SPLIT_MEMORY_FILES
endif

32
src/vendorcode/amd/pi/Kconfig
View File

@ -58,10 +58,42 @@ config AGESA_BINARY_PI_AS_STAGE
cpu address space. It's required that the file be in ELF format
containing the relocations necessary for relocating at runtime.
config AGESA_SPLIT_MEMORY_FILES
bool "Split AGESA Binary PI into pre- and post-memory files."
depends on AGESA_BINARY_PI_AS_STAGE
default n
help
Specifies that AGESA is split into two binaries for pre- and
post-memory.
config AGESA_PRE_MEMORY_BINARY_PI_FILE
string
depends on AGESA_SPLIT_MEMORY_FILES
default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_premem.elf" if SOC_AMD_STONEYRIDGE_FT4
help
Specify the binary file to use for pre-memory AMD platform
initialization.
config AGESA_POST_MEMORY_BINARY_PI_FILE
string
depends on AGESA_SPLIT_MEMORY_FILES
default "3rdparty/blobs/pi/amd/00670F00/FT4/AGESA_postmem.elf" if SOC_AMD_STONEYRIDGE_FT4
help
Specify the binary file to use for post-memory AMD platform
initialization.
config AGESA_CBFS_NAME
string
default "AGESA"
config AGESA_PRE_MEMORY_CBFS_NAME
string
default "AGESA_PRE_MEM"
config AGESA_POST_MEMORY_CBFS_NAME
string
default "AGESA_POST_MEM"
config AGESA_BINARY_PI_LOCATION
hex "AGESA PI binary address in ROM"
default 0xFFE00000