google/clapper: fix up devicetree

When clapper was upstreamed, the devicetree was pulled from
the wrong firmware branch, leading to some incorrect settings
and touchpad, touchscreen, and audio not working.

Correct devicetree settings using Chromium branch firmware-clapper-5216.199.B

Test: build/boot google/clapper, verify touchpad/touchscreen/audio
functional under Linux (GalliumOS 3.0/kernel 4.16.18).

Change-Id: Iacfce575a054b1f484149f36d0aa83d20d034d8a
Signed-off-by: Matt DeVillier <matt.devillier@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Matt DeVillier
2019-05-26 16:25:24 -05:00
committed by Patrick Georgi
parent 348a44ecae
commit 924463d1a5

View File

@ -32,16 +32,25 @@ chip soc/intel/baytrail
register "sdcard_cap_high" = "0x0" register "sdcard_cap_high" = "0x0"
# Enable devices in ACPI mode # Enable devices in ACPI mode
register "lpe_acpi_mode" = "1"
register "lpss_acpi_mode" = "1"
register "scc_acpi_mode" = "1" register "scc_acpi_mode" = "1"
# Enable PIPEA as DP_C # Enable PIPEA as DP_C
register "gpu_pipea_port_select" = "2" # DP_C register "gpu_pipea_port_select" = "2" # DP_C
register "gpu_pipea_power_cycle_delay" = "5" # 400ms register "gpu_pipea_power_cycle_delay" = "6" # 600ms
register "gpu_pipea_power_on_delay" = "2000" # 200ms register "gpu_pipea_power_on_delay" = "5000" # 500ms
register "gpu_pipea_light_on_delay" = "10" # 1ms register "gpu_pipea_light_on_delay" = "70" # 7ms
register "gpu_pipea_power_off_delay" = "500" # 50ms register "gpu_pipea_power_off_delay" = "500" # 50ms
register "gpu_pipea_light_off_delay" = "2000" # 200ms register "gpu_pipea_light_off_delay" = "2000" # 200ms
# VR PS2 control
register "vnn_ps2_enable" = "1"
register "vcc_ps2_enable" = "1"
# Disable SLP_X stretching after SUS power well fail.
register "disable_slp_x_stretch_sus_fail" = "1"
device cpu_cluster 0 on device cpu_cluster 0 on
device lapic 0 on end device lapic 0 on end
end end
@ -59,11 +68,11 @@ chip soc/intel/baytrail
device pci 18.2 on end # I2C2 device pci 18.2 on end # I2C2
device pci 18.3 off end # I2C3 device pci 18.3 off end # I2C3
device pci 18.4 off end # I2C4 device pci 18.4 off end # I2C4
device pci 18.5 off end # I2C5 device pci 18.5 on end # I2C5
device pci 18.6 on end # I2C6 device pci 18.6 on end # I2C6
device pci 18.7 off end # I2C7 device pci 18.7 off end # I2C7
device pci 1a.0 off end # TXE device pci 1a.0 off end # TXE
device pci 1b.0 off end # HDA device pci 1b.0 on end # HDA
device pci 1c.0 on end # PCIE_PORT1 device pci 1c.0 on end # PCIE_PORT1
device pci 1c.1 on end # PCIE_PORT2 device pci 1c.1 on end # PCIE_PORT2
device pci 1c.2 off end # PCIE_PORT3 device pci 1c.2 off end # PCIE_PORT3