soc/amd/stoneyridge: Change code to accommodate Merlin Falcon SOC

Stoney Ridge is family 15h models 70h-7Fh, Merlin Falcon is family 15h models
60h-6Fh. Add changes based on config parameter SOC_AMD_MERLINFALCON to make
the code  backward compatible with Merlin Falcon.

BUG=none.
TEST=Tested later with padmelon board.

Change-Id: I00fe832324500bcb07fca292a0a55f7258a2d82f
Signed-off-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33624
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/amd/stoneyridge/acpi/cpu.asl

@@ -34,7 +34,15 @@ External (\_PR.P007, DeviceObj)
 /* Return a package containing enabled processor entries */
 Method (PPKG)
 {
-	If (LGreaterEqual (\PCNT, 2)) {
+	If (LGreaterEqual (\PCNT, 4)) {
+		Return (Package ()
+		{
+			\_PR.P000,
+			\_PR.P001,
+			\_PR.P002,
+			\_PR.P003
+		})
+	} ElseIf (LGreaterEqual (\PCNT, 2)) {
 		Return (Package ()
 		{
 			\_PR.P000,

src/soc/amd/stoneyridge/chip.h

@@ -23,9 +23,15 @@
 #include <soc/i2c.h>
 #include <arch/acpi_device.h>
 
+/* Merlin Falcon supports 2 channels, Prairie Falcon only 1 (channel B) */
 #define MAX_NODES 1
+#if CONFIG(SOC_AMD_MERLINFALCON) &&  CONFIG(HAVE_MERLINFALCON_BINARIES)
+#define MAX_DRAM_CH 2
+#define MAX_DIMMS_PER_CH 2
+#else
 #define MAX_DRAM_CH 1
 #define MAX_DIMMS_PER_CH 2
+#endif
 
 #define STONEY_I2C_DEV_MAX 4
 

src/soc/amd/stoneyridge/cpu.c

@@ -145,6 +145,7 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_AMD, 0x660f01 },
 	{ X86_VENDOR_AMD, 0x670f00 },
 	{ 0, 0 },
 };

src/soc/amd/stoneyridge/include/soc/pci_devs.h

@@ -39,17 +39,24 @@
 #define IOMMU_DEVFN		PCI_DEVFN(IOMMU_DEV, IOMMU_FUNC)
 #define SOC_IOMMU_DEV		_SOC_DEV(IOMMU_DEV, IOMMU_FUNC)
 
-/* Internal Graphics */
+/*
+ * Internal Graphics
+ * Device IDs subject to SKU/OPN variation
+ * GFX_DEVID for merlinfalcon		PCI_DEVICE_ID_AMD_15H_MODEL_606F_GFX
+ * GFX_DEVID for stoneyridge		PCI_DEVICE_ID_AMD_15H_MODEL_707F_GFX
+ */
 #define GFX_DEV			0x1
 #define GFX_FUNC		0
-#define GFX_DEVID		0x98e4 /* subject to SKU/OPN variation */
 #define GFX_DEVFN		PCI_DEVFN(GFX_DEV, GFX_FUNC)
 #define SOC_GFX_DEV		_SOC_DEV(GFX_DEV, GFX_FUNC)
 
-/* HD Audio 0 */
+/* HD Audio 0
+ * Device IDs
+ * HDA0_DEVID			PCI_DEVICE_ID_AMD_15H_MODEL_606F_HDA
+ * HDA0_DEVID			PCI_DEVICE_ID_AMD_15H_MODEL_707F_HDA
+ */
 #define HDA0_DEV		0x1
 #define HDA0_FUNC		1
-#define HDA0_DEVID		0x15b3
 #define HDA0_DEVFN		PCI_DEVFN(HDA0_DEV, HDA0_FUNC)
 #define SOC_HDA0_DEV		_SOC_DEV(HDA0_DEV, HDA0_FUNC)
 
@@ -109,45 +116,63 @@
 #define HDA1_DEVFN		PCI_DEVFN(HDA1_DEV, HDA1_FUNC)
 #define SOC_HDA1_DEV		_SOC_DEV(HDA1_DEV, HDA1_FUNC)
 
-/* HT Configuration */
+/* HT Configuration
+ * Device IDs
+ * HT_DEVID for merlinfalcon	PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT
+ * HT_DEVID for stoneyridge	PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT
+ */
 #define HT_DEV			0x18
 #define HT_FUNC			0
-#define HT_DEVID		0x15b0
 #define HT_DEVFN		PCI_DEVFN(HT_DEV, HT_FUNC)
 #define SOC_HT_DEV		_SOC_DEV(HT_DEV, HT_FUNC)
 
-/* Address Maps */
+/* Address Maps
+ * Device IDs
+ * ADDR_DEVID for merlinfalcon	0x1571
+ * ADDR_DEVID for stoneyridge	0x15b1
+ */
 #define ADDR_DEV		0x18
 #define ADDR_FUNC		1
-#define ADDR_DEVID		0x15b1
 #define ADDR_DEVFN		PCI_DEVFN(ADDR_DEV, ADDR_FUNC)
 #define SOC_ADDR_DEV		_SOC_DEV(ADDR_DEV, ADDR_FUNC)
 
-/* DRAM Configuration */
+/* DRAM Configuration
+ * Device IDs
+ * DCT_DEVID for merlinfalcon	0x1572
+ * DCT_DEVID for stoneyridge	0x15b2
+ */
 #define DCT_DEV			0x18
 #define DCT_FUNC		2
-#define DCT_DEVID		0x15b2
 #define DCT_DEVFN		PCI_DEVFN(DCT_DEV, DCT_FUNC)
 #define SOC_DCT_DEV		_SOC_DEV(DCT_DEV, DCT_FUNC)
 
-/* Misc. Configuration */
+/* Misc. Configuration
+ * Device IDs
+ * MISC_DEVID for merlinfalcon	0x1573
+ * MISC_DEVID for stoneyridge	0x15b3
+ */
 #define MISC_DEV		0x18
 #define MISC_FUNC		3
-#define MISC_DEVID		0x15b3
 #define MISC_DEVFN		PCI_DEVFN(MISC_DEV, MISC_FUNC)
 #define SOC_MISC_DEV		_SOC_DEV(MISC_DEV, MISC_FUNC)
 
-/* PM Configuration */
+/* PM Configuration
+ * Device IDs
+ * PM_DEVID for merlinfalcon	0x1574
+ * PM_DEVID for stoneyridge	0x15b4
+ */
 #define PM_DEV			0x18
 #define PM_FUNC			4
-#define PM_DEVID		0x15b4
 #define PM_DEVFN		PCI_DEVFN(PM_DEV, PM_FUNC)
 #define SOC_PM_DEV		_SOC_DEV(PM_DEV, PM_FUNC)
 
-/* Northbridge Configuration */
+/* Northbridge Configuration
+ * Device IDs
+ * NB_DEVID for merlinfalcon	0x1575
+ * NB_DEVID for stoneyridge	0x15b5
+ */
 #define NB_DEV			0x18
 #define NB_FUNC			5
-#define NB_DEVID		0x15b5
 #define NB_DEVFN		PCI_DEVFN(NB_DEV, NB_FUNC)
 #define SOC_NB_DEV		_SOC_DEV(NB_DEV, NB_FUNC)
 

src/soc/amd/stoneyridge/northbridge.c

@@ -347,10 +347,15 @@ static struct device_operations northbridge_operations = {
 	.ops_pci	  = 0,
 };
 
+static const unsigned short pci_device_ids[] = {
+	PCI_DEVICE_ID_AMD_15H_MODEL_606F_NB_HT,
+	PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT,
+	0 };
+
 static const struct pci_driver family15_northbridge __pci_driver = {
 	.ops	= &northbridge_operations,
 	.vendor = PCI_VENDOR_ID_AMD,
-	.device = PCI_DEVICE_ID_AMD_15H_MODEL_707F_NB_HT,
+	.devices = pci_device_ids,
 };
 
 /*
@@ -464,9 +469,13 @@ void domain_set_resources(struct device *dev)
 u32 map_oprom_vendev(u32 vendev)
 {
 	u32 new_vendev;
-	new_vendev =
+
-		((vendev >= 0x100298e0) && (vendev <= 0x100298ef)) ?
+	if ((vendev >= 0x100298e0) && (vendev <= 0x100298ef))
-				0x100298e0 : vendev;
+		new_vendev = 0x100298e0;
+	else if ((vendev >= 0x10029870) && (vendev <= 0x1002987f))
+		new_vendev = 0x10029870;
+	else
+		new_vendev = vendev;
 
 	if (vendev != new_vendev)
 		printk(BIOS_NOTICE, "Mapping PCI device %8x to %8x\n",