soc/intel/cannonlake: Add option to skip coreboot MP init

This patch provides option for mainboard to skip coreboot MP
initialization if required based on use_fsp_mp_init.

Option for mainboard to skip coreboot MP initialization
* 0 = Make use of coreboot MP Init
* 1 = Make use of FSP MP Init

Default coreboot does MP initialization for CNL.

Change-Id: Ia7da0842996a9db09e6e2b7b201b3a883c3887a2
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/26819
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/mainboard/google/zoombini/variants/baseboard/devicetree.cb

@@ -20,7 +20,6 @@ chip soc/intel/cannonlake
 
 	# FSP configuration
 	register "SaGv" = "3"
-	register "FspSkipMpInit" = "1"
 	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"

src/mainboard/google/zoombini/variants/meowth/devicetree.cb

@@ -29,7 +29,6 @@ chip soc/intel/cannonlake
 
 	# FSP configuration
 	register "SaGv" = "SaGv_Enabled"
-	register "FspSkipMpInit" = "1"
 	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"

src/mainboard/intel/cannonlake_rvp/variants/cnl_u/devicetree.cb

@@ -6,7 +6,6 @@ chip soc/intel/cannonlake
 
 	# FSP configuration
 	register "SaGv" = "3"
-	register "FspSkipMpInit" = "1"
 	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"

src/mainboard/intel/cannonlake_rvp/variants/cnl_y/devicetree.cb

@@ -6,7 +6,6 @@ chip soc/intel/cannonlake
 
 	# FSP configuration
 	register "SaGv" = "3"
-	register "FspSkipMpInit" = "1"
 	register "SmbusEnable" = "1"
 	register "ScsEmmcEnabled" = "1"
 	register "ScsEmmcHs400Enabled" = "1"

src/soc/intel/cannonlake/chip.c

@@ -295,7 +295,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 	params->Heci3Enabled = config->Heci3Enabled;
 	params->Device4Enable = config->Device4Enable;
-	params->SkipMpInit = config->FspSkipMpInit;
+	params->SkipMpInit = !config->use_fsp_mp_init;
 
 	/* VrConfig Settings for 5 domains
 	 * 0 = System Agent, 1 = IA Core, 2 = Ring,

src/soc/intel/cannonlake/chip.h

@@ -206,7 +206,12 @@ struct soc_intel_cannonlake_config {
 		CHIPSET_LOCKDOWN_COREBOOT, /* coreboot handles locking */
 	} chipset_lockdown;
 
-	uint8_t FspSkipMpInit;
+	/*
+	 * Option for mainboard to skip coreboot MP initialization
+	 * 0 = Make use of coreboot MP Init
+	 * 1 = Make use of FSP MP Init
+	 */
+	uint8_t use_fsp_mp_init;
 	/* VrConfig Settings for 5 domains
 	 * 0 = System Agent, 1 = IA Core, 2 = Ring,
 	 * 3 = GT unsliced,  4 = GT sliced */