soc/intel/cannonlake/bootblock: Clear the GPI IS & IE registers

Clear the GPI Interrupt Status & Enable registers to prevent any
interrupt storms due to GPI.

BUG=b:138282962
TEST=Ensure that the Interrupt status & enable registers are reset
during the boot-up when the system is brought out of G3, S5 & S3. Ensure
that the system boots fine to ChromeOS.

Change-Id: I2185355d0095601e0778b6bf47ae137cc53e4051
Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/34624
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org>

src/soc/intel/cannonlake/bootblock/bootblock.c

@@ -59,6 +59,11 @@ void bootblock_soc_early_init(void)
 
 void bootblock_soc_init(void)
 {
+	/*
+	 * Clear the GPI interrupt status and enable registers. These
+	 * registers do not get reset to default state when booting from S5.
+	 */
+	gpi_clear_int_cfg();
 	report_platform_info();
 	pch_early_init();
 }