drivers/intel/fsp1_1: align on using ACPI_Sx definitions
The SLEEP_STATE_x definitions in the chipsets utilizing FSP 1.1. driver have the exact same values as the ACPI_Sx definitions. The chipsets will be moved over subsequently, but updating this first allows the per-chipset patches to be isolated. BUG=chrome-os-partner:54977 Change-Id: I383a9a732ef68bf2276f6149ffa5360bcdfb70b3 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: https://review.coreboot.org/15665 Tested-by: build bot (Jenkins) Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-by: Furquan Shaikh <furquan@google.com> Reviewed-by: Lee Leahy <leroy.p.leahy@intel.com>
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@ -13,6 +13,7 @@
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* GNU General Public License for more details.
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*/
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#include <arch/acpi.h>
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#include <cbmem.h>
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#include <console/console.h>
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#include <fsp/memmap.h>
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@ -80,7 +81,7 @@ void raminit(struct romstage_params *params)
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/* Zero fill RT Buffer data and start populating fields. */
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memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer));
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pei_ptr = params->pei_data;
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if (pei_ptr->boot_mode == SLEEP_STATE_S3) {
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if (pei_ptr->boot_mode == ACPI_S3) {
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fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME;
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} else if (pei_ptr->saved_data != NULL) {
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fsp_rt_common_buffer.BootMode =
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@ -156,7 +157,7 @@ void raminit(struct romstage_params *params)
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/* Migrate CAR data */
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printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
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if (pei_ptr->boot_mode != SLEEP_STATE_S3) {
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if (pei_ptr->boot_mode != ACPI_S3) {
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cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
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fsp_reserved_bytes);
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} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
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