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soc/amd/stoneyridge: Add IO access functions for PMx

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Replace locations in the source that explicitely use the CD6/CD7
index/data pair with utility function calls.

Change-Id: I6e7ba472ef2551e363987d18a79408fcd2074de4
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32648
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Marshall Dawson
2019-05-05 15:39:40 -06:00
committed by Martin Roth
parent f36fcdf2ab
commit 939bfccb3d
4 changed files with 48 additions and 12 deletions
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12
src/soc/amd/stoneyridge/southbridge.c
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@@ -329,11 +329,9 @@ void sb_lpc_port80(void)
u8 byte;
/* Enable LPC controller */
outb(PM_LPC_GATING, PM_INDEX);
byte = inb(PM_DATA);
byte = pm_io_read8(PM_LPC_GATING);
byte |= PM_LPC_ENABLE;
outb(PM_LPC_GATING, PM_INDEX);
outb(byte, PM_DATA);
pm_io_write8(PM_LPC_GATING, byte);
/* Enable port 80 LPC decode in pci function 3 configuration space. */
byte = pci_read_config8(SOC_LPC_DEV, LPC_IO_OR_MEM_DEC_EN_HIGH);
@@ -367,11 +365,9 @@ void sb_acpi_mmio_decode(void)
uint8_t byte;
/* Enable ACPI MMIO range 0xfed80000 - 0xfed81fff */
outb(PM_ISA_CONTROL, PM_INDEX);
byte = inb(PM_DATA);
byte = pm_io_read8(PM_ISA_CONTROL);
byte |= MMIO_EN;
outb(PM_ISA_CONTROL, PM_INDEX);
outb(byte, PM_DATA);
pm_io_write8(PM_ISA_CONTROL, byte);
}
static void sb_enable_cf9_io(void)