nb/intel/ironlake: Add definition for QPI Link PCI device

On multi-socket platforms, there can be two QPI buses, each with its own
PCI device. We only have one QPI link on Arrandale, though. In case
support for multi-socket processors ever gets added, name it Link 0.

Tested with BUILD_TIMELESS=1, Packard Bell MS2290 does not change.

Change-Id: I6481154a2d1cc1c84c1f167a374a62af3b2cf3d8
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43735
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>

src/northbridge/intel/ironlake/ironlake.h

@@ -60,6 +60,11 @@
 #define SAD_DRAM_RULE(x)	(0x80 + 4 * (x)) /* 0-7 */
 #define SAD_INTERLEAVE_LIST(x)	(0xc0 + 4 * (x)) /* 0-7 */
 
+/*
+ * QPI Link 0
+ */
+#define QPI_LINK_0		PCI_DEV(QUICKPATH_BUS, 2, 0)
+
 
 /* Device 0:2.0 PCI configuration space (Graphics Device) */