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soc/intel/skylake: Fix PMC address range setup for PCH-H

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The PMC of PCH-H requires a different destination id.

TEST=Run on kontron/bsl6 and observed that PM registers are correctly
     dumped at start of romstage.

Change-Id: I862e4df986f1cdea34f8fa45d016fb6b51f29122
Signed-off-by: Nico Huber <nico.huber@secunet.com>
Reviewed-on: https://review.coreboot.org/20479
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
This commit is contained in:
Nico Huber
2017-07-06 15:06:37 +02:00
committed by Nico Huber
parent c587b971dd
commit 9413cb5f95
1 changed files with 8 additions and 2 deletions
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10
src/soc/intel/skylake/bootblock/pch.c
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@@ -141,7 +141,10 @@ static void soc_config_acpibase(void)
*/ */
reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1); reg32 = ((0x3f << 18) | ACPI_BASE_ADDRESS | 1);
pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32);
pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23A0); if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))
pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8);
else
pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a0);
} }
static void soc_config_pwrmbase(void) static void soc_config_pwrmbase(void)
@@ -172,7 +175,10 @@ static void soc_config_pwrmbase(void)
pcr_write32(PID_DMI, PCR_DMI_PMBASEA, pcr_write32(PID_DMI, PCR_DMI_PMBASEA,
((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) | ((PCH_PWRM_BASE_ADDRESS & 0xFFFF0000) |
(PCH_PWRM_BASE_ADDRESS >> 16))); (PCH_PWRM_BASE_ADDRESS >> 16)));
pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023A0); if (IS_ENABLED(CONFIG_SKYLAKE_SOC_PCH_H))
pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a8);
else
pcr_write32(PID_DMI, PCR_DMI_PMBASEC, 0x800023a0);
} }
static void soc_config_tco(void) static void soc_config_tco(void)