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arm(64): Manually clean up the mess left by write32() transition

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This patch is a manual cleanup of all the rubble left by coccinelle
waltzing through our code base. It's generally not very good with line
breaks and sometimes even eats comments, so this patch is my best
attempt at putting it all back together.

Also finally remove those hated writel()-style macros from the headers.

BRANCH=none
BUG=chromium:444723
TEST=None (depends on next patch)

Change-Id: Id572f69c420c35577701feb154faa5aaf79cd13e
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: 817402a80ab77083728b55aed74b3b4202ba7f1d
Original-Change-Id: I3b0dcd6fe09fc4e3b83ee491625d6dced98e3047
Original-Signed-off-by: Julius Werner <jwerner@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/254865
Reviewed-on: http://review.coreboot.org/9837
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
Julius Werner
2015-02-19 20:19:23 -08:00
committed by Patrick Georgi
parent 2f37bd6551
commit 9418476524
26 changed files with 397 additions and 155 deletions
Download Patch File Download Diff File Expand all files Collapse all files

31
src/soc/rockchip/rk3288/sdram.c
View File

@@ -609,12 +609,15 @@ static void pctl_cfg(u32 channel,
sdram_params->pctl_timing.tcl - 1);
write32(&ddr_pctl_regs->dfitphywrlat,
sdram_params->pctl_timing.tcwl);
write32(&ddr_pctl_regs->mcfg,
LPDDR2_S4 | MDDR_LPDDR2_CLK_STOP_IDLE(0) | LPDDR2_EN | BURSTLENGTH_CFG(burstlen) | TFAW_CFG(6) | PD_EXIT_FAST | PD_TYPE(1) | PD_IDLE(0));
write32(&ddr_pctl_regs->mcfg, LPDDR2_S4 |
MDDR_LPDDR2_CLK_STOP_IDLE(0) | LPDDR2_EN |
BURSTLENGTH_CFG(burstlen) | TFAW_CFG(6) |
PD_EXIT_FAST | PD_TYPE(1) | PD_IDLE(0));
write32(&rk3288_grf->soc_con0, MSCH_MAINDDR3(channel, 0));
write32(&rk3288_grf->soc_con2,
PUBL_LPDDR3_EN(channel, 1) | PCTL_BST_DISABLE(channel, 1) | PCTL_LPDDR3_ODT_EN(channel, sdram_params->odt));
write32(&rk3288_grf->soc_con2, PUBL_LPDDR3_EN(channel, 1) |
PCTL_BST_DISABLE(channel, 1) |
PCTL_LPDDR3_ODT_EN(channel, sdram_params->odt));
break;
case DDR3:
@@ -627,11 +630,14 @@ static void pctl_cfg(u32 channel,
write32(&ddr_pctl_regs->dfitphywrlat,
sdram_params->pctl_timing.tcwl - 1);
write32(&ddr_pctl_regs->mcfg,
MDDR_LPDDR2_CLK_STOP_IDLE(0) | DDR3_EN | DDR2_DDR3_BL_8 | TFAW_CFG(6) | PD_EXIT_SLOW | PD_TYPE(1) | PD_IDLE(0));
MDDR_LPDDR2_CLK_STOP_IDLE(0) | DDR3_EN |
DDR2_DDR3_BL_8 | TFAW_CFG(6) |
PD_EXIT_SLOW | PD_TYPE(1) | PD_IDLE(0));
write32(&rk3288_grf->soc_con0, MSCH_MAINDDR3(channel, 1));
write32(&rk3288_grf->soc_con2,
PUBL_LPDDR3_EN(channel, 0) | PCTL_BST_DISABLE(channel, 0) | PCTL_LPDDR3_ODT_EN(channel, 0));
write32(&rk3288_grf->soc_con2, PUBL_LPDDR3_EN(channel, 0) |
PCTL_BST_DISABLE(channel, 0) |
PCTL_LPDDR3_ODT_EN(channel, 0));
break;
}
@@ -656,11 +662,14 @@ static void phy_cfg(u32 channel, const struct rk3288_sdram_params *sdram_params)
write32(&msch_regs->devtodev,
BUSWRTORD(2) | BUSRDTOWR(2) | BUSRDTORD(1));
write32(&ddr_publ_regs->ptr[0],
PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / MHz * 5120, 1000)) | PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / MHz * 50, 1000)) | PRT_ITMSRST(8));
PRT_DLLLOCK(div_round_up(sdram_params->ddr_freq / MHz * 5120, 1000))
| PRT_DLLSRST(div_round_up(sdram_params->ddr_freq / MHz * 50, 1000))
| PRT_ITMSRST(8));
write32(&ddr_publ_regs->ptr[1],
PRT_DINIT0(div_round_up(sdram_params->ddr_freq / MHz * 500000, 1000)) | PRT_DINIT1(div_round_up(sdram_params->ddr_freq / MHz * 400, 1000)));
write32(&ddr_publ_regs->ptr[2],
PRT_DINIT2(MIN(dinit2, 0x1ffff)) | PRT_DINIT3(div_round_up(sdram_params->ddr_freq / MHz * 1000, 1000)));
PRT_DINIT0(div_round_up(sdram_params->ddr_freq / MHz * 500000, 1000))
| PRT_DINIT1(div_round_up(sdram_params->ddr_freq / MHz * 400, 1000)));
write32(&ddr_publ_regs->ptr[2], PRT_DINIT2(MIN(dinit2, 0x1ffff))
| PRT_DINIT3(div_round_up(sdram_params->ddr_freq / MHz * 1000, 1000)));
switch (sdram_params->dramtype) {
case LPDDR3: