From 87e36c442e33388493f259bfa14db460a4f02753 Mon Sep 17 00:00:00 2001 From: Sridhar Siricilla Date: Sun, 3 May 2020 19:08:18 +0530 Subject: [PATCH 0001/1155] soc/intel/common: Trigger recovery mode for CSE Lite SKU run time errors Implement triggering recovery mode for CSE Lite SKU runtime errors. Also, define recovery subcodes for various possible Lite SKU runtime errors. BUG=b:153520354 TEST=Verified on hatch Signed-off-by: Sridhar Siricilla Change-Id: Ib7744fc4fd0e41804d9b45079bf706b300220c62 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40563 Tested-by: build bot (Jenkins) Reviewed-by: V Sowmya Reviewed-by: Rizwan Qureshi Reviewed-by: Furquan Shaikh --- src/soc/intel/common/block/cse/cse_lite.c | 49 +++++++++++++++++++---- 1 file changed, 42 insertions(+), 7 deletions(-) diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index b985a94628..1f9e2ce225 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -4,6 +4,8 @@ #include #include #include +#include +#include /* Converts bp index to boot partition string */ #define GET_BP_STR(bp_index) (bp_index ? "RW" : "RO") @@ -27,6 +29,30 @@ enum boot_partition_id { RW = 1 }; +/* CSE recovery sub-error codes */ +enum csme_failure_reason { + /* Unspecified error */ + CSE_LITE_SKU_UNSPECIFIED = 1, + + /* CSE fails to boot from RW */ + CSE_LITE_SKU_RW_JUMP_ERROR = 2, + + /* CSE RW boot partition access error */ + CSE_LITE_SKU_RW_ACCESS_ERROR = 3, + + /* Fails to set next boot partition as RW */ + CSE_LITE_SKU_RW_SWITCH_ERROR = 4, + + /* CSE firmware update failure */ + CSE_LITE_SKU_FW_UPDATE_ERROR = 5, + + /* Fails to communicate with CSE */ + CSE_LITE_SKU_COMMUNICATION_ERROR = 6, + + /* Fails to wipe CSE runtime data */ + CSE_LITE_SKU_DATA_WIPE_ERROR = 7 +}; + /* * Boot partition status. * The status is returned in response to MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO cmd. @@ -112,6 +138,19 @@ struct get_bp_info_rsp { struct cse_bp_info bp_info; } __packed; +static void cse_trigger_recovery(uint8_t rec_sub_code) +{ + if (CONFIG(VBOOT)) { + struct vb2_context *ctx; + ctx = vboot_get_context(); + vb2api_fail(ctx, VB2_RECOVERY_INTEL_CSE_LITE_SKU, rec_sub_code); + vboot_save_data(ctx); + vboot_reboot(); + } + + die("cse_lite: Failed to trigger recovery mode(recovery subcode:%d)\n", rec_sub_code); +} + static uint8_t cse_get_current_bp(const struct cse_bp_info *cse_bp_info) { return cse_bp_info->current_bp; @@ -306,22 +345,18 @@ void cse_fw_sync(void *unused) if (!cse_get_bp_info(&cse_bp_info)) { printk(BIOS_ERR, "cse_bp: Failed to get CSE boot partition info\n"); - goto failed; + cse_trigger_recovery(CSE_LITE_SKU_COMMUNICATION_ERROR); } - if (!cse_is_rw_info_valid(&cse_bp_info.bp_info)) { printk(BIOS_ERR, "cse_bp: CSE RW partition is not valid\n"); - goto failed; + cse_trigger_recovery(CSE_LITE_SKU_RW_JUMP_ERROR); } if (!cse_boot_to_rw(&cse_bp_info.bp_info)) { printk(BIOS_ERR, "cse_bp: Failed to switch to RW\n"); - goto failed; + cse_trigger_recovery(CSE_LITE_SKU_RW_SWITCH_ERROR); } - return; -failed: - do_global_reset(); } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_ENTRY, cse_fw_sync, NULL); From 3fd5a1bbbb7a112544975045a0c4ac1f3ea82202 Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Tue, 19 May 2020 20:21:36 +0530 Subject: [PATCH 0002/1155] mb/google/dedede: Enable coreboot lock down config TEST=Build and boot waddledoo board Change-Id: Ic10af9a0d50946a98a5c4a77b492d242cef171ca Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/41535 Reviewed-by: Furquan Shaikh Reviewed-by: Karthik Ramasubramanian Tested-by: build bot (Jenkins) --- src/mainboard/google/dedede/variants/baseboard/devicetree.cb | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index fc4397689e..72ce7c1821 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -140,6 +140,7 @@ chip soc/intel/jasperlake #+-------------------+---------------------------+ #| Field | Value | #+-------------------+---------------------------+ + #| chipset_lockdown | CHIPSET_LOCKDOWN_COREBOOT | #| GSPI0 | cr50 TPM. Early init is | #| | required to set up a BAR | #| | for TPM communication | @@ -151,6 +152,7 @@ chip soc/intel/jasperlake #| I2C4 | Audio | #+-------------------+---------------------------+ register "common_soc_config" = "{ + .chipset_lockdown = CHIPSET_LOCKDOWN_COREBOOT, .gspi[0] = { .speed_mhz = 1, .early_init = 1, From 29c6169efdac2a93fa1d891e476644b203443f5b Mon Sep 17 00:00:00 2001 From: Aamir Bohra Date: Mon, 16 Mar 2020 14:47:27 +0530 Subject: [PATCH 0003/1155] mb/google/dedede: Add SD card support 1. Configure SD card GPIOs. 2. Set SD card power polarity and card detect configs. SD card CMD. DATA and CLK GPIOs are set for native pad termination as per recommendation in EDS vol1 section 10.4.10 BUG=b:150872580 TEST=Verify SD card enumeration and read/write transactions. Change-Id: I90c8ceb85ada23718ff7b6fd7013317c818dd532 Signed-off-by: Aamir Bohra Reviewed-on: https://review.coreboot.org/c/coreboot/+/39237 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- .../dedede/variants/baseboard/devicetree.cb | 7 +++++- .../google/dedede/variants/baseboard/gpio.c | 22 +++++++++++-------- 2 files changed, 19 insertions(+), 10 deletions(-) diff --git a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb index 72ce7c1821..a856b222c1 100644 --- a/src/mainboard/google/dedede/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/dedede/variants/baseboard/devicetree.cb @@ -114,6 +114,11 @@ chip soc/intel/jasperlake # Enable EMMC HS400 mode register "ScsEmmcHs400Enabled" = "1" + # GPIO for SD card detect + register "sdcard_cd_gpio" = "VGPIO_39" + # SD card power enable polarity + register "SdCardPowerEnableActiveHigh" = "1" + # Display related UPDs # Select eDP for port A register "DdiPortAConfig" = "1" @@ -255,7 +260,7 @@ chip soc/intel/jasperlake register "wake" = "GPE0_PME_B0" device pci 14.3 on end # CNVi wifi end - device pci 14.5 off end # SDCard + device pci 14.5 on end # SDCard device pci 15.0 on end # I2C 0 device pci 15.1 on end # I2C 1 device pci 15.2 on end # I2C 2 diff --git a/src/mainboard/google/dedede/variants/baseboard/gpio.c b/src/mainboard/google/dedede/variants/baseboard/gpio.c index ca28e3d525..e62140e2d1 100644 --- a/src/mainboard/google/dedede/variants/baseboard/gpio.c +++ b/src/mainboard/google/dedede/variants/baseboard/gpio.c @@ -267,26 +267,26 @@ static const struct pad_config gpio_table[] = { PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1), /* G0 : SD_CMD */ - PAD_NC(GPP_G0, NONE), + PAD_CFG_NF(GPP_G0, NATIVE, DEEP, NF1), /* G1 : SD_DATA0 */ - PAD_NC(GPP_G1, NONE), + PAD_CFG_NF(GPP_G1, NATIVE, DEEP, NF1), /* G2 : SD_DATA1 */ - PAD_NC(GPP_G2, NONE), + PAD_CFG_NF(GPP_G2, NATIVE, DEEP, NF1), /* G3 : SD_DATA2 */ - PAD_NC(GPP_G3, NONE), + PAD_CFG_NF(GPP_G3, NATIVE, DEEP, NF1), /* G4 : SD_DATA3 */ - PAD_NC(GPP_G4, NONE), + PAD_CFG_NF(GPP_G4, NATIVE, DEEP, NF1), /* G5 : SD_CD_ODL */ - PAD_NC(GPP_G5, NONE), + PAD_CFG_NF(GPP_G5, NONE, PLTRST, NF1), /* G6 : SD_CLK */ - PAD_NC(GPP_G6, NONE), + PAD_CFG_NF(GPP_G6, NATIVE, DEEP, NF1), /* G7 : SD_SDIO_WP */ - PAD_NC(GPP_G7, NONE), + PAD_CFG_NF(GPP_G7, DN_20K, DEEP, NF1), /* H0 : WWAN_PERST */ PAD_NC(GPP_H0, NONE), /* H1 : EN_PP3300_SD_U */ - PAD_NC(GPP_H1, NONE), + PAD_CFG_NF(GPP_H1, NONE, DEEP, NF1), /* H2 : CNV_CLKREQ0 */ PAD_CFG_NF(GPP_H2, NONE, DEEP, NF3), /* H3 : GPP_H03/SX_EXIT_HOLDOFF_N */ @@ -382,6 +382,10 @@ static const struct pad_config gpio_table[] = { PAD_NC(GPD9, NONE), /* GPD10 : AP_SLP_S5_L */ PAD_NC(GPD10, NONE), + + /* SD card detect virtual GPIO */ + PAD_CFG_GPI_GPIO_DRIVER(VGPIO_39, NONE, PLTRST), + }; /* Early pad configuration in bootblock */ From af983db3f4c0825a9645d343ccac2b114f8814e8 Mon Sep 17 00:00:00 2001 From: Paul Fagerburg Date: Thu, 21 May 2020 17:13:48 -0600 Subject: [PATCH 0004/1155] util/mb/google: add templates for dedede boards Add template directories for the Waddledee and Waddledoo reference boards of the Dedede baseboard. BUG=b:157183582 BRANCH=None TEST=N/A Signed-off-by: Paul Fagerburg Change-Id: Ida70a44097334991a93fec8f4933d7f6e39a187b Reviewed-on: https://review.coreboot.org/c/coreboot/+/41640 Tested-by: build bot (Jenkins) Reviewed-by: Karthik Ramasubramanian --- .../google/waddledee/template/Makefile.inc | 3 + .../waddledee/template/include/variant/ec.h | 8 +++ .../waddledee/template/include/variant/gpio.h | 8 +++ .../google/waddledee/template/overridetree.cb | 42 ++++++++++++++ .../google/waddledoo/template/Makefile.inc | 3 + .../template/include/variant/acpi/camera.asl | 3 + .../waddledoo/template/include/variant/ec.h | 8 +++ .../waddledoo/template/include/variant/gpio.h | 8 +++ .../google/waddledoo/template/overridetree.cb | 58 +++++++++++++++++++ 9 files changed, 141 insertions(+) create mode 100644 util/mainboard/google/waddledee/template/Makefile.inc create mode 100644 util/mainboard/google/waddledee/template/include/variant/ec.h create mode 100644 util/mainboard/google/waddledee/template/include/variant/gpio.h create mode 100644 util/mainboard/google/waddledee/template/overridetree.cb create mode 100644 util/mainboard/google/waddledoo/template/Makefile.inc create mode 100644 util/mainboard/google/waddledoo/template/include/variant/acpi/camera.asl create mode 100644 util/mainboard/google/waddledoo/template/include/variant/ec.h create mode 100644 util/mainboard/google/waddledoo/template/include/variant/gpio.h create mode 100644 util/mainboard/google/waddledoo/template/overridetree.cb diff --git a/util/mainboard/google/waddledee/template/Makefile.inc b/util/mainboard/google/waddledee/template/Makefile.inc new file mode 100644 index 0000000000..68611944f0 --- /dev/null +++ b/util/mainboard/google/waddledee/template/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +SPD_SOURCES += empty #0b0000 diff --git a/util/mainboard/google/waddledee/template/include/variant/ec.h b/util/mainboard/google/waddledee/template/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/util/mainboard/google/waddledee/template/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/util/mainboard/google/waddledee/template/include/variant/gpio.h b/util/mainboard/google/waddledee/template/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/util/mainboard/google/waddledee/template/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/util/mainboard/google/waddledee/template/overridetree.cb b/util/mainboard/google/waddledee/template/overridetree.cb new file mode 100644 index 0000000000..404024b1d6 --- /dev/null +++ b/util/mainboard/google/waddledee/template/overridetree.cb @@ -0,0 +1,42 @@ +chip soc/intel/jasperlake + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + }, + }" + + device domain 0 on + device pci 15.0 on end + end +end diff --git a/util/mainboard/google/waddledoo/template/Makefile.inc b/util/mainboard/google/waddledoo/template/Makefile.inc new file mode 100644 index 0000000000..fd8d1268f3 --- /dev/null +++ b/util/mainboard/google/waddledoo/template/Makefile.inc @@ -0,0 +1,3 @@ +## SPDX-License-Identifier: GPL-2.0-or-later + +SPD_SOURCES = empty #0b0000 diff --git a/util/mainboard/google/waddledoo/template/include/variant/acpi/camera.asl b/util/mainboard/google/waddledoo/template/include/variant/acpi/camera.asl new file mode 100644 index 0000000000..318b0dea04 --- /dev/null +++ b/util/mainboard/google/waddledoo/template/include/variant/acpi/camera.asl @@ -0,0 +1,3 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include diff --git a/util/mainboard/google/waddledoo/template/include/variant/ec.h b/util/mainboard/google/waddledoo/template/include/variant/ec.h new file mode 100644 index 0000000000..08870e0627 --- /dev/null +++ b/util/mainboard/google/waddledoo/template/include/variant/ec.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_EC_H +#define MAINBOARD_EC_H + +#include + +#endif diff --git a/util/mainboard/google/waddledoo/template/include/variant/gpio.h b/util/mainboard/google/waddledoo/template/include/variant/gpio.h new file mode 100644 index 0000000000..9078664608 --- /dev/null +++ b/util/mainboard/google/waddledoo/template/include/variant/gpio.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#ifndef MAINBOARD_GPIO_H +#define MAINBOARD_GPIO_H + +#include + +#endif /* MAINBOARD_GPIO_H */ diff --git a/util/mainboard/google/waddledoo/template/overridetree.cb b/util/mainboard/google/waddledoo/template/overridetree.cb new file mode 100644 index 0000000000..69ea1e16f2 --- /dev/null +++ b/util/mainboard/google/waddledoo/template/overridetree.cb @@ -0,0 +1,58 @@ +chip soc/intel/jasperlake + + # USB Port Configuration + register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Camera + + # Intel Common SoC Config + #+-------------------+---------------------------+ + #| Field | Value | + #+-------------------+---------------------------+ + #| GSPI0 | cr50 TPM. Early init is | + #| | required to set up a BAR | + #| | for TPM communication | + #| | before memory is up | + #| I2C0 | Trackpad | + #| I2C1 | Digitizer | + #| I2C2 | Touchscreen | + #| I2C3 | Camera | + #| I2C4 | Audio | + #+-------------------+---------------------------+ + register "common_soc_config" = "{ + .gspi[0] = { + .speed_mhz = 1, + .early_init = 1, + }, + .i2c[0] = { + .speed = I2C_SPEED_FAST, + .rise_time_ns = 66, + .fall_time_ns = 90, + .data_hold_time_ns = 350, + }, + .i2c[1] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[2] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[3] = { + .speed = I2C_SPEED_FAST, + }, + .i2c[4] = { + .speed = I2C_SPEED_FAST, + .speed_config[0] = { + .speed = I2C_SPEED_FAST, + .scl_lcnt = 176, + .scl_hcnt = 95, + .sda_hold = 36, + } + }, + }" + device domain 0 on + device pci 14.0 on end + device pci 15.0 on end + device pci 15.2 on end + device pci 1c.7 on end + device pci 19.0 on end + device pci 1f.3 on end + end +end From f219b6a2b9f9528e4a182d9b035af900ae740c2a Mon Sep 17 00:00:00 2001 From: Usha P Date: Thu, 14 May 2020 13:13:06 +0530 Subject: [PATCH 0005/1155] mb/google/dedede: Enable GBB configs for dedede This patch enables the necessary GBB configs for dedede BUG=none BRANCH=none TEST=GBB Flag value was 0x39 before enabling the required flags and now it is updated to 0x40b9. Verfied from CPU log. Change-Id: Ica07c65d6cf23ea859de6aa8413377661547e47a Signed-off-by: Usha P Reviewed-on: https://review.coreboot.org/c/coreboot/+/41405 Tested-by: build bot (Jenkins) Reviewed-by: Maulik V Vaghela Reviewed-by: Meera Ravindranath --- src/mainboard/google/dedede/Kconfig | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/src/mainboard/google/dedede/Kconfig b/src/mainboard/google/dedede/Kconfig index 85dbc38ea4..d9f5ada495 100644 --- a/src/mainboard/google/dedede/Kconfig +++ b/src/mainboard/google/dedede/Kconfig @@ -29,6 +29,10 @@ config CHROMEOS default y select EC_GOOGLE_CHROMEEC_SWITCHES select GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC + select GBB_FLAG_FORCE_DEV_SWITCH_ON + select GBB_FLAG_FORCE_DEV_BOOT_USB + select GBB_FLAG_FORCE_DEV_BOOT_LEGACY + select GBB_FLAG_FORCE_MANUAL_RECOVERY select VBOOT_LID_SWITCH config DEVICETREE From 5d79a0cc5ad7e58b240be3d3531bfa1df225534d Mon Sep 17 00:00:00 2001 From: John Zhao Date: Wed, 13 May 2020 16:44:38 -0700 Subject: [PATCH 0006/1155] mb/google/volteer: Enable TCSS DMA0 for Volteer This explicitly enables TCSS DMA0 controller and disables TBT PCIe2 and PCIE3 since they are unused on volteer. BUG=:b:146624360 TEST=Built and booted on Volteer. Signed-off-by: John Zhao Change-Id: I05cc9e3964d8037d433fca443be6e8d5b444bbce Reviewed-on: https://review.coreboot.org/c/coreboot/+/41387 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- .../google/volteer/variants/baseboard/devicetree.cb | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index c6a2e8b1a6..b7f2a0a3de 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -132,7 +132,6 @@ chip soc/intel/tigerlake register "IomTypeCPortPadCfg[6]" = "0x0" register "IomTypeCPortPadCfg[7]" = "0x0" - # D3Hot and D3Cold for TCSS register "TcssD3HotEnable" = "1" register "TcssD3ColdEnable" = "1" @@ -227,16 +226,16 @@ chip soc/intel/tigerlake device pci 04.0 on end # DPTF 0x9A03 device pci 05.0 off end # IPU 0x9A19 device pci 06.0 off end # PEG60 0x9A09 - device pci 07.0 on end # TBT_PCIe0 0x9A23 - device pci 07.1 on end # TBT_PCIe1 0x9A25 - device pci 07.2 on end # TBT_PCIe2 0x9A27 - device pci 07.3 on end # TBT_PCIe3 0x9A29 + device pci 07.0 on end # TBT_PCIe0 0x9A23 + device pci 07.1 on end # TBT_PCIe1 0x9A25 + device pci 07.2 off end # TBT_PCIe2 0x9A27 + device pci 07.3 off end # TBT_PCIe3 0x9A29 device pci 08.0 on end # GNA 0x9A11 device pci 09.0 off end # NPK 0x9A33 device pci 0a.0 off end # Crash-log SRAM 0x9A0D device pci 0d.0 on end # USB xHCI 0x9A13 device pci 0d.1 off end # USB xDCI (OTG) 0x9A15 - device pci 0d.2 off end # TBT DMA0 0x9A1B + device pci 0d.2 on end # TBT DMA0 0x9A1B device pci 0d.3 off end # TBT DMA1 0x9A1D device pci 0e.0 off end # VMD 0x9A0B From 924fe94075b9559d8f6469413cf61589c49538da Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Wed, 29 Apr 2020 09:48:09 +0200 Subject: [PATCH 0007/1155] soc/intel/denverton_ns: Fix 16-bit read/write PCI_COMMAND register Change-Id: I23ca0c50b0b3c71710173b84d98c2e170ed3e45b Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40842 Reviewed-by: Nico Huber Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/soc/intel/denverton_ns/lpc.c | 12 +++++------- src/soc/intel/denverton_ns/smihandler.c | 8 ++++---- 2 files changed, 9 insertions(+), 11 deletions(-) diff --git a/src/soc/intel/denverton_ns/lpc.c b/src/soc/intel/denverton_ns/lpc.c index d08405e58f..05c648438c 100644 --- a/src/soc/intel/denverton_ns/lpc.c +++ b/src/soc/intel/denverton_ns/lpc.c @@ -514,24 +514,22 @@ static void pch_hide_devfn(uint32_t devfn) { /* TODO */ } void southcluster_enable_dev(struct device *dev) { - u32 reg32; + u16 reg16; if (!dev->enabled) { printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Hide this device if possible */ pch_hide_devfn(dev->path.pci.devfn); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } diff --git a/src/soc/intel/denverton_ns/smihandler.c b/src/soc/intel/denverton_ns/smihandler.c index 6b53964667..b81eb1157f 100644 --- a/src/soc/intel/denverton_ns/smihandler.c +++ b/src/soc/intel/denverton_ns/smihandler.c @@ -49,7 +49,7 @@ static void busmaster_disable_on_bus(int bus) for (slot = 0; slot < 0x20; slot++) { for (func = 0; func < 8; func++) { - u32 reg32; + u16 reg16; pci_devfn_t dev = PCI_DEV(bus, slot, func); val = pci_read_config32(dev, PCI_VENDOR_ID); @@ -59,9 +59,9 @@ static void busmaster_disable_on_bus(int bus) continue; /* Disable Bus Mastering for this one device */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~PCI_COMMAND_MASTER; + pci_write_config16(dev, PCI_COMMAND, reg16); /* If this is a bridge, then follow it. */ hdr = pci_read_config8(dev, PCI_HEADER_TYPE); From 4247ba362876db21507cdad9a681248e29771afe Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Wed, 27 May 2020 12:26:41 -0700 Subject: [PATCH 0008/1155] acpi: Add definitions for device sleep states The ACPI device sleep states are different from system sleep states and many places hardcode to specific values that are difficult to decode without referring to the spec. Change-Id: If5e732725b775742fd2a9fd0df697e312aa7bf20 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/41791 Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/include/acpi/acpi.h | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/include/acpi/acpi.h b/src/include/acpi/acpi.h index ea80e3ba75..34cb6ea4ff 100644 --- a/src/include/acpi/acpi.h +++ b/src/include/acpi/acpi.h @@ -31,6 +31,14 @@ #define SLP_TYP_S5 5 #endif +/* ACPI Device Sleep States */ +#define ACPI_DEVICE_SLEEP_D0 0 +#define ACPI_DEVICE_SLEEP_D1 1 +#define ACPI_DEVICE_SLEEP_D2 2 +#define ACPI_DEVICE_SLEEP_D3 3 +#define ACPI_DEVICE_SLEEP_D3_HOT ACPI_DEVICE_SLEEP_D3 +#define ACPI_DEVICE_SLEEP_D3_COLD 4 + #define ACPI_TABLE_CREATOR "COREBOOT" /* Must be exactly 8 bytes long! */ #define OEM_ID "COREv4" /* Must be exactly 6 bytes long! */ From b781680d6edb876dbf5ce5a935b7918f590f5fdf Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Wed, 27 May 2020 17:29:30 +0200 Subject: [PATCH 0009/1155] cpu/x86/mtrr.h: Get rid of commonlib/helpers.h dependency We want to use the CACHE_ROM_* macros in linker scripts. Avoid `commonlib/helpers.h` as it contains an ALIGN() macro definition that conflicts with the ALIGN keyword in linker scripts. Change-Id: I3bf20733418ca4135f364a3f6489e74d45e4f466 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41785 Reviewed-by: Angel Pons Reviewed-by: HAOUAS Elyes Tested-by: build bot (Jenkins) --- src/include/cpu/x86/mtrr.h | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 50148ffd35..301ea3052d 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -1,7 +1,6 @@ #ifndef CPU_X86_MTRR_H #define CPU_X86_MTRR_H -#include #ifndef __ASSEMBLER__ #include #include @@ -187,8 +186,8 @@ static inline unsigned int fls(unsigned int x) /* Last but not least, most (if not all) chipsets have MMIO between 0xfe000000 and 0xff000000, so limit to 16MiB. */ -#if CAR_CACHE_ROM_SIZE >= 16 * MiB -# define CACHE_ROM_SIZE (16 * MiB) +#if CAR_CACHE_ROM_SIZE >= 16 << 20 +# define CACHE_ROM_SIZE (16 << 20) #else # define CACHE_ROM_SIZE CAR_CACHE_ROM_SIZE #endif From a9117ed49645a9e87c61398680711bb8fa1230e4 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Thu, 28 May 2020 11:02:13 -0700 Subject: [PATCH 0010/1155] drivers/vpd: rename VPD_ANY to VPD_RO_THEN_RW Rename VPD_ANY to VPD_RO_THEN_RW, to reflect the VPD region search preference. Update all existing code references for VPD_ANY. Signed-off-by: Jonathan Zhang Change-Id: I960688d1f6ab199768107ab73b8a7400a3fdf473 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41586 Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/drivers/vpd/vpd.h | 2 +- src/mainboard/google/reef/variants/snappy/mainboard.c | 2 +- src/vendorcode/google/chromeos/sar.c | 2 +- src/vendorcode/google/chromeos/vpd_calibration.c | 2 +- src/vendorcode/google/chromeos/vpd_mac.c | 2 +- src/vendorcode/google/chromeos/vpd_serialno.c | 2 +- src/vendorcode/google/chromeos/wrdd.c | 2 +- 7 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index d54cef8df1..df7711af90 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -8,7 +8,7 @@ #define GOOGLE_VPD_2_0_OFFSET 0x600 enum vpd_region { - VPD_ANY = 0, + VPD_RO_THEN_RW = 0, VPD_RO = 1, VPD_RW = 2 }; diff --git a/src/mainboard/google/reef/variants/snappy/mainboard.c b/src/mainboard/google/reef/variants/snappy/mainboard.c index 0dd7529ae3..fc0652cf91 100644 --- a/src/mainboard/google/reef/variants/snappy/mainboard.c +++ b/src/mainboard/google/reef/variants/snappy/mainboard.c @@ -46,7 +46,7 @@ uint8_t variant_board_sku(void) if (!CONFIG(CHROMEOS)) return board_sku_num; - if (!vpd_gets(vpd_skuid, vpd_buffer, ARRAY_SIZE(vpd_buffer), VPD_ANY)) + if (!vpd_gets(vpd_skuid, vpd_buffer, ARRAY_SIZE(vpd_buffer), VPD_RO_THEN_RW)) return board_sku_num; vpd_len = strlen(vpd_buffer); diff --git a/src/vendorcode/google/chromeos/sar.c b/src/vendorcode/google/chromeos/sar.c index ab4f3d206a..b07d41d3bd 100644 --- a/src/vendorcode/google/chromeos/sar.c +++ b/src/vendorcode/google/chromeos/sar.c @@ -70,7 +70,7 @@ int get_wifi_sar_limits(struct wifi_sar_limits *sar_limits) /* Try to read the SAR limit entry from VPD */ if (!vpd_gets(wifi_sar_limit_key, wifi_sar_limit_str, - buffer_size, VPD_ANY)) { + buffer_size, VPD_RO_THEN_RW)) { printk(BIOS_ERR, "Error: Could not locate '%s' in VPD.\n", wifi_sar_limit_key); diff --git a/src/vendorcode/google/chromeos/vpd_calibration.c b/src/vendorcode/google/chromeos/vpd_calibration.c index 3dc58d1097..ab862c808d 100644 --- a/src/vendorcode/google/chromeos/vpd_calibration.c +++ b/src/vendorcode/google/chromeos/vpd_calibration.c @@ -99,7 +99,7 @@ static size_t fill_up_entries_cache(struct vpd_blob_cache_t *cache, strcpy(cache->key_name, templates[i]); cache->key_name[index_location] = j + '0'; - payload = vpd_find(cache->key_name, &payload_size, VPD_ANY); + payload = vpd_find(cache->key_name, &payload_size, VPD_RO_THEN_RW); if (!payload) continue; diff --git a/src/vendorcode/google/chromeos/vpd_mac.c b/src/vendorcode/google/chromeos/vpd_mac.c index 097afcbac0..385b9f475d 100644 --- a/src/vendorcode/google/chromeos/vpd_mac.c +++ b/src/vendorcode/google/chromeos/vpd_mac.c @@ -73,7 +73,7 @@ void lb_table_add_macs_from_vpd(struct lb_header *header) * in the VPD - move on. */ if (!vpd_gets(mac_addr_key, mac_addr_str, - sizeof(mac_addr_str), VPD_ANY)) + sizeof(mac_addr_str), VPD_RO_THEN_RW)) break; if (!macs) { diff --git a/src/vendorcode/google/chromeos/vpd_serialno.c b/src/vendorcode/google/chromeos/vpd_serialno.c index 9ee4f6fa76..9a3aa81ceb 100644 --- a/src/vendorcode/google/chromeos/vpd_serialno.c +++ b/src/vendorcode/google/chromeos/vpd_serialno.c @@ -15,7 +15,7 @@ void lb_table_add_serialno_from_vpd(struct lb_header *header) size_t len; if (!vpd_gets(serialno_key, serialno, - sizeof(serialno), VPD_ANY)) { + sizeof(serialno), VPD_RO_THEN_RW)) { printk(BIOS_ERR, "no serial number in vpd\n"); return; } diff --git a/src/vendorcode/google/chromeos/wrdd.c b/src/vendorcode/google/chromeos/wrdd.c index e9d7247539..524a7e0e62 100644 --- a/src/vendorcode/google/chromeos/wrdd.c +++ b/src/vendorcode/google/chromeos/wrdd.c @@ -48,7 +48,7 @@ uint16_t wifi_regulatory_domain(void) /* If not found for any reason fall backto the default value */ if (!vpd_gets(wrdd_domain_key, wrdd_domain_code, - ARRAY_SIZE(wrdd_domain_code), VPD_ANY)) { + ARRAY_SIZE(wrdd_domain_code), VPD_RO_THEN_RW)) { printk(BIOS_DEBUG, "Error: Could not locate '%s' in VPD\n", wrdd_domain_key); return WRDD_DEFAULT_REGULATORY_DOMAIN; From 9b110bf97ae1da0eb60e76df6957fae044d71554 Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Thu, 28 May 2020 13:35:44 -0700 Subject: [PATCH 0011/1155] drivers/vpd: add VPD region VPD_RW_THEN_RO This change is based on the concept that system user's (overwrite) settings are held in VPD_RW region, while system owner's (default) settings are held in VPD_RO region. Add VPD_RW_THEN_RO region type, so that VPD_RW region is searched first to get overwrite setting, otherwise VPD_RO region is searched to get default setting. Signed-off-by: Jonathan Zhang Change-Id: Icd7cbd9c3fb2a6b02fc417ad45d7d22ca6795457 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41732 Tested-by: build bot (Jenkins) Reviewed-by: Hung-Te Lin --- src/drivers/vpd/vpd.c | 8 ++++++-- src/drivers/vpd/vpd.h | 7 ++++--- 2 files changed, 10 insertions(+), 5 deletions(-) diff --git a/src/drivers/vpd/vpd.c b/src/drivers/vpd/vpd.c index f5ac81ebfd..c332a6e94c 100644 --- a/src/drivers/vpd/vpd.c +++ b/src/drivers/vpd/vpd.c @@ -209,10 +209,14 @@ const void *vpd_find(const char *key, int *size, enum vpd_region region) init_vpd_rdevs(); - if (region != VPD_RW) + if (region == VPD_RW_THEN_RO) + vpd_find_in(&rw_vpd, &arg); + + if (!arg.matched && (region == VPD_RO || region == VPD_RO_THEN_RW || + region == VPD_RW_THEN_RO)) vpd_find_in(&ro_vpd, &arg); - if (!arg.matched && region != VPD_RO) + if (!arg.matched && (region == VPD_RW || region == VPD_RO_THEN_RW)) vpd_find_in(&rw_vpd, &arg); if (!arg.matched) diff --git a/src/drivers/vpd/vpd.h b/src/drivers/vpd/vpd.h index df7711af90..25e0aed4ee 100644 --- a/src/drivers/vpd/vpd.h +++ b/src/drivers/vpd/vpd.h @@ -8,9 +8,10 @@ #define GOOGLE_VPD_2_0_OFFSET 0x600 enum vpd_region { - VPD_RO_THEN_RW = 0, - VPD_RO = 1, - VPD_RW = 2 + VPD_RO, + VPD_RW, + VPD_RO_THEN_RW, + VPD_RW_THEN_RO }; /* From d09459fe30bb9876ca72ba5a34024cfbb2f98e79 Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 26 May 2020 22:13:09 +0200 Subject: [PATCH 0012/1155] util/sconfig: Refactor and fix add_register() add_register() contained a duplicate check but only compared the new key to the first (smallest in order) list member. Fix that and factor the list handling out so it can be used by other functions. Change-Id: I5a8346f36fa024351e1282c9681868ecf451b283 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41743 Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- util/sconfig/main.c | 37 +++++++++++++++++++------------------ 1 file changed, 19 insertions(+), 18 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 6676baea90..3e3bd17098 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -528,33 +528,34 @@ void add_resource(struct bus *bus, int type, int index, int base) new_resource(bus->dev, type, index, base); } -void add_register(struct chip_instance *chip_instance, char *name, char *val) +static void add_reg(struct reg **const head, char *const name, char *const val) { - struct reg *r = S_ALLOC(sizeof(struct reg)); + struct reg *const r = S_ALLOC(sizeof(struct reg)); + struct reg *prev = NULL; + struct reg *cur; r->key = name; r->value = val; - if (chip_instance->reg) { - struct reg *head = chip_instance->reg; - // sorting to be equal to sconfig's behaviour - int sort = strcmp(r->key, head->key); + + for (cur = *head; cur != NULL; prev = cur, cur = cur->next) { + const int sort = strcmp(r->key, cur->key); if (sort == 0) { printf("ERROR: duplicate 'register' key.\n"); exit(1); } - if (sort < 0) { - r->next = head; - chip_instance->reg = r; - } else { - while ((head->next) - && (strcmp(head->next->key, r->key) < 0)) - head = head->next; - r->next = head->next; - head->next = r; - } - } else { - chip_instance->reg = r; + if (sort < 0) + break; } + r->next = cur; + if (prev) + prev->next = r; + else + *head = r; +} + +void add_register(struct chip_instance *chip_instance, char *name, char *val) +{ + add_reg(&chip_instance->reg, name, val); } void add_slot_desc(struct bus *bus, char *type, char *length, char *designation, From 57bbcb3dff99f5eeba390ccd216cd4306107582b Mon Sep 17 00:00:00 2001 From: Nico Huber Date: Tue, 26 May 2020 22:39:47 +0200 Subject: [PATCH 0013/1155] util/sconfig: Move default includes out of emit_chips() This should make it easier to add more includes. Change-Id: Ib4a25352901408c2b36de4972391df742a0d8037 Signed-off-by: Nico Huber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41744 Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- util/sconfig/main.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 3e3bd17098..0d8f7f86af 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -889,9 +889,6 @@ static void emit_chip_headers(FILE *fil, struct chip *chip) { struct chip *tmp = chip; - fprintf(fil, "#include \n"); - fprintf(fil, "#include \n"); - while (chip) { if (chip->chiph_exists) fprintf(fil, "#include \"%s/chip.h\"\n", chip->name); @@ -1347,6 +1344,9 @@ int main(int argc, char **argv) fprintf(autohead, "#define __STATIC_DEVICE_TREE_H\n\n"); fprintf(autohead, "#include \n\n"); + fprintf(autogen, "#include \n"); + fprintf(autogen, "#include \n\n"); + emit_chips(autogen); walk_device_tree(autogen, autohead, &base_root_dev, inherit_subsystem_ids); From 9657fc2bd95955b22b5b4fb19e1a98d632f1887a Mon Sep 17 00:00:00 2001 From: Wim Vervoorn Date: Thu, 28 May 2020 13:50:33 +0200 Subject: [PATCH 0014/1155] commonlib: Add CBFS_TYPE_BOOTBLOCK MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Add CBFS_TYPE_BOOTBLOCK to allow accessing the bootblock as a CBFS file. BUG=N/A TEST=build Change-Id: Ibb03ac3a6cd8711e0402e47335bb8e110c6ef61a Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/41824 Reviewed-by: Kyösti Mälkki Reviewed-by: Frans Hendriks Tested-by: build bot (Jenkins) --- src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h | 1 + 1 file changed, 1 insertion(+) diff --git a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h index d2fc6267ad..af4baf512b 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h +++ b/src/commonlib/bsd/include/commonlib/bsd/cbfs_serialized.h @@ -21,6 +21,7 @@ #define CBFS_TYPE_DELETED 0x00000000 #define CBFS_TYPE_DELETED2 0xffffffff +#define CBFS_TYPE_BOOTBLOCK 0x01 #define CBFS_TYPE_STAGE 0x10 #define CBFS_TYPE_SELF 0x20 #define CBFS_TYPE_FIT 0x21 From ad2eb28c10652ee5ad5a899ff1ff8805c43fd5ab Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Mon, 25 May 2020 06:45:08 +0300 Subject: [PATCH 0015/1155] mb/facebook/fbg1701: Remove C_ENV_BOOTBLOCK_SIZE MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Remove the use of C_ENV_BOOTBLOCK_SIZE. Verify the bootblock by reading the CBFS file instead of directly accessing the datablock. BUG=None BRANCH=None TEST=tested on facebook fbg1701 Change-Id: I4254d681525327c7eec18832586818e9c4e8eb22 Signed-off-by: Wim Vervoorn Reviewed-on: https://review.coreboot.org/c/coreboot/+/41694 Reviewed-by: Angel Pons Reviewed-by: Frans Hendriks Reviewed-by: Kyösti Mälkki Tested-by: build bot (Jenkins) --- src/mainboard/facebook/fbg1701/board_verified_boot.c | 12 ++++-------- src/mainboard/facebook/fbg1701/board_verified_boot.h | 1 + 2 files changed, 5 insertions(+), 8 deletions(-) diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.c b/src/mainboard/facebook/fbg1701/board_verified_boot.c index 57bd199543..a03c6fc615 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.c +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.c @@ -8,10 +8,8 @@ const verify_item_t bootblock_verify_list[] = { { VERIFY_FILE, ROMSTAGE, { { NULL, CBFS_TYPE_STAGE } }, HASH_IDX_ROM_STAGE, MBOOT_PCR_INDEX_0 }, - { VERIFY_BLOCK, "BootBlock", - { { (void *)0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, - CONFIG_C_ENV_BOOTBLOCK_SIZE, } }, HASH_IDX_BOOTBLOCK, - MBOOT_PCR_INDEX_0 }, + { VERIFY_FILE, BOOTBLOCK, { { NULL, CBFS_TYPE_BOOTBLOCK } }, + HASH_IDX_BOOTBLOCK, MBOOT_PCR_INDEX_0 }, #if CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST) { VERIFY_BLOCK, "PublicKey", { { (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION, @@ -34,10 +32,8 @@ const verify_item_t romstage_verify_list[] = { MBOOT_PCR_INDEX_1 }, { VERIFY_FILE, "spd.bin", { { NULL, CBFS_TYPE_SPD } }, HASH_IDX_SPD0, MBOOT_PCR_INDEX_1 }, - { VERIFY_BLOCK, "BootBlock", - { { (void *)0xffffffff - CONFIG_C_ENV_BOOTBLOCK_SIZE + 1, - CONFIG_C_ENV_BOOTBLOCK_SIZE, } }, HASH_IDX_BOOTBLOCK, - MBOOT_PCR_INDEX_0 }, + { VERIFY_FILE, BOOTBLOCK, { { NULL, CBFS_TYPE_BOOTBLOCK } }, + HASH_IDX_BOOTBLOCK, MBOOT_PCR_INDEX_0 }, #if CONFIG(VENDORCODE_ELTAN_VBOOT_SIGNED_MANIFEST) { VERIFY_BLOCK, "PublicKey", { { (void *)CONFIG_VENDORCODE_ELTAN_VBOOT_KEY_LOCATION, diff --git a/src/mainboard/facebook/fbg1701/board_verified_boot.h b/src/mainboard/facebook/fbg1701/board_verified_boot.h index 589006b510..b5ff5f838a 100644 --- a/src/mainboard/facebook/fbg1701/board_verified_boot.h +++ b/src/mainboard/facebook/fbg1701/board_verified_boot.h @@ -6,6 +6,7 @@ #include /* Define the items to be measured or verified */ +#define BOOTBLOCK (const char *)"bootblock" #define FSP (const char *)"fsp.bin" #define CMOS_LAYOUT (const char *)"cmos_layout.bin" #define RAMSTAGE (const char *)CONFIG_CBFS_PREFIX"/ramstage" From 3855a9806e5dd4ed47af99f0d2efb4d9a45b6e0a Mon Sep 17 00:00:00 2001 From: Arthur Heymans Date: Tue, 19 May 2020 09:16:54 +0200 Subject: [PATCH 0016/1155] soc/intel/xeon_sp/skx: Let iasl automatically resolve _PRT package size BUILD_TIMELESS=1 with ocp/tiogapass results in identical binaries. Change-Id: Iff97f3cc0ce800036be32b2758c60e4b7ac39fe9 Signed-off-by: Arthur Heymans Reviewed-on: https://review.coreboot.org/c/coreboot/+/41529 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov Reviewed-by: Angel Pons Reviewed-by: Paul Menzel --- src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl | 196 +++++++++--------- 1 file changed, 98 insertions(+), 98 deletions(-) diff --git a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl index 2f5328f100..9926367536 100644 --- a/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl +++ b/src/soc/intel/xeon_sp/skx/acpi/uncore_irq.asl @@ -7,225 +7,225 @@ */ #define GEN_PCIE_LEGACY_IRQ() \ - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ - Package (0x04) { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ - Package (0x04) { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ - Package (0x04) { 0x0003FFFF, 0x00, LNKA, 0x00 } + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0001FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0002FFFF, 0x00, LNKA, 0x00 }, \ + Package () { 0x0003FFFF, 0x00, LNKA, 0x00 } #define GEN_UNCORE_LEGACY_IRQ(dev) \ - Package (0x04) { ##dev, 0x00, LNKA, 0x00 }, \ - Package (0x04) { ##dev, 0x01, LNKB, 0x00 }, \ - Package (0x04) { ##dev, 0x02, LNKC, 0x00 }, \ - Package (0x04) { ##dev, 0x03, LNKD, 0x00 } + Package () { ##dev, 0x00, LNKA, 0x00 }, \ + Package () { ##dev, 0x01, LNKB, 0x00 }, \ + Package () { ##dev, 0x02, LNKC, 0x00 }, \ + Package () { ##dev, 0x03, LNKD, 0x00 } #define GEN_PCIE_IOAPIC_IRQ(irq) \ - Package (0x04) { 0x0000FFFF, 0x00, 0x00, ##irq }, \ - Package (0x04) { 0x0001FFFF, 0x00, 0x00, ##irq }, \ - Package (0x04) { 0x0002FFFF, 0x00, 0x00, ##irq }, \ - Package (0x04) { 0x0003FFFF, 0x00, 0x00, ##irq } + Package () { 0x0000FFFF, 0x00, 0x00, ##irq }, \ + Package () { 0x0001FFFF, 0x00, 0x00, ##irq }, \ + Package () { 0x0002FFFF, 0x00, 0x00, ##irq }, \ + Package () { 0x0003FFFF, 0x00, 0x00, ##irq } #define GEN_UNCORE_IOAPIC_IRQ(dev,irq1,irq2,irq3,irq4) \ - Package (0x04) { ##dev, 0x00, 0x00, ##irq1 }, \ - Package (0x04) { ##dev, 0x01, 0x00, ##irq2 }, \ - Package (0x04) { ##dev, 0x02, 0x00, ##irq3 }, \ - Package (0x04) { ##dev, 0x03, 0x00, ##irq4 } + Package () { ##dev, 0x00, 0x00, ##irq1 }, \ + Package () { ##dev, 0x01, 0x00, ##irq2 }, \ + Package () { ##dev, 0x02, 0x00, ##irq3 }, \ + Package () { ##dev, 0x03, 0x00, ##irq4 } // Socket 0, IIOStack 0 device legacy interrupt routing Name (PR00, Package (0x28) { // [DMI0]: Legacy PCI Express Port 0 - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, // [CB0A]: CBDMA // [CB0E]: CBDMA - Package (0x04) { 0x0004FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0004FFFF, 0x00, LNKA, 0x00 }, // [CB0B]: CBDMA // [CB0F]: CBDMA - Package (0x04) { 0x0004FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0004FFFF, 0x01, LNKB, 0x00 }, // [CB0C]: CBDMA // [CB0G]: CBDMA - Package (0x04) { 0x0004FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0004FFFF, 0x02, LNKC, 0x00 }, // [CB0D]: CBDMA // [CB0H]: CBDMA - Package (0x04) { 0x0004FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0004FFFF, 0x03, LNKD, 0x00 }, // Uncore 0 UBOX Device - Package (0x04) { 0x0008FFFF, 0x00, LNKA, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x01, LNKB, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x02, LNKC, 0x00 }, - Package (0x04) { 0x0008FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0008FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0008FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0008FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0008FFFF, 0x03, LNKD, 0x00 }, // [DISP]: Display Controller - Package (0x04) { 0x000FFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x000FFFFF, 0x00, LNKA, 0x00 }, // [IHC1]: HECI #1 // [IHC3]: HECI #3 - Package (0x04) { 0x0010FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0010FFFF, 0x00, LNKA, 0x00 }, // [IHC2]: HECI #2 - Package (0x04) { 0x0010FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0010FFFF, 0x01, LNKB, 0x00 }, // [IIDR]: IDE-Redirection (IDE-R) - Package (0x04) { 0x0010FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0010FFFF, 0x02, LNKC, 0x00 }, // [IMKT]: Keyboard and Text (KT) Redirection - Package (0x04) { 0x0010FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0010FFFF, 0x03, LNKD, 0x00 }, // [SAT2]: sSATA Host controller 2 on PCH - Package (0x04) { 0x0011FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0011FFFF, 0x00, LNKA, 0x00 }, // // [XHCI]: xHCI controller 1 on PCH - Package (0x04) { 0x0014FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0014FFFF, 0x00, LNKA, 0x00 }, // [OTG0]: USB Device Controller (OTG) on PCH - Package (0x04) { 0x0014FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0014FFFF, 0x01, LNKB, 0x00 }, // [TERM]: Thermal Subsystem on PCH - Package (0x04) { 0x0014FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0014FFFF, 0x02, LNKC, 0x00 }, // [CAMR]: Camera IO Host Controller on PCH - Package (0x04) { 0x0014FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0014FFFF, 0x03, LNKD, 0x00 }, // [HEC1]: HECI #1 on PCH // [HEC3]: HECI #3 on PCH - Package (0x04) { 0x0016FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0016FFFF, 0x00, LNKA, 0x00 }, // [HEC2]: HECI #2 on PCH - Package (0x04) { 0x0016FFFF, 0x01, LNKB, 0x00 }, + Package () { 0x0016FFFF, 0x01, LNKB, 0x00 }, // [IDER]: ME IDE redirect on PCH - Package (0x04) { 0x0016FFFF, 0x02, LNKC, 0x00 }, + Package () { 0x0016FFFF, 0x02, LNKC, 0x00 }, // [MEKT]: MEKT on PCH - Package (0x04) { 0x0016FFFF, 0x03, LNKD, 0x00 }, + Package () { 0x0016FFFF, 0x03, LNKD, 0x00 }, // [SAT1]: SATA controller 1 on PCH - Package (0x04) { 0x0017FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0017FFFF, 0x00, LNKA, 0x00 }, // [NAN1]: NAND Cycle Router on PCH - Package (0x04) { 0x0018FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0018FFFF, 0x00, LNKA, 0x00 }, // [RP17]: PCIE PCH Root Port #17 - Package (0x04) { 0x001BFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001BFFFF, 0x00, LNKA, 0x00 }, // [RP18]: PCIE PCH Root Port #18 - Package (0x04) { 0x001BFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x001BFFFF, 0x01, LNKB, 0x00 }, // [RP19]: PCIE PCH Root Port #19 - Package (0x04) { 0x001BFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001BFFFF, 0x02, LNKC, 0x00 }, // [RP20]: PCIE PCH Root Port #20 - Package (0x04) { 0x001BFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001BFFFF, 0x03, LNKD, 0x00 }, // [RP01]: PCIE PCH Root Port #1 // [RP05]: PCIE PCH Root Port #5 - Package (0x04) { 0x001CFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001CFFFF, 0x00, LNKA, 0x00 }, // [RP02]: PCIE PCH Root Port #2 // [RP06]: PCIE PCH Root Port #6 - Package (0x04) { 0x001CFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x001CFFFF, 0x01, LNKB, 0x00 }, // [RP03]: PCIE PCH Root Port #3 // [RP07]: PCIE PCH Root Port #7 - Package (0x04) { 0x001CFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001CFFFF, 0x02, LNKC, 0x00 }, // [RP04]: PCIE PCH Root Port #4 // [RP08]: PCIE PCH Root Port #8 - Package (0x04) { 0x001CFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001CFFFF, 0x03, LNKD, 0x00 }, // [RP09]: PCIE PCH Root Port #9 // [RP13]: PCIE PCH Root Port #13 - Package (0x04) { 0x001DFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001DFFFF, 0x00, LNKA, 0x00 }, // [RP10]: PCIE PCH Root Port #10 // [RP14]: PCIE PCH Root Port #14 - Package (0x04) { 0x001DFFFF, 0x01, LNKB, 0x00 }, + Package () { 0x001DFFFF, 0x01, LNKB, 0x00 }, // [RP11]: PCIE PCH Root Port #11 // [RP15]: PCIE PCH Root Port #15 - Package (0x04) { 0x001DFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001DFFFF, 0x02, LNKC, 0x00 }, // [RP12]: PCIE PCH Root Port #12 // [RP16]: PCIE PCH Root Port #16 - Package (0x04) { 0x001DFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001DFFFF, 0x03, LNKD, 0x00 }, // [UAR0]: UART #0 on PCH - Package (0x04) { 0x001EFFFF, 0x02, LNKC, 0x00 }, + Package () { 0x001EFFFF, 0x02, LNKC, 0x00 }, // [UAR1]: UART #1 on PCH - Package (0x04) { 0x001EFFFF, 0x03, LNKD, 0x00 }, + Package () { 0x001EFFFF, 0x03, LNKD, 0x00 }, // [CAVS]: HD Audio Subsystem Controller on PCH // [SMBS]: SMBus controller on PCH // [GBE1]: GbE Controller on PCH // [NTPK]: Northpeak Controller on PCH - Package (0x04) { 0x001FFFFF, 0x00, LNKA, 0x00 }, + Package () { 0x001FFFFF, 0x00, LNKA, 0x00 }, }) // Socket 0, IIOStack 0 device IOAPIC interrupt routing Name (AR00, Package (0x28) { // [DMI0]: Legacy PCI Express Port 0 - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x1F }, + Package () { 0x0000FFFF, 0x00, 0x00, 0x1F }, // [CB0A]: CB3DMA // [CB0E]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x1A }, + Package () { 0x0004FFFF, 0x00, 0x00, 0x1A }, // [CB0B]: CB3DMA // [CB0F]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x1B }, + Package () { 0x0004FFFF, 0x01, 0x00, 0x1B }, // [CB0C]: CB3DMA // [CB0G]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A }, + Package () { 0x0004FFFF, 0x02, 0x00, 0x1A }, // [CB0D]: CB3DMA // [CB0H]: CB3DMA - Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B }, + Package () { 0x0004FFFF, 0x03, 0x00, 0x1B }, // [UBX0]: Uncore 0 UBOX Device - Package (0x04) { 0x0008FFFF, 0x00, 0x00, 0x18 }, - Package (0x04) { 0x0008FFFF, 0x01, 0x00, 0x1C }, - Package (0x04) { 0x0008FFFF, 0x02, 0x00, 0x1D }, - Package (0x04) { 0x0008FFFF, 0x03, 0x00, 0x1E }, + Package () { 0x0008FFFF, 0x00, 0x00, 0x18 }, + Package () { 0x0008FFFF, 0x01, 0x00, 0x1C }, + Package () { 0x0008FFFF, 0x02, 0x00, 0x1D }, + Package () { 0x0008FFFF, 0x03, 0x00, 0x1E }, // [DISP]: Display Controller - Package (0x04) { 0x000FFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x000FFFFF, 0x00, 0x00, 0x10 }, // [IHC1]: HECI #1 // [IHC3]: HECI #3 - Package (0x04) { 0x0010FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0010FFFF, 0x00, 0x00, 0x10 }, // [IHC2]: HECI #2 - Package (0x04) { 0x0010FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0010FFFF, 0x01, 0x00, 0x11 }, // [IIDR]: IDE-Redirection (IDE-R) - Package (0x04) { 0x0010FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0010FFFF, 0x02, 0x00, 0x12 }, // [IMKT]: Keyboard and Text (KT) Redirection - Package (0x04) { 0x0010FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0010FFFF, 0x03, 0x00, 0x13 }, // [SAT2]: sSATA Host controller 2 on PCH - Package (0x04) { 0x0011FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0011FFFF, 0x00, 0x00, 0x10 }, // [XHCI]: xHCI controller 1 on PCH - Package (0x04) { 0x0014FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0014FFFF, 0x00, 0x00, 0x10 }, // [OTG0]: USB Device Controller (OTG) on PCH - Package (0x04) { 0x0014FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0014FFFF, 0x01, 0x00, 0x11 }, // [TERM]: Thermal Subsystem on PCH - Package (0x04) { 0x0014FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0014FFFF, 0x02, 0x00, 0x12 }, // [CAMR]: Camera IO Host Controller on PCH - Package (0x04) { 0x0014FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0014FFFF, 0x03, 0x00, 0x13 }, // [HEC1]: HECI #1 on PCH // [HEC3]: HECI #3 on PCH - Package (0x04) { 0x0016FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0016FFFF, 0x00, 0x00, 0x10 }, // [HEC2]: HECI #2 on PCH - Package (0x04) { 0x0016FFFF, 0x01, 0x00, 0x11 }, + Package () { 0x0016FFFF, 0x01, 0x00, 0x11 }, // [IDER]: ME IDE redirect on PCH - Package (0x04) { 0x0016FFFF, 0x02, 0x00, 0x12 }, + Package () { 0x0016FFFF, 0x02, 0x00, 0x12 }, // [MEKT]: MEKT on PCH - Package (0x04) { 0x0016FFFF, 0x03, 0x00, 0x13 }, + Package () { 0x0016FFFF, 0x03, 0x00, 0x13 }, // [SAT1]: SATA controller 1 on PCH - Package (0x04) { 0x0017FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0017FFFF, 0x00, 0x00, 0x10 }, // [NAN1]: NAND Cycle Router on PCH - Package (0x04) { 0x0018FFFF, 0x00, 0x00, 0x10 }, + Package () { 0x0018FFFF, 0x00, 0x00, 0x10 }, // [RP17]: PCIE PCH Root Port #17 - Package (0x04) { 0x001BFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001BFFFF, 0x00, 0x00, 0x10 }, // [RP18]: PCIE PCH Root Port #18 - Package (0x04) { 0x001BFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x001BFFFF, 0x01, 0x00, 0x11 }, // [RP19]: PCIE PCH Root Port #19 - Package (0x04) { 0x001BFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x001BFFFF, 0x02, 0x00, 0x12 }, // [RP20]: PCIE PCH Root Port #20 - Package (0x04) { 0x001BFFFF, 0x03, 0x00, 0x13 }, + Package () { 0x001BFFFF, 0x03, 0x00, 0x13 }, // [RP01]: PCIE PCH Root Port #1 // [RP05]: PCIE PCH Root Port #5 - Package (0x04) { 0x001CFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001CFFFF, 0x00, 0x00, 0x10 }, // [RP02]: PCIE PCH Root Port #2 // [RP06]: PCIE PCH Root Port #6 - Package (0x04) { 0x001CFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x001CFFFF, 0x01, 0x00, 0x11 }, // [RP03]: PCIE PCH Root Port #3 // [RP07]: PCIE PCH Root Port #7 - Package (0x04) { 0x001CFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x001CFFFF, 0x02, 0x00, 0x12 }, // [RP04]: PCIE PCH Root Port #4 // [RP08]: PCIE PCH Root Port #8 - Package (0x04) { 0x001CFFFF, 0x03, 0x00, 0x13 }, + Package () { 0x001CFFFF, 0x03, 0x00, 0x13 }, // [RP09]: PCIE PCH Root Port #9 // [RP13]: PCIE PCH Root Port #13 - Package (0x04) { 0x001DFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001DFFFF, 0x00, 0x00, 0x10 }, // [RP10]: PCIE PCH Root Port #10 // [RP14]: PCIE PCH Root Port #14 - Package (0x04) { 0x001DFFFF, 0x01, 0x00, 0x11 }, + Package () { 0x001DFFFF, 0x01, 0x00, 0x11 }, // [RP11]: PCIE PCH Root Port #11 // [RP15]: PCIE PCH Root Port #15 - Package (0x04) { 0x001DFFFF, 0x02, 0x00, 0x12 }, + Package () { 0x001DFFFF, 0x02, 0x00, 0x12 }, // [RP12]: PCIE PCH Root Port #12 // [RP16]: PCIE PCH Root Port #16 - Package (0x04) { 0x001DFFFF, 0x03, 0x00, 0x13 }, + Package () { 0x001DFFFF, 0x03, 0x00, 0x13 }, // [UAR0]: UART #0 on PCH - Package (0x04) { 0x001EFFFF, 0x02, 0x00, 0x16 }, + Package () { 0x001EFFFF, 0x02, 0x00, 0x16 }, // [UAR1]: UART #1 on PCH - Package (0x04) { 0x001EFFFF, 0x03, 0x00, 0x17 }, + Package () { 0x001EFFFF, 0x03, 0x00, 0x17 }, // [CAVS]: HD Audio Subsystem Controller on PCH // [SMBS]: SMBus controller on PCH // [GBE1]: GbE Controller on PCH // [NTPK]: Northpeak Controller on PCH - Package (0x04) { 0x001FFFFF, 0x00, 0x00, 0x10 }, + Package () { 0x001FFFFF, 0x00, 0x00, 0x10 }, }) // Socket 0, IIOStack 1 device legacy interrupt routing @@ -406,7 +406,7 @@ Name (AR28, Package (0x20) Name (PR40, Package (0x09) { // DMI - Package (0x04) { 0x0000FFFF, 0x00, LNKA, 0x00 }, + Package () { 0x0000FFFF, 0x00, LNKA, 0x00 }, // CBDMA GEN_UNCORE_LEGACY_IRQ(0x0004FFFF), @@ -419,7 +419,7 @@ Name (PR40, Package (0x09) Name (AR40, Package (0x09) { // DMI - Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x4F }, + Package () { 0x0000FFFF, 0x00, 0x00, 0x4F }, // CBDMA GEN_UNCORE_IOAPIC_IRQ(0x0004FFFF, 0x4A, 0x4B, 0x4A, 0x4B), From a895344936594402175b2f4321b0e1a9d5dbfe7b Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Daniel=20Gr=C3=B6ber?= Date: Tue, 26 May 2020 22:21:27 +0200 Subject: [PATCH 0017/1155] lockdown: Fix missing spaces in boot log MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I414703c53d356c6a69be515596c178997eed82e3 Signed-off-by: Daniel Gröber Reviewed-on: https://review.coreboot.org/c/coreboot/+/41748 Reviewed-by: Arthur Heymans Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/security/lockdown/lockdown.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/security/lockdown/lockdown.c b/src/security/lockdown/lockdown.c index 81478cc044..c2e2ac3501 100644 --- a/src/security/lockdown/lockdown.c +++ b/src/security/lockdown/lockdown.c @@ -28,7 +28,7 @@ void boot_device_security_lockdown(void) printk(BIOS_DEBUG, "'WP_RO only'"); lock_type = CTRLR_WP; } - printk(BIOS_DEBUG, "using CTRL...\n"); + printk(BIOS_DEBUG, " using CTRL...\n"); } else { if (CONFIG(BOOTMEDIA_LOCK_WHOLE_RO)) { printk(BIOS_DEBUG, "'readonly'"); @@ -37,7 +37,7 @@ void boot_device_security_lockdown(void) printk(BIOS_DEBUG, "'WP_RO only'"); lock_type = MEDIA_WP; } - printk(BIOS_DEBUG, "using flash chip...\n"); + printk(BIOS_DEBUG, " using flash chip...\n"); } if (CONFIG(BOOTMEDIA_LOCK_WPRO_VBOOT_RO)) { From c62c98a884231ef36bf3eb613b2d24e37c89c4d2 Mon Sep 17 00:00:00 2001 From: Rocky Phagura Date: Sat, 23 May 2020 20:29:00 -0700 Subject: [PATCH 0018/1155] soc/intel/xeon_sp: Early programming of ACPI bar ACPI bar was not programmed previously for which is needed to enable SMI's and to check SMI status registers. The architecture of Lewisburg PCH is very similar to SunrisePoint PCH thus we can use code from soc/intel/skylake. TEST=build for Tiogapass and check ACPI base. Log message will now show pmbase=501 (bit 0 is enable) instead of 0. Check by reading and writing to io port 0x500. Change-Id: If5a0c4daabf5c35dc2852434fe46712ac9b06379 Signed-off-by: Rocky Phagura Reviewed-on: https://review.coreboot.org/c/coreboot/+/41680 Tested-by: build bot (Jenkins) Reviewed-by: Maxim Polyakov --- src/soc/intel/xeon_sp/Makefile.inc | 2 +- src/soc/intel/xeon_sp/bootblock.c | 2 + src/soc/intel/xeon_sp/include/soc/bootblock.h | 11 ++++ src/soc/intel/xeon_sp/include/soc/pch.h | 12 +++++ src/soc/intel/xeon_sp/include/soc/pmc.h | 32 ++++++++---- src/soc/intel/xeon_sp/pch.c | 50 +++++++++++++++++++ 6 files changed, 97 insertions(+), 12 deletions(-) create mode 100644 src/soc/intel/xeon_sp/include/soc/bootblock.h create mode 100644 src/soc/intel/xeon_sp/include/soc/pch.h create mode 100644 src/soc/intel/xeon_sp/pch.c diff --git a/src/soc/intel/xeon_sp/Makefile.inc b/src/soc/intel/xeon_sp/Makefile.inc index 7950b814fb..9589e5a88b 100644 --- a/src/soc/intel/xeon_sp/Makefile.inc +++ b/src/soc/intel/xeon_sp/Makefile.inc @@ -5,7 +5,7 @@ ifeq ($(CONFIG_XEON_SP_COMMON_BASE),y) subdirs-$(CONFIG_SOC_INTEL_SKYLAKE_SP) += skx subdirs-$(CONFIG_SOC_INTEL_COOPERLAKE_SP) += cpx -bootblock-y += bootblock.c spi.c lpc.c gpio.c +bootblock-y += bootblock.c spi.c lpc.c gpio.c pch.c romstage-y += romstage.c reset.c util.c spi.c gpio.c ramstage-y += uncore.c reset.c util.c lpc.c spi.c gpio.c postcar-y += spi.c diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 7f14be6329..72d9742af8 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -9,6 +9,7 @@ #include #include #include +#include const FSPT_UPD temp_ram_init_params = { .FspUpdHeader = { @@ -53,4 +54,5 @@ void bootblock_soc_init(void) { if (CONFIG(BOOTBLOCK_CONSOLE)) printk(BIOS_DEBUG, "FSP TempRamInit successful...\n"); + bootblock_pch_init(); } diff --git a/src/soc/intel/xeon_sp/include/soc/bootblock.h b/src/soc/intel/xeon_sp/include/soc/bootblock.h new file mode 100644 index 0000000000..6be4370454 --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/bootblock.h @@ -0,0 +1,11 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_XEON_SP_BOOTBLOCK_H_ +#define _SOC_XEON_SP_BOOTBLOCK_H_ + +#include "iomap.h" + +/* Bootblock post console init programming */ +void bootblock_pch_init(void); + +#endif diff --git a/src/soc/intel/xeon_sp/include/soc/pch.h b/src/soc/intel/xeon_sp/include/soc/pch.h new file mode 100644 index 0000000000..84d5e4896b --- /dev/null +++ b/src/soc/intel/xeon_sp/include/soc/pch.h @@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef _SOC_PCH_H_ +#define _SOC_PCH_H_ + +#include + +#if ENV_RAMSTAGE +void pch_disable_devfn(struct device *dev); +#endif + +#endif /* _SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/include/soc/pmc.h b/src/soc/intel/xeon_sp/include/soc/pmc.h index 74343f84c8..d3bad1b715 100644 --- a/src/soc/intel/xeon_sp/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/include/soc/pmc.h @@ -3,18 +3,28 @@ #ifndef _SOC_PMC_H_ #define _SOC_PMC_H_ -/* PCI Configuration Space (D31:F2): PMC */ -#define PMC_ACPI_CNT 0x44 + /* PCI Configuration Space (D31:F2): PMC */ +#define ABASE 0x40 +#define ACTL 0x44 +#define PMC_ACPI_CNT 0x44 +#define PWRM_EN (1 << 8) +#define ACPI_EN (1 << 7) +#define SCI_IRQ_SEL (7 << 0) +#define SCI_IRQ_ADJUST 0 -#define SCI_IRQ_SEL (7 << 0) -#define SCIS_IRQ9 0 -#define SCIS_IRQ10 1 -#define SCIS_IRQ11 2 -#define SCIS_IRQ20 4 -#define SCIS_IRQ21 5 -#define SCIS_IRQ22 6 -#define SCIS_IRQ23 7 +#define SCIS_IRQ9 0 +#define SCIS_IRQ10 1 +#define SCIS_IRQ11 2 +#define SCIS_IRQ20 4 +#define SCIS_IRQ21 5 +#define SCIS_IRQ22 6 +#define SCIS_IRQ23 7 +#define PWRMBASE 0x48 +#define GEN_PMCON_A 0xa0 +#define SMI_LOCK (1 << 4) +#define GEN_PMCON_B 0xa4 +#define SLP_STR_POL_LOCK (1 << 18) +#define ACPI_BASE_LOCK (1 << 17) -#define SCI_IRQ_ADJUST 0 #endif diff --git a/src/soc/intel/xeon_sp/pch.c b/src/soc/intel/xeon_sp/pch.c new file mode 100644 index 0000000000..5427952688 --- /dev/null +++ b/src/soc/intel/xeon_sp/pch.c @@ -0,0 +1,50 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +#define PCR_DMI_DMICTL 0x2234 +#define PCR_DMI_DMICTL_SRLOCK (1 << 31) +#define PCR_DMI_ACPIBA 0x27B4 +#define PCR_DMI_ACPIBDID 0x27B8 +#define PCR_DMI_PMBASEA 0x27AC +#define PCR_DMI_PMBASEC 0x27B0 + +static void soc_config_acpibase(void) +{ + uint32_t reg32; + + /* Disable ABASE in PMC Device first before changing Base Address */ + reg32 = pci_read_config32(PCH_DEV_PMC, ACTL); + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 & ~ACPI_EN); + + /* Program ACPI Base */ + pci_write_config32(PCH_DEV_PMC, ABASE, ACPI_BASE_ADDRESS); + + /* Enable ACPI in PMC */ + pci_write_config32(PCH_DEV_PMC, ACTL, reg32 | ACPI_EN); + + uint32_t data = pci_read_config32(PCH_DEV_PMC, ABASE); + printk(BIOS_INFO, "%s : pmbase = %x\n", __func__, (int)data); + /* + * Program "ACPI Base Address" PCR[DMI] + 27B4h[23:18, 15:2, 0] + * to [0x3F, PMC PCI Offset 40h bit[15:2], 1] + */ + reg32 = (0x3f << 18) | ACPI_BASE_ADDRESS | 1; + pcr_write32(PID_DMI, PCR_DMI_ACPIBA, reg32); + pcr_write32(PID_DMI, PCR_DMI_ACPIBDID, 0x23a8); +} + +void bootblock_pch_init(void) +{ + /* + * Enabling ABASE for accessing PM1_STS, PM1_EN, PM1_CNT + */ + soc_config_acpibase(); +} From 9d00242e24b5e50d4560878b332d9ddf0beabe70 Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sun, 19 Apr 2020 16:12:55 -0400 Subject: [PATCH 0019/1155] mb/asus/p2b: Add p3b-f IRQ routing to DSDT Change-Id: Ie4d24eee1cffd65707887dd621e3de873d20cf01 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/41097 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/mainboard/asus/p2b/dsdt.asl | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/src/mainboard/asus/p2b/dsdt.asl b/src/mainboard/asus/p2b/dsdt.asl index c1ac5996c6..e1bda176a9 100644 --- a/src/mainboard/asus/p2b/dsdt.asl +++ b/src/mainboard/asus/p2b/dsdt.asl @@ -141,6 +141,17 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, OEM_ID, ACPI_TABLE_CREATOR, 1) Package (0x04) { 0x000CFFFF, 2, LNKC, 0 }, Package (0x04) { 0x000CFFFF, 3, LNKD, 0 }, +#if CONFIG(BOARD_ASUS_P3B_F) + Package (0x04) { 0x000DFFFF, 0, LNKD, 0 }, + Package (0x04) { 0x000DFFFF, 1, LNKA, 0 }, + Package (0x04) { 0x000DFFFF, 2, LNKB, 0 }, + Package (0x04) { 0x000DFFFF, 3, LNKC, 0 }, + + Package (0x04) { 0x000EFFFF, 0, LNKC, 0 }, + Package (0x04) { 0x000EFFFF, 1, LNKD, 0 }, + Package (0x04) { 0x000EFFFF, 2, LNKA, 0 }, + Package (0x04) { 0x000EFFFF, 3, LNKB, 0 }, +#endif }) #include #include From 32da3437f92f1c7e19b81e3bc99b4951d5268502 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 17 May 2020 17:15:31 +0200 Subject: [PATCH 0020/1155] src: Remove unused '#include ' Also, replace 'lapic.h' by 'lapic_def.h' in 'soc/intel/braswell/northcluster.c'. Change-Id: I71cff43d53660dc1e5a760ac3034bcf75f93c6e7 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41489 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/cpu/amd/smm/smm_init.c | 1 - src/cpu/intel/haswell/smmrelocate.c | 1 - src/cpu/intel/hyperthreading/intel_sibling.c | 1 - src/cpu/x86/mtrr/mtrr.c | 1 - src/mainboard/amd/gardenia/mptable.c | 1 - src/mainboard/amd/olivehill/mptable.c | 1 - src/mainboard/amd/parmer/mptable.c | 1 - src/mainboard/amd/thatcher/mptable.c | 1 - src/mainboard/asrock/imb-a180/mptable.c | 1 - src/mainboard/asus/am1i-a/mptable.c | 1 - src/mainboard/asus/f2a85-m/mptable.c | 1 - src/mainboard/bap/ode_e20XX/mptable.c | 1 - src/mainboard/bap/ode_e21XX/mptable.c | 1 - src/mainboard/bap/ode_e21XX/romstage.c | 1 - src/mainboard/biostar/a68n_5200/mptable.c | 1 - src/mainboard/biostar/am1ml/mptable.c | 1 - src/mainboard/gizmosphere/gizmo2/mptable.c | 1 - src/mainboard/google/butterfly/early_init.c | 1 - src/mainboard/google/kahlee/mptable.c | 1 - src/mainboard/google/link/early_init.c | 1 - src/mainboard/google/parrot/early_init.c | 1 - src/mainboard/google/stout/early_init.c | 1 - src/mainboard/hp/abm/mptable.c | 1 - src/mainboard/hp/pavilion_m6_1035dx/mptable.c | 1 - src/mainboard/intel/emeraldlake2/early_init.c | 1 - src/mainboard/kontron/ktqm77/early_init.c | 1 - src/mainboard/lenovo/g505s/mptable.c | 1 - src/mainboard/lenovo/x1_carbon_gen1/early_init.c | 1 - src/mainboard/lenovo/x201/mainboard.c | 1 - src/mainboard/lenovo/x220/early_init.c | 1 - src/mainboard/lenovo/x230/variants/x230/early_init.c | 1 - src/mainboard/msi/ms7721/mptable.c | 1 - src/mainboard/packardbell/ms2290/mainboard.c | 1 - src/mainboard/samsung/lumpy/early_init.c | 1 - src/mainboard/samsung/stumpy/early_init.c | 1 - src/northbridge/amd/agesa/family14/northbridge.c | 1 - src/soc/amd/common/block/smbus/sm.c | 1 - src/soc/intel/braswell/northcluster.c | 2 +- src/soc/intel/broadwell/smmrelocate.c | 1 - src/soc/intel/cannonlake/smmrelocate.c | 1 - src/soc/intel/icelake/smmrelocate.c | 1 - src/soc/intel/jasperlake/smmrelocate.c | 1 - src/soc/intel/skylake/smmrelocate.c | 1 - src/soc/intel/tigerlake/smmrelocate.c | 1 - src/soc/intel/xeon_sp/uncore.c | 2 +- src/southbridge/amd/agesa/hudson/sm.c | 1 - src/southbridge/amd/pi/hudson/sm.c | 1 - 47 files changed, 2 insertions(+), 47 deletions(-) diff --git a/src/cpu/amd/smm/smm_init.c b/src/cpu/amd/smm/smm_init.c index 0de8fba085..71cca82b23 100644 --- a/src/cpu/amd/smm/smm_init.c +++ b/src/cpu/amd/smm/smm_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/cpu/intel/haswell/smmrelocate.c b/src/cpu/intel/haswell/smmrelocate.c index 1c961881ed..0f7585ae69 100644 --- a/src/cpu/intel/haswell/smmrelocate.c +++ b/src/cpu/intel/haswell/smmrelocate.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/cpu/intel/hyperthreading/intel_sibling.c b/src/cpu/intel/hyperthreading/intel_sibling.c index 9febc839c5..329b693140 100644 --- a/src/cpu/intel/hyperthreading/intel_sibling.c +++ b/src/cpu/intel/hyperthreading/intel_sibling.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 6187578c0a..1f37659503 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -19,7 +19,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/amd/gardenia/mptable.c b/src/mainboard/amd/gardenia/mptable.c index 3528a13ce1..6460fedb8b 100644 --- a/src/mainboard/amd/gardenia/mptable.c +++ b/src/mainboard/amd/gardenia/mptable.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/amd/olivehill/mptable.c b/src/mainboard/amd/olivehill/mptable.c index ab321c0d5c..4761728927 100644 --- a/src/mainboard/amd/olivehill/mptable.c +++ b/src/mainboard/amd/olivehill/mptable.c @@ -5,7 +5,6 @@ #include #include #include -#include #include u8 picr_data[0x54] = { diff --git a/src/mainboard/amd/parmer/mptable.c b/src/mainboard/amd/parmer/mptable.c index 28866e8cec..c7aa69eee6 100644 --- a/src/mainboard/amd/parmer/mptable.c +++ b/src/mainboard/amd/parmer/mptable.c @@ -5,7 +5,6 @@ #include #include #include -#include #include u8 picr_data[0x54] = { diff --git a/src/mainboard/amd/thatcher/mptable.c b/src/mainboard/amd/thatcher/mptable.c index 8b8bc03b0a..bc091e5125 100644 --- a/src/mainboard/amd/thatcher/mptable.c +++ b/src/mainboard/amd/thatcher/mptable.c @@ -5,7 +5,6 @@ #include #include #include -#include #include u8 picr_data[] = { diff --git a/src/mainboard/asrock/imb-a180/mptable.c b/src/mainboard/asrock/imb-a180/mptable.c index 2a35eb9bda..20c4b8d781 100644 --- a/src/mainboard/asrock/imb-a180/mptable.c +++ b/src/mainboard/asrock/imb-a180/mptable.c @@ -5,7 +5,6 @@ #include #include #include -#include #include diff --git a/src/mainboard/asus/am1i-a/mptable.c b/src/mainboard/asus/am1i-a/mptable.c index 5caa78384e..cd72ca3927 100644 --- a/src/mainboard/asus/am1i-a/mptable.c +++ b/src/mainboard/asus/am1i-a/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/asus/f2a85-m/mptable.c b/src/mainboard/asus/f2a85-m/mptable.c index 7d9dcc3a69..e3c7d80028 100644 --- a/src/mainboard/asus/f2a85-m/mptable.c +++ b/src/mainboard/asus/f2a85-m/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/bap/ode_e20XX/mptable.c b/src/mainboard/bap/ode_e20XX/mptable.c index b854b75297..c0ad4ed349 100644 --- a/src/mainboard/bap/ode_e20XX/mptable.c +++ b/src/mainboard/bap/ode_e20XX/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/bap/ode_e21XX/mptable.c b/src/mainboard/bap/ode_e21XX/mptable.c index 0d8c942462..c5aeeb0b4e 100644 --- a/src/mainboard/bap/ode_e21XX/mptable.c +++ b/src/mainboard/bap/ode_e21XX/mptable.c @@ -5,7 +5,6 @@ #include #include #include -#include #include u8 picr_data[0x54] = { diff --git a/src/mainboard/bap/ode_e21XX/romstage.c b/src/mainboard/bap/ode_e21XX/romstage.c index 74b8517c73..6b116fd46f 100644 --- a/src/mainboard/bap/ode_e21XX/romstage.c +++ b/src/mainboard/bap/ode_e21XX/romstage.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/biostar/a68n_5200/mptable.c b/src/mainboard/biostar/a68n_5200/mptable.c index ab321c0d5c..4761728927 100644 --- a/src/mainboard/biostar/a68n_5200/mptable.c +++ b/src/mainboard/biostar/a68n_5200/mptable.c @@ -5,7 +5,6 @@ #include #include #include -#include #include u8 picr_data[0x54] = { diff --git a/src/mainboard/biostar/am1ml/mptable.c b/src/mainboard/biostar/am1ml/mptable.c index 7a028007aa..41e70b9b5f 100644 --- a/src/mainboard/biostar/am1ml/mptable.c +++ b/src/mainboard/biostar/am1ml/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/gizmosphere/gizmo2/mptable.c b/src/mainboard/gizmosphere/gizmo2/mptable.c index b854b75297..c0ad4ed349 100644 --- a/src/mainboard/gizmosphere/gizmo2/mptable.c +++ b/src/mainboard/gizmosphere/gizmo2/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/butterfly/early_init.c b/src/mainboard/google/butterfly/early_init.c index 21d59d18ac..df51f66518 100644 --- a/src/mainboard/google/butterfly/early_init.c +++ b/src/mainboard/google/butterfly/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/google/kahlee/mptable.c b/src/mainboard/google/kahlee/mptable.c index 3528a13ce1..6460fedb8b 100644 --- a/src/mainboard/google/kahlee/mptable.c +++ b/src/mainboard/google/kahlee/mptable.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include diff --git a/src/mainboard/google/link/early_init.c b/src/mainboard/google/link/early_init.c index 27f086cea4..8360f2ac24 100644 --- a/src/mainboard/google/link/early_init.c +++ b/src/mainboard/google/link/early_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/parrot/early_init.c b/src/mainboard/google/parrot/early_init.c index cff8438f5d..3c5c36369b 100644 --- a/src/mainboard/google/parrot/early_init.c +++ b/src/mainboard/google/parrot/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/google/stout/early_init.c b/src/mainboard/google/stout/early_init.c index 1b73fc0d36..e71d0eec78 100644 --- a/src/mainboard/google/stout/early_init.c +++ b/src/mainboard/google/stout/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/hp/abm/mptable.c b/src/mainboard/hp/abm/mptable.c index ab321c0d5c..4761728927 100644 --- a/src/mainboard/hp/abm/mptable.c +++ b/src/mainboard/hp/abm/mptable.c @@ -5,7 +5,6 @@ #include #include #include -#include #include u8 picr_data[0x54] = { diff --git a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c index 4433c71bcd..c620be253e 100644 --- a/src/mainboard/hp/pavilion_m6_1035dx/mptable.c +++ b/src/mainboard/hp/pavilion_m6_1035dx/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 6e1f7e3a8f..119346efb7 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/kontron/ktqm77/early_init.c b/src/mainboard/kontron/ktqm77/early_init.c index 31eb05b645..b8f44b5561 100644 --- a/src/mainboard/kontron/ktqm77/early_init.c +++ b/src/mainboard/kontron/ktqm77/early_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/g505s/mptable.c b/src/mainboard/lenovo/g505s/mptable.c index 19ac198b46..bc1759a5c1 100644 --- a/src/mainboard/lenovo/g505s/mptable.c +++ b/src/mainboard/lenovo/g505s/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c index a709450678..f5299ea94d 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/early_init.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/early_init.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/lenovo/x201/mainboard.c b/src/mainboard/lenovo/x201/mainboard.c index beb99385f5..1a306b1695 100644 --- a/src/mainboard/lenovo/x201/mainboard.c +++ b/src/mainboard/lenovo/x201/mainboard.c @@ -6,7 +6,6 @@ #include #include "dock.h" #include -#include #include static void fill_ssdt(const struct device *device) diff --git a/src/mainboard/lenovo/x220/early_init.c b/src/mainboard/lenovo/x220/early_init.c index f87a9d48d2..5f0ad456be 100644 --- a/src/mainboard/lenovo/x220/early_init.c +++ b/src/mainboard/lenovo/x220/early_init.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/lenovo/x230/variants/x230/early_init.c b/src/mainboard/lenovo/x230/variants/x230/early_init.c index 2089ee6bb2..e6c4ffa038 100644 --- a/src/mainboard/lenovo/x230/variants/x230/early_init.c +++ b/src/mainboard/lenovo/x230/variants/x230/early_init.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/msi/ms7721/mptable.c b/src/mainboard/msi/ms7721/mptable.c index 7d9dcc3a69..e3c7d80028 100644 --- a/src/mainboard/msi/ms7721/mptable.c +++ b/src/mainboard/msi/ms7721/mptable.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/packardbell/ms2290/mainboard.c b/src/mainboard/packardbell/ms2290/mainboard.c index 6df8fad268..ce8d504211 100644 --- a/src/mainboard/packardbell/ms2290/mainboard.c +++ b/src/mainboard/packardbell/ms2290/mainboard.c @@ -7,7 +7,6 @@ #include #include #include -#include static void mainboard_enable(struct device *dev) { diff --git a/src/mainboard/samsung/lumpy/early_init.c b/src/mainboard/samsung/lumpy/early_init.c index 23309ba498..091cbc5064 100644 --- a/src/mainboard/samsung/lumpy/early_init.c +++ b/src/mainboard/samsung/lumpy/early_init.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/samsung/stumpy/early_init.c b/src/mainboard/samsung/stumpy/early_init.c index 6636a6b744..f07948291f 100644 --- a/src/mainboard/samsung/stumpy/early_init.c +++ b/src/mainboard/samsung/stumpy/early_init.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/northbridge/amd/agesa/family14/northbridge.c b/src/northbridge/amd/agesa/family14/northbridge.c index 34fc0c08b3..7c5ecdc8f4 100644 --- a/src/northbridge/amd/agesa/family14/northbridge.c +++ b/src/northbridge/amd/agesa/family14/northbridge.c @@ -12,7 +12,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/common/block/smbus/sm.c b/src/soc/amd/common/block/smbus/sm.c index 2f37a91362..5a4edd8b2b 100644 --- a/src/soc/amd/common/block/smbus/sm.c +++ b/src/soc/amd/common/block/smbus/sm.c @@ -6,7 +6,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index 94b91cc047..dd49acd3fc 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -6,7 +6,7 @@ #include #include #include -#include +#include #include #include #include diff --git a/src/soc/intel/broadwell/smmrelocate.c b/src/soc/intel/broadwell/smmrelocate.c index 660a688df4..03ed24494b 100644 --- a/src/soc/intel/broadwell/smmrelocate.c +++ b/src/soc/intel/broadwell/smmrelocate.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/cannonlake/smmrelocate.c b/src/soc/intel/cannonlake/smmrelocate.c index dcf67bc924..3aec51b216 100644 --- a/src/soc/intel/cannonlake/smmrelocate.c +++ b/src/soc/intel/cannonlake/smmrelocate.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/icelake/smmrelocate.c b/src/soc/intel/icelake/smmrelocate.c index d9ca915bb2..f1a7033498 100644 --- a/src/soc/intel/icelake/smmrelocate.c +++ b/src/soc/intel/icelake/smmrelocate.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/jasperlake/smmrelocate.c b/src/soc/intel/jasperlake/smmrelocate.c index af16fbd3e5..664ea6cfe4 100644 --- a/src/soc/intel/jasperlake/smmrelocate.c +++ b/src/soc/intel/jasperlake/smmrelocate.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/skylake/smmrelocate.c b/src/soc/intel/skylake/smmrelocate.c index e45da91353..cb83d615fd 100644 --- a/src/soc/intel/skylake/smmrelocate.c +++ b/src/soc/intel/skylake/smmrelocate.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/tigerlake/smmrelocate.c b/src/soc/intel/tigerlake/smmrelocate.c index af16fbd3e5..664ea6cfe4 100644 --- a/src/soc/intel/tigerlake/smmrelocate.c +++ b/src/soc/intel/tigerlake/smmrelocate.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/xeon_sp/uncore.c b/src/soc/intel/xeon_sp/uncore.c index 1d46e4070f..a549acb0f6 100644 --- a/src/soc/intel/xeon_sp/uncore.c +++ b/src/soc/intel/xeon_sp/uncore.c @@ -2,7 +2,7 @@ #include #include -#include +#include #include #include #include diff --git a/src/southbridge/amd/agesa/hudson/sm.c b/src/southbridge/amd/agesa/hudson/sm.c index 9f149080ba..39e6752f6e 100644 --- a/src/southbridge/amd/agesa/hudson/sm.c +++ b/src/southbridge/amd/agesa/hudson/sm.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include "hudson.h" diff --git a/src/southbridge/amd/pi/hudson/sm.c b/src/southbridge/amd/pi/hudson/sm.c index ee30b7fa5e..268d7e4ee2 100644 --- a/src/southbridge/amd/pi/hudson/sm.c +++ b/src/southbridge/amd/pi/hudson/sm.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include "hudson.h" From 51a549584131e509605b273474f3b7cc3dd73e83 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 17 May 2020 18:34:35 +0200 Subject: [PATCH 0021/1155] src: Remove unused '#include ' Change-Id: I57e064d26b215743a1cb06bb6605fc4fe1160876 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41491 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/drivers/analogix/anx7625/anx7625.c | 1 - src/drivers/intel/ptt/ptt.c | 1 - src/soc/amd/common/block/psp/psp.c | 1 - src/soc/amd/common/block/psp/psp_smm.c | 1 - src/soc/amd/picasso/finalize.c | 1 - src/soc/amd/stoneyridge/finalize.c | 1 - src/soc/intel/skylake/cpu.c | 1 - src/soc/intel/skylake/finalize.c | 1 - src/soc/mediatek/mt8173/i2c.c | 1 - src/soc/qualcomm/sc7180/gpio.c | 1 - 10 files changed, 10 deletions(-) diff --git a/src/drivers/analogix/anx7625/anx7625.c b/src/drivers/analogix/anx7625/anx7625.c index 57f1c7745d..ee98fd4df9 100644 --- a/src/drivers/analogix/anx7625/anx7625.c +++ b/src/drivers/analogix/anx7625/anx7625.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include "anx7625.h" diff --git a/src/drivers/intel/ptt/ptt.c b/src/drivers/intel/ptt/ptt.c index 91eb42c04e..67ed0eebb7 100644 --- a/src/drivers/intel/ptt/ptt.c +++ b/src/drivers/intel/ptt/ptt.c @@ -3,7 +3,6 @@ #include #include #include -#include #include "ptt.h" diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index b1b8b0d1c8..0e03174f08 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index 4fd80fc052..024e952760 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/picasso/finalize.c b/src/soc/amd/picasso/finalize.c index 0df944685c..2df55247cf 100644 --- a/src/soc/amd/picasso/finalize.c +++ b/src/soc/amd/picasso/finalize.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/amd/stoneyridge/finalize.c b/src/soc/amd/stoneyridge/finalize.c index 0df944685c..2df55247cf 100644 --- a/src/soc/amd/stoneyridge/finalize.c +++ b/src/soc/amd/stoneyridge/finalize.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 28572e5948..845becc516 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -26,7 +26,6 @@ #include #include #include -#include #include "chip.h" diff --git a/src/soc/intel/skylake/finalize.c b/src/soc/intel/skylake/finalize.c index ba154f2bcf..b20f391f8d 100644 --- a/src/soc/intel/skylake/finalize.c +++ b/src/soc/intel/skylake/finalize.c @@ -24,7 +24,6 @@ #include #include #include -#include #include "chip.h" diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index d2acd2c9d7..0adee22338 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/qualcomm/sc7180/gpio.c b/src/soc/qualcomm/sc7180/gpio.c index 9588cc127c..51d9135ffd 100644 --- a/src/soc/qualcomm/sc7180/gpio.c +++ b/src/soc/qualcomm/sc7180/gpio.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include From 8b08c69386d280842da44df65df5f103a53d23d6 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 24 Apr 2020 17:11:25 +0200 Subject: [PATCH 0022/1155] {icelake,jasperlake,skylake,tigerlake}/bootblock.c: Clean up includes Drop unused includes and add missing . Change-Id: I06c8b2bf65283c3c1fcd25fdaae298b82fc0e09c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40689 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Wonkyu Kim --- src/soc/intel/icelake/bootblock/bootblock.c | 3 --- src/soc/intel/jasperlake/bootblock/bootblock.c | 3 --- src/soc/intel/skylake/bootblock/bootblock.c | 2 +- src/soc/intel/tigerlake/bootblock/bootblock.c | 3 --- 4 files changed, 1 insertion(+), 10 deletions(-) diff --git a/src/soc/intel/icelake/bootblock/bootblock.c b/src/soc/intel/icelake/bootblock/bootblock.c index ce71cdde89..54ad85a82e 100644 --- a/src/soc/intel/icelake/bootblock/bootblock.c +++ b/src/soc/intel/icelake/bootblock/bootblock.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include -#include -#include asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { diff --git a/src/soc/intel/jasperlake/bootblock/bootblock.c b/src/soc/intel/jasperlake/bootblock/bootblock.c index ce71cdde89..54ad85a82e 100644 --- a/src/soc/intel/jasperlake/bootblock/bootblock.c +++ b/src/soc/intel/jasperlake/bootblock/bootblock.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include -#include -#include asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { diff --git a/src/soc/intel/skylake/bootblock/bootblock.c b/src/soc/intel/skylake/bootblock/bootblock.c index 461e28cbc5..6380db2e1f 100644 --- a/src/soc/intel/skylake/bootblock/bootblock.c +++ b/src/soc/intel/skylake/bootblock/bootblock.c @@ -1,7 +1,7 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include +#include #include #include #include diff --git a/src/soc/intel/tigerlake/bootblock/bootblock.c b/src/soc/intel/tigerlake/bootblock/bootblock.c index ce71cdde89..54ad85a82e 100644 --- a/src/soc/intel/tigerlake/bootblock/bootblock.c +++ b/src/soc/intel/tigerlake/bootblock/bootblock.c @@ -1,12 +1,9 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include -#include -#include asmlinkage void bootblock_c_entry(uint64_t base_timestamp) { From 98e360e835a5c8b53f1ead574cd5bef38945a1bb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Fri, 24 Apr 2020 17:31:53 +0200 Subject: [PATCH 0023/1155] soc/intel/*/bootblock/cpu.c: Drop unused includes Change-Id: Ide01a922d7d8e500f9a0b507544010706661d7de Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40690 Reviewed-by: Angel Pons Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/bootblock/cpu.c | 1 - src/soc/intel/skylake/bootblock/cpu.c | 1 - 2 files changed, 2 deletions(-) diff --git a/src/soc/intel/cannonlake/bootblock/cpu.c b/src/soc/intel/cannonlake/bootblock/cpu.c index a64eb26027..5a56d29b43 100644 --- a/src/soc/intel/cannonlake/bootblock/cpu.c +++ b/src/soc/intel/cannonlake/bootblock/cpu.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/soc/intel/skylake/bootblock/cpu.c b/src/soc/intel/skylake/bootblock/cpu.c index 08fbdb9774..bf487c3623 100644 --- a/src/soc/intel/skylake/bootblock/cpu.c +++ b/src/soc/intel/skylake/bootblock/cpu.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include From f2b21f6d421185da188dd5274d6feb8bafe6c6a3 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Mon, 18 May 2020 17:12:29 +0200 Subject: [PATCH 0024/1155] soc/intel/xeon_sp/skx/soc_util.c: Remove unused Change-Id: I6dd004b417c27ff0b9f7e55557a9670f927d425c Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41514 Tested-by: build bot (Jenkins) Reviewed-by: Jonathan Zhang Reviewed-by: Angel Pons --- src/soc/intel/xeon_sp/skx/soc_util.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index aa965b6cce..dc97d5ec34 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include From a685fcb7cede7b8e0ff20af255e3ad39d0bee1b5 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 23 May 2020 08:47:56 +0200 Subject: [PATCH 0025/1155] src: Remove unused 'include ' Change-Id: If8048586e3693a8e6f63d9dc2800b073bab78628 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41669 Reviewed-by: Angel Pons Reviewed-by: David Guckian Tested-by: build bot (Jenkins) --- src/mainboard/google/beltino/acpi_tables.c | 1 - src/mainboard/google/jecht/acpi_tables.c | 1 - src/mainboard/google/parrot/acpi_tables.c | 1 - src/mainboard/google/rambi/acpi_tables.c | 1 - src/mainboard/google/slippy/acpi_tables.c | 1 - src/mainboard/google/stout/acpi_tables.c | 1 - src/mainboard/google/stout/onboard.h | 2 -- src/mainboard/intel/baskingridge/acpi_tables.c | 1 - src/mainboard/intel/emeraldlake2/acpi_tables.c | 1 - src/mainboard/intel/harcuvar/acpi_tables.c | 1 - src/mainboard/intel/strago/acpi_tables.c | 1 - src/mainboard/intel/wtm2/acpi_tables.c | 1 - src/mainboard/samsung/lumpy/acpi_tables.c | 1 - src/mainboard/samsung/stumpy/acpi_tables.c | 1 - src/mainboard/scaleway/tagada/acpi_tables.c | 1 - src/southbridge/intel/i82371eb/acpi_tables.c | 1 - 16 files changed, 17 deletions(-) diff --git a/src/mainboard/google/beltino/acpi_tables.c b/src/mainboard/google/beltino/acpi_tables.c index b6a5606a8f..d2f7f45ff1 100644 --- a/src/mainboard/google/beltino/acpi_tables.c +++ b/src/mainboard/google/beltino/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/jecht/acpi_tables.c b/src/mainboard/google/jecht/acpi_tables.c index 50bd1e04dd..3e8cc2016a 100644 --- a/src/mainboard/google/jecht/acpi_tables.c +++ b/src/mainboard/google/jecht/acpi_tables.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/parrot/acpi_tables.c b/src/mainboard/google/parrot/acpi_tables.c index ce03c70324..62722ec486 100644 --- a/src/mainboard/google/parrot/acpi_tables.c +++ b/src/mainboard/google/parrot/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/rambi/acpi_tables.c b/src/mainboard/google/rambi/acpi_tables.c index 507da97979..c4c17888d8 100644 --- a/src/mainboard/google/rambi/acpi_tables.c +++ b/src/mainboard/google/rambi/acpi_tables.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/google/slippy/acpi_tables.c b/src/mainboard/google/slippy/acpi_tables.c index d09193136c..ba55647e03 100644 --- a/src/mainboard/google/slippy/acpi_tables.c +++ b/src/mainboard/google/slippy/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/stout/acpi_tables.c b/src/mainboard/google/stout/acpi_tables.c index 76342d409d..08bd4cdd1c 100644 --- a/src/mainboard/google/stout/acpi_tables.c +++ b/src/mainboard/google/stout/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/stout/onboard.h b/src/mainboard/google/stout/onboard.h index 6024ba85e5..a31dffd4cd 100644 --- a/src/mainboard/google/stout/onboard.h +++ b/src/mainboard/google/stout/onboard.h @@ -3,8 +3,6 @@ #ifndef STOUT_ONBOARD_H #define STOUT_ONBOARD_H -#include - #define STOUT_NIC_VENDOR_ID 0x10EC #define STOUT_NIC_DEVICE_ID 0x8168 diff --git a/src/mainboard/intel/baskingridge/acpi_tables.c b/src/mainboard/intel/baskingridge/acpi_tables.c index ba6d9c06e1..24edfea49f 100644 --- a/src/mainboard/intel/baskingridge/acpi_tables.c +++ b/src/mainboard/intel/baskingridge/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/intel/emeraldlake2/acpi_tables.c b/src/mainboard/intel/emeraldlake2/acpi_tables.c index 013487f48b..36d0d66fd8 100644 --- a/src/mainboard/intel/emeraldlake2/acpi_tables.c +++ b/src/mainboard/intel/emeraldlake2/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/intel/harcuvar/acpi_tables.c b/src/mainboard/intel/harcuvar/acpi_tables.c index 046d3acdcf..1351e62876 100644 --- a/src/mainboard/intel/harcuvar/acpi_tables.c +++ b/src/mainboard/intel/harcuvar/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/mainboard/intel/strago/acpi_tables.c b/src/mainboard/intel/strago/acpi_tables.c index a3b9dd07fb..e97d9c14e7 100644 --- a/src/mainboard/intel/strago/acpi_tables.c +++ b/src/mainboard/intel/strago/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/intel/wtm2/acpi_tables.c b/src/mainboard/intel/wtm2/acpi_tables.c index 960dbde3c0..87cb965313 100644 --- a/src/mainboard/intel/wtm2/acpi_tables.c +++ b/src/mainboard/intel/wtm2/acpi_tables.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/samsung/lumpy/acpi_tables.c b/src/mainboard/samsung/lumpy/acpi_tables.c index 592ed50629..aafbdb6638 100644 --- a/src/mainboard/samsung/lumpy/acpi_tables.c +++ b/src/mainboard/samsung/lumpy/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #if CONFIG(CHROMEOS) diff --git a/src/mainboard/samsung/stumpy/acpi_tables.c b/src/mainboard/samsung/stumpy/acpi_tables.c index de2d51dfe0..b66e4ddd66 100644 --- a/src/mainboard/samsung/stumpy/acpi_tables.c +++ b/src/mainboard/samsung/stumpy/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/scaleway/tagada/acpi_tables.c b/src/mainboard/scaleway/tagada/acpi_tables.c index 046d3acdcf..1351e62876 100644 --- a/src/mainboard/scaleway/tagada/acpi_tables.c +++ b/src/mainboard/scaleway/tagada/acpi_tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include diff --git a/src/southbridge/intel/i82371eb/acpi_tables.c b/src/southbridge/intel/i82371eb/acpi_tables.c index ab28e760b5..7507cd5d5d 100644 --- a/src/southbridge/intel/i82371eb/acpi_tables.c +++ b/src/southbridge/intel/i82371eb/acpi_tables.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include "i82371eb.h" From fcf7d992bf0e8dfb887b7c1db29852898deb7684 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 23 May 2020 09:01:17 +0200 Subject: [PATCH 0026/1155] src: Remove unused 'include ' Change-Id: I658023f7c3535a2cddd8e11ca8bebe20ae53ffb0 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41670 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/ec/google/chromeec/ec.c | 1 - src/northbridge/intel/sandybridge/raminit.c | 1 - src/northbridge/intel/sandybridge/raminit_mrc.c | 1 - src/soc/cavium/cn81xx/soc.c | 1 - src/soc/intel/apollolake/romstage.c | 1 - src/soc/intel/broadwell/romstage/romstage.c | 1 - src/soc/intel/skylake/chip.c | 1 - 7 files changed, 7 deletions(-) diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 034e9313c9..233f61bafb 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index a2b26ae1bf..72c284fb30 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 43858f53bb..1ec54b328e 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/cavium/cn81xx/soc.c b/src/soc/cavium/cn81xx/soc.c index 1077824d39..3545d55bd9 100644 --- a/src/soc/cavium/cn81xx/soc.c +++ b/src/soc/cavium/cn81xx/soc.c @@ -4,7 +4,6 @@ * Derived from Cavium's BSD-3 Clause OCTEONTX-SDK-6.2.0. */ -#include #include #include #include diff --git a/src/soc/intel/apollolake/romstage.c b/src/soc/intel/apollolake/romstage.c index 2abeb3a7f6..09537a1af3 100644 --- a/src/soc/intel/apollolake/romstage.c +++ b/src/soc/intel/apollolake/romstage.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/intel/broadwell/romstage/romstage.c b/src/soc/intel/broadwell/romstage/romstage.c index 54d6134b16..3b7aa40049 100644 --- a/src/soc/intel/broadwell/romstage/romstage.c +++ b/src/soc/intel/broadwell/romstage/romstage.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index b14bb72a7b..a1ef06e6e0 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include From ebddada48db221838e82fea5f2f14d9faeb53dfe Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 23 May 2020 09:16:34 +0200 Subject: [PATCH 0027/1155] src: Remove unused 'include ' Change-Id: I54eda3d51ecda77309841e598f06eb9cea3babc1 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41671 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/arch/x86/acpi_bert_storage.c | 1 - src/arch/x86/tables.c | 1 - src/drivers/intel/fsp1_1/hob.c | 1 - src/ec/google/chromeec/ec.c | 1 - src/lib/cbmem_common.c | 1 - src/lib/ext_stage_cache.c | 1 - src/lib/imd_cbmem.c | 1 - src/mainboard/google/hatch/variants/jinlon/mainboard.c | 1 - src/mainboard/intel/strago/mainboard.c | 1 - src/mainboard/protectli/vault_kbl/ramstage.c | 1 - src/mainboard/supermicro/x11-lga1151-series/ramstage.c | 1 - src/soc/amd/common/block/psp/psp_gen1.c | 1 - src/soc/amd/common/block/psp/psp_gen2.c | 1 - src/soc/amd/common/block/psp/psp_smm.c | 1 - src/soc/amd/picasso/chip.c | 1 - src/soc/intel/apollolake/elog.c | 1 - src/soc/intel/braswell/ramstage.c | 1 - src/soc/intel/common/block/smm/smm.c | 1 - src/soc/intel/common/vbt.c | 1 - src/soc/intel/skylake/chip.c | 1 - src/soc/intel/skylake/cpu.c | 1 - src/soc/intel/tigerlake/pmc.c | 1 - src/southbridge/intel/lynxpoint/smi.c | 1 - 23 files changed, 23 deletions(-) diff --git a/src/arch/x86/acpi_bert_storage.c b/src/arch/x86/acpi_bert_storage.c index cde95f12e0..de56291ac4 100644 --- a/src/arch/x86/acpi_bert_storage.c +++ b/src/arch/x86/acpi_bert_storage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/arch/x86/tables.c b/src/arch/x86/tables.c index 3b1b76d14b..492674c5a9 100644 --- a/src/arch/x86/tables.c +++ b/src/arch/x86/tables.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/drivers/intel/fsp1_1/hob.c b/src/drivers/intel/fsp1_1/hob.c index d13939cb11..9a09cfd81a 100644 --- a/src/drivers/intel/fsp1_1/hob.c +++ b/src/drivers/intel/fsp1_1/hob.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 233f61bafb..a97dfb355e 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include diff --git a/src/lib/cbmem_common.c b/src/lib/cbmem_common.c index c24479deb4..bc3bfc911d 100644 --- a/src/lib/cbmem_common.c +++ b/src/lib/cbmem_common.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include void cbmem_run_init_hooks(int is_recovery) diff --git a/src/lib/ext_stage_cache.c b/src/lib/ext_stage_cache.c index afc061883f..2fb1e9ee90 100644 --- a/src/lib/ext_stage_cache.c +++ b/src/lib/ext_stage_cache.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/lib/imd_cbmem.c b/src/lib/imd_cbmem.c index d06a9e9416..cb66c3b219 100644 --- a/src/lib/imd_cbmem.c +++ b/src/lib/imd_cbmem.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c index 6e0315b8cc..6fde60278a 100644 --- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c +++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c @@ -4,7 +4,6 @@ * SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include #include #include diff --git a/src/mainboard/intel/strago/mainboard.c b/src/mainboard/intel/strago/mainboard.c index 287623e549..dd40848948 100644 --- a/src/mainboard/intel/strago/mainboard.c +++ b/src/mainboard/intel/strago/mainboard.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/protectli/vault_kbl/ramstage.c b/src/mainboard/protectli/vault_kbl/ramstage.c index 266094a464..962702fb5a 100644 --- a/src/mainboard/protectli/vault_kbl/ramstage.c +++ b/src/mainboard/protectli/vault_kbl/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include "gpio.h" diff --git a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c index 8c9daf702b..5de606d807 100644 --- a/src/mainboard/supermicro/x11-lga1151-series/ramstage.c +++ b/src/mainboard/supermicro/x11-lga1151-series/ramstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include diff --git a/src/soc/amd/common/block/psp/psp_gen1.c b/src/soc/amd/common/block/psp/psp_gen1.c index 703af9d5b9..5096dd3adc 100644 --- a/src/soc/amd/common/block/psp/psp_gen1.c +++ b/src/soc/amd/common/block/psp/psp_gen1.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index cf9b532f88..59e62551c1 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include "psp_def.h" diff --git a/src/soc/amd/common/block/psp/psp_smm.c b/src/soc/amd/common/block/psp/psp_smm.c index 024e952760..b103b3e629 100644 --- a/src/soc/amd/common/block/psp/psp_smm.c +++ b/src/soc/amd/common/block/psp/psp_smm.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index f5936646d2..9c26f35121 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/apollolake/elog.c b/src/soc/intel/apollolake/elog.c index 30d7b20306..408017f940 100644 --- a/src/soc/intel/apollolake/elog.c +++ b/src/soc/intel/apollolake/elog.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/braswell/ramstage.c b/src/soc/intel/braswell/ramstage.c index 101ab92054..893a6b6ea2 100644 --- a/src/soc/intel/braswell/ramstage.c +++ b/src/soc/intel/braswell/ramstage.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/common/block/smm/smm.c b/src/soc/intel/common/block/smm/smm.c index 2696777ad7..93fcee2602 100644 --- a/src/soc/intel/common/block/smm/smm.c +++ b/src/soc/intel/common/block/smm/smm.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/common/vbt.c b/src/soc/intel/common/vbt.c index 3d0ba1a406..690fb5fc3a 100644 --- a/src/soc/intel/common/vbt.c +++ b/src/soc/intel/common/vbt.c @@ -2,7 +2,6 @@ #include #include -#include #include "vbt.h" #include diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index a1ef06e6e0..6ef01d8c0c 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 845becc516..bfa59fed80 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/soc/intel/tigerlake/pmc.c b/src/soc/intel/tigerlake/pmc.c index 84a18e3865..4d898700bd 100644 --- a/src/soc/intel/tigerlake/pmc.c +++ b/src/soc/intel/tigerlake/pmc.c @@ -7,7 +7,6 @@ */ #include -#include #include #include #include diff --git a/src/southbridge/intel/lynxpoint/smi.c b/src/southbridge/intel/lynxpoint/smi.c index 9d575549e8..cddada1d18 100644 --- a/src/southbridge/intel/lynxpoint/smi.c +++ b/src/southbridge/intel/lynxpoint/smi.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include From 9ffef56c45cc51e51e44ec148738244639edf90e Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 23 May 2020 09:47:13 +0200 Subject: [PATCH 0028/1155] soc/amd/picasso: Remove unused 'include ' Change-Id: I07100361705ce421131b8a5d772cb5ba2d8722ff Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41672 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/chip.c | 1 - src/soc/amd/picasso/romstage.c | 1 - 2 files changed, 2 deletions(-) diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 9c26f35121..4ea962f715 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -5,7 +5,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/picasso/romstage.c b/src/soc/amd/picasso/romstage.c index a2ca055525..0bbceec0d1 100644 --- a/src/soc/amd/picasso/romstage.c +++ b/src/soc/amd/picasso/romstage.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include From a3b02e2818bedf39f4f84388f6d52dcf3ee299cc Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 23 May 2020 10:15:39 +0200 Subject: [PATCH 0029/1155] src: Remove unused 'include ' Change-Id: Ica355292eeda9c386b49db97f021566d52943d40 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41673 Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/security/vboot/common.c | 1 - src/soc/mediatek/mt8173/i2c.c | 1 - src/soc/nvidia/tegra124/spi.c | 1 - src/soc/nvidia/tegra210/arm_tf.c | 1 - 4 files changed, 4 deletions(-) diff --git a/src/security/vboot/common.c b/src/security/vboot/common.c index 97016907a7..db51fa13b8 100644 --- a/src/security/vboot/common.c +++ b/src/security/vboot/common.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index 0adee22338..af2e02958b 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 75cd9f772a..6a2572167e 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -13,7 +13,6 @@ #include #include #include -#include #include #include diff --git a/src/soc/nvidia/tegra210/arm_tf.c b/src/soc/nvidia/tegra210/arm_tf.c index e12b2012b9..684a3c47d8 100644 --- a/src/soc/nvidia/tegra210/arm_tf.c +++ b/src/soc/nvidia/tegra210/arm_tf.c @@ -5,7 +5,6 @@ #include #include #include -#include #include typedef struct bl31_plat_params { From 48378e1f8d132a3d3bdbb7b1eac5c769c273e6e1 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sat, 23 May 2020 11:18:46 +0200 Subject: [PATCH 0030/1155] src: Remove duplicated includes Change-Id: If8c7e26ebd954b19bfb8766b26570c6865ad255e Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41676 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/51nb/x210/romstage.c | 1 - src/mainboard/google/fizz/mainboard.c | 1 - src/soc/amd/common/block/acpi/acpi.c | 1 - src/soc/amd/common/block/lpc/lpc_util.c | 1 - src/soc/intel/braswell/northcluster.c | 1 - src/soc/mediatek/common/dsi.c | 1 - src/soc/mediatek/mt8173/i2c.c | 2 -- src/southbridge/amd/agesa/hudson/early_setup.c | 1 - src/southbridge/amd/pi/hudson/early_setup.c | 1 - 9 files changed, 10 deletions(-) diff --git a/src/mainboard/51nb/x210/romstage.c b/src/mainboard/51nb/x210/romstage.c index caaa52d4a2..60f008c20a 100644 --- a/src/mainboard/51nb/x210/romstage.c +++ b/src/mainboard/51nb/x210/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include diff --git a/src/mainboard/google/fizz/mainboard.c b/src/mainboard/google/fizz/mainboard.c index c86be82c68..7b8905888a 100644 --- a/src/mainboard/google/fizz/mainboard.c +++ b/src/mainboard/google/fizz/mainboard.c @@ -10,7 +10,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/amd/common/block/acpi/acpi.c b/src/soc/amd/common/block/acpi/acpi.c index 964aef1882..2be9b9e25e 100644 --- a/src/soc/amd/common/block/acpi/acpi.c +++ b/src/soc/amd/common/block/acpi/acpi.c @@ -10,7 +10,6 @@ #include #include #include -#include void poweroff(void) { diff --git a/src/soc/amd/common/block/lpc/lpc_util.c b/src/soc/amd/common/block/lpc/lpc_util.c index d2a65c8c96..eb129dc00d 100644 --- a/src/soc/amd/common/block/lpc/lpc_util.c +++ b/src/soc/amd/common/block/lpc/lpc_util.c @@ -12,7 +12,6 @@ /* The LPC-ISA bridge is always at D14F3 */ #if !defined(__SIMPLE_DEVICE__) -#include #define _LPCB_DEV pcidev_on_root(0x14, 0x3) #else #define _LPCB_DEV PCI_DEV(0, 0x14, 0x3) diff --git a/src/soc/intel/braswell/northcluster.c b/src/soc/intel/braswell/northcluster.c index dd49acd3fc..1f310d490e 100644 --- a/src/soc/intel/braswell/northcluster.c +++ b/src/soc/intel/braswell/northcluster.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/mediatek/common/dsi.c b/src/soc/mediatek/common/dsi.c index 73dacef33b..2505bbc075 100644 --- a/src/soc/mediatek/common/dsi.c +++ b/src/soc/mediatek/common/dsi.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8173/i2c.c b/src/soc/mediatek/mt8173/i2c.c index af2e02958b..f80fb97121 100644 --- a/src/soc/mediatek/mt8173/i2c.c +++ b/src/soc/mediatek/mt8173/i2c.c @@ -7,9 +7,7 @@ #include #include #include -#include #include -#include #define I2C_CLK_HZ (AXI_HZ / 16) diff --git a/src/southbridge/amd/agesa/hudson/early_setup.c b/src/southbridge/amd/agesa/hudson/early_setup.c index 63d2b81c22..48649453c1 100644 --- a/src/southbridge/amd/agesa/hudson/early_setup.c +++ b/src/southbridge/amd/agesa/hudson/early_setup.c @@ -7,7 +7,6 @@ #include #include #include -#include #include "hudson.h" diff --git a/src/southbridge/amd/pi/hudson/early_setup.c b/src/southbridge/amd/pi/hudson/early_setup.c index 09a2750fcf..8bca42b6ee 100644 --- a/src/southbridge/amd/pi/hudson/early_setup.c +++ b/src/southbridge/amd/pi/hudson/early_setup.c @@ -9,7 +9,6 @@ #include #include #include -#include #include "hudson.h" #include "pci_devs.h" From 0c154af2175fcb05bffa4ccad11c40366f5417e7 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Thu, 28 May 2020 08:54:42 +0200 Subject: [PATCH 0031/1155] src: Remove redundant includes is supposed to provide , , and . So remove those includes each time when is included. Change-Id: I886f02255099f3005852a2e6095b21ca86a940ed Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41817 Tested-by: build bot (Jenkins) Reviewed-by: Julius Werner Reviewed-by: Paul Menzel --- src/arch/arm/armv7/exception.c | 1 - src/arch/arm64/armv8/exception.c | 1 - src/device/pci_device.c | 1 - src/drivers/i2c/tpm/tpm.c | 1 - src/drivers/intel/fsp2_0/include/fsp/info_header.h | 1 - src/drivers/tpm/tpm.c | 1 - src/drivers/uart/pl011.h | 1 - src/ec/google/wilco/commands.h | 1 - src/ec/google/wilco/mailbox.c | 1 - src/include/device/dram/ddr3.h | 1 - src/include/device/dram/ddr4.h | 1 - src/include/lib.h | 2 +- src/mainboard/supermicro/x10slm-f/mainboard.c | 1 - src/northbridge/intel/x4x/dq_dqs.c | 1 - src/security/tpm/tss.h | 1 - src/security/tpm/tss/tcg-2.0/tss_structures.h | 1 - src/soc/amd/common/block/include/amdblocks/acpimmio.h | 1 - src/soc/amd/common/block/include/amdblocks/lpc.h | 1 - src/soc/amd/common/block/lpc/espi_util.c | 2 -- src/soc/cavium/cn81xx/include/soc/soc.h | 1 - src/soc/cavium/cn81xx/include/soc/timer.h | 1 - src/soc/cavium/cn81xx/include/soc/uart.h | 1 - src/soc/intel/common/block/include/intelblocks/cse.h | 1 - src/soc/mediatek/mt8173/flash_controller.c | 1 - src/soc/mediatek/mt8173/include/soc/dramc_register.h | 1 - src/soc/mediatek/mt8173/include/soc/emi.h | 1 - src/soc/mediatek/mt8183/include/soc/emi.h | 1 - src/soc/mediatek/mt8183/include/soc/spm.h | 1 - src/soc/nvidia/tegra/dc.h | 2 +- src/soc/nvidia/tegra124/spi.c | 1 - src/soc/nvidia/tegra210/include/soc/dma.h | 1 - src/soc/nvidia/tegra210/spi.c | 1 - 32 files changed, 2 insertions(+), 33 deletions(-) diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c index 39ef16da22..799ae027c9 100644 --- a/src/arch/arm/armv7/exception.c +++ b/src/arch/arm/armv7/exception.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -#include #include #include #include diff --git a/src/arch/arm64/armv8/exception.c b/src/arch/arm64/armv8/exception.c index db399fe699..88e68e759e 100644 --- a/src/arch/arm64/armv8/exception.c +++ b/src/arch/arm64/armv8/exception.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: BSD-3-Clause */ -#include #include #include #include diff --git a/src/device/pci_device.c b/src/device/pci_device.c index e6c6ff31a4..f83520e079 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -11,7 +11,6 @@ #include #include #include -#include #include #include #include diff --git a/src/drivers/i2c/tpm/tpm.c b/src/drivers/i2c/tpm/tpm.c index 41d4577b48..78ac224eda 100644 --- a/src/drivers/i2c/tpm/tpm.c +++ b/src/drivers/i2c/tpm/tpm.c @@ -17,7 +17,6 @@ #include -#include #include #include #include diff --git a/src/drivers/intel/fsp2_0/include/fsp/info_header.h b/src/drivers/intel/fsp2_0/include/fsp/info_header.h index f6f66cea37..7755d2a2f9 100644 --- a/src/drivers/intel/fsp2_0/include/fsp/info_header.h +++ b/src/drivers/intel/fsp2_0/include/fsp/info_header.h @@ -3,7 +3,6 @@ #ifndef _FSP2_0_INFO_HEADER_H_ #define _FSP2_0_INFO_HEADER_H_ -#include #include #define FSP_HDR_OFFSET 0x94 diff --git a/src/drivers/tpm/tpm.c b/src/drivers/tpm/tpm.c index ad4a54c770..d3485bbec9 100644 --- a/src/drivers/tpm/tpm.c +++ b/src/drivers/tpm/tpm.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include diff --git a/src/drivers/uart/pl011.h b/src/drivers/uart/pl011.h index 7b573a4eda..d4d54c45f4 100644 --- a/src/drivers/uart/pl011.h +++ b/src/drivers/uart/pl011.h @@ -7,7 +7,6 @@ #ifndef __DRIVERS_UART_PL011_H #define __DRIVERS_UART_PL011_H -#include #include /* PL011 r1p5 registers */ diff --git a/src/ec/google/wilco/commands.h b/src/ec/google/wilco/commands.h index 912e88a1ec..a2163459e1 100644 --- a/src/ec/google/wilco/commands.h +++ b/src/ec/google/wilco/commands.h @@ -3,7 +3,6 @@ #ifndef EC_GOOGLE_WILCO_COMMANDS_H #define EC_GOOGLE_WILCO_COMMANDS_H -#include #include enum { diff --git a/src/ec/google/wilco/mailbox.c b/src/ec/google/wilco/mailbox.c index c592d81f76..f7aac863de 100644 --- a/src/ec/google/wilco/mailbox.c +++ b/src/ec/google/wilco/mailbox.c @@ -4,7 +4,6 @@ #include #include #include -#include #include #include #include diff --git a/src/include/device/dram/ddr3.h b/src/include/device/dram/ddr3.h index 08b7b7c72c..a209e48b8b 100644 --- a/src/include/device/dram/ddr3.h +++ b/src/include/device/dram/ddr3.h @@ -15,7 +15,6 @@ * \brief Utilities for decoding DDR3 SPDs */ -#include #include #include #include diff --git a/src/include/device/dram/ddr4.h b/src/include/device/dram/ddr4.h index 51fd7bff6d..f258fa9f09 100644 --- a/src/include/device/dram/ddr4.h +++ b/src/include/device/dram/ddr4.h @@ -14,7 +14,6 @@ * \brief Utilities for decoding DDR4 SPDs */ -#include #include #include #include diff --git a/src/include/lib.h b/src/include/lib.h index d7b6b14b91..0d6fdb14be 100644 --- a/src/include/lib.h +++ b/src/include/lib.h @@ -4,7 +4,7 @@ #ifndef __LIB_H__ #define __LIB_H__ -#include + #include /* Defined in src/lib/lzma.c. Returns decompressed size or 0 on error. */ diff --git a/src/mainboard/supermicro/x10slm-f/mainboard.c b/src/mainboard/supermicro/x10slm-f/mainboard.c index 7d840f5c32..2f206060b7 100644 --- a/src/mainboard/supermicro/x10slm-f/mainboard.c +++ b/src/mainboard/supermicro/x10slm-f/mainboard.c @@ -3,7 +3,6 @@ #include #include #include -#include #include /* diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 7df259172a..dda41744ae 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include "x4x.h" diff --git a/src/security/tpm/tss.h b/src/security/tpm/tss.h index f644e3e7e7..4a8206d056 100644 --- a/src/security/tpm/tss.h +++ b/src/security/tpm/tss.h @@ -9,7 +9,6 @@ #ifndef TSS_H_ #define TSS_H_ -#include #include #include diff --git a/src/security/tpm/tss/tcg-2.0/tss_structures.h b/src/security/tpm/tss/tcg-2.0/tss_structures.h index f8c6012990..1c7aa4b48f 100644 --- a/src/security/tpm/tss/tcg-2.0/tss_structures.h +++ b/src/security/tpm/tss/tcg-2.0/tss_structures.h @@ -7,7 +7,6 @@ * This file includes a subset of definitions of TPM protocol version 2.x * constants and structures needed for functions used in coreboot. */ -#include #include #include "../common/tss_common.h" diff --git a/src/soc/amd/common/block/include/amdblocks/acpimmio.h b/src/soc/amd/common/block/include/amdblocks/acpimmio.h index 0d41782003..84a9360d1b 100644 --- a/src/soc/amd/common/block/include/amdblocks/acpimmio.h +++ b/src/soc/amd/common/block/include/amdblocks/acpimmio.h @@ -4,7 +4,6 @@ #define __AMDBLOCKS_ACPIMMIO_H__ #include -#include #include #include diff --git a/src/soc/amd/common/block/include/amdblocks/lpc.h b/src/soc/amd/common/block/include/amdblocks/lpc.h index 11acc78228..7412e7bb1b 100644 --- a/src/soc/amd/common/block/include/amdblocks/lpc.h +++ b/src/soc/amd/common/block/include/amdblocks/lpc.h @@ -4,7 +4,6 @@ #define __AMDBLOCKS_LPC_H__ #include -#include /* PCI registers for D14F3 */ #define LPC_PCI_CONTROL 0x40 diff --git a/src/soc/amd/common/block/lpc/espi_util.c b/src/soc/amd/common/block/lpc/espi_util.c index 5ca0d2831a..3750a8b7f9 100644 --- a/src/soc/amd/common/block/lpc/espi_util.c +++ b/src/soc/amd/common/block/lpc/espi_util.c @@ -7,8 +7,6 @@ #include #include #include -#include -#include #include #include diff --git a/src/soc/cavium/cn81xx/include/soc/soc.h b/src/soc/cavium/cn81xx/include/soc/soc.h index 39395171f7..78343fd705 100644 --- a/src/soc/cavium/cn81xx/include/soc/soc.h +++ b/src/soc/cavium/cn81xx/include/soc/soc.h @@ -3,7 +3,6 @@ #ifndef __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H #define __SOC_CAVIUM_CN81XX_INCLUDE_SOC_SOC_H -#include #include /* MIO BOOT Registers */ diff --git a/src/soc/cavium/cn81xx/include/soc/timer.h b/src/soc/cavium/cn81xx/include/soc/timer.h index 99dbb6ad5a..d7225692f9 100644 --- a/src/soc/cavium/cn81xx/include/soc/timer.h +++ b/src/soc/cavium/cn81xx/include/soc/timer.h @@ -3,7 +3,6 @@ #ifndef __SOC_CAVIUM_CN81XX_TIMER_H__ #define __SOC_CAVIUM_CN81XX_TIMER_H__ -#include #include /* Watchdog functions */ diff --git a/src/soc/cavium/cn81xx/include/soc/uart.h b/src/soc/cavium/cn81xx/include/soc/uart.h index db1a51eb90..afafd0ec1b 100644 --- a/src/soc/cavium/cn81xx/include/soc/uart.h +++ b/src/soc/cavium/cn81xx/include/soc/uart.h @@ -3,7 +3,6 @@ #ifndef __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H #define __SOC_CAVIUM_COMMON_INCLUDE_SOC_UART_H -#include #include int uart_is_enabled(const size_t bus); diff --git a/src/soc/intel/common/block/include/intelblocks/cse.h b/src/soc/intel/common/block/include/intelblocks/cse.h index 9f85730e3f..a1dc3d9d56 100644 --- a/src/soc/intel/common/block/include/intelblocks/cse.h +++ b/src/soc/intel/common/block/include/intelblocks/cse.h @@ -3,7 +3,6 @@ #ifndef SOC_INTEL_COMMON_CSE_H #define SOC_INTEL_COMMON_CSE_H -#include #include /* MKHI Command groups */ diff --git a/src/soc/mediatek/mt8173/flash_controller.c b/src/soc/mediatek/mt8173/flash_controller.c index c1f2dae7f3..64eff2e309 100644 --- a/src/soc/mediatek/mt8173/flash_controller.c +++ b/src/soc/mediatek/mt8173/flash_controller.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/mediatek/mt8173/include/soc/dramc_register.h b/src/soc/mediatek/mt8173/include/soc/dramc_register.h index 5841b24be7..cabc1dcd19 100644 --- a/src/soc/mediatek/mt8173/include/soc/dramc_register.h +++ b/src/soc/mediatek/mt8173/include/soc/dramc_register.h @@ -3,7 +3,6 @@ #ifndef _DRAMC_REGISTER_H_ #define _DRAMC_REGISTER_H_ -#include #include #define DRIVING_DS2_0 7 /* DS[2:0] 7->6 */ diff --git a/src/soc/mediatek/mt8173/include/soc/emi.h b/src/soc/mediatek/mt8173/include/soc/emi.h index 8f12ee3ad9..1cc2577a94 100644 --- a/src/soc/mediatek/mt8173/include/soc/emi.h +++ b/src/soc/mediatek/mt8173/include/soc/emi.h @@ -4,7 +4,6 @@ #define SOC_MEDIATEK_MT8173_EMI_H #include -#include #include /* DDR type */ diff --git a/src/soc/mediatek/mt8183/include/soc/emi.h b/src/soc/mediatek/mt8183/include/soc/emi.h index e775973b4c..b2d78b965f 100644 --- a/src/soc/mediatek/mt8183/include/soc/emi.h +++ b/src/soc/mediatek/mt8183/include/soc/emi.h @@ -3,7 +3,6 @@ #ifndef SOC_MEDIATEK_MT8183_EMI_H #define SOC_MEDIATEK_MT8183_EMI_H -#include #include #include diff --git a/src/soc/mediatek/mt8183/include/soc/spm.h b/src/soc/mediatek/mt8183/include/soc/spm.h index e09d451ccf..fa6d6d00ce 100644 --- a/src/soc/mediatek/mt8183/include/soc/spm.h +++ b/src/soc/mediatek/mt8183/include/soc/spm.h @@ -4,7 +4,6 @@ #define SOC_MEDIATEK_MT8183_SPM_H #include -#include #include /* SPM READ/WRITE CFG */ diff --git a/src/soc/nvidia/tegra/dc.h b/src/soc/nvidia/tegra/dc.h index f0f5b11172..27bbee80e6 100644 --- a/src/soc/nvidia/tegra/dc.h +++ b/src/soc/nvidia/tegra/dc.h @@ -2,8 +2,8 @@ #ifndef __SOC_NVIDIA_TEGRA_DC_H #define __SOC_NVIDIA_TEGRA_DC_H + #include -#include #include /* Register definitions for the Tegra display controller */ diff --git a/src/soc/nvidia/tegra124/spi.c b/src/soc/nvidia/tegra124/spi.c index 6a2572167e..adf0248849 100644 --- a/src/soc/nvidia/tegra124/spi.c +++ b/src/soc/nvidia/tegra124/spi.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include diff --git a/src/soc/nvidia/tegra210/include/soc/dma.h b/src/soc/nvidia/tegra210/include/soc/dma.h index 3add2baf99..b06cec6212 100644 --- a/src/soc/nvidia/tegra210/include/soc/dma.h +++ b/src/soc/nvidia/tegra210/include/soc/dma.h @@ -3,7 +3,6 @@ #ifndef __NVIDIA_TEGRA210_DMA_H__ #define __NVIDIA_TEGRA210_DMA_H__ -#include #include #include diff --git a/src/soc/nvidia/tegra210/spi.c b/src/soc/nvidia/tegra210/spi.c index eae8f39cc9..8fde9c2ea7 100644 --- a/src/soc/nvidia/tegra210/spi.c +++ b/src/soc/nvidia/tegra210/spi.c @@ -7,7 +7,6 @@ #include #include #include -#include #include #include #include From e83c56ae46fd8204b8f39b6637f3ae21a6db0646 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 24 May 2020 12:58:39 +0200 Subject: [PATCH 0032/1155] src: Remove unused 'include ' Change-Id: I79eea0a00c2de54f82b372229381534707a295bb Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41681 Reviewed-by: Angel Pons Reviewed-by: Aaron Durbin Tested-by: build bot (Jenkins) --- src/security/vboot/vboot_common.c | 1 - 1 file changed, 1 deletion(-) diff --git a/src/security/vboot/vboot_common.c b/src/security/vboot/vboot_common.c index 30a2c2f668..1cddeeb5f3 100644 --- a/src/security/vboot/vboot_common.c +++ b/src/security/vboot/vboot_common.c @@ -3,7 +3,6 @@ #include #include #include -#include #include #include #include From d50cde279b1523f5c6765e02c6de2af405d25982 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 24 May 2020 14:29:27 +0200 Subject: [PATCH 0033/1155] src: Remove unused '#include ' Found using: diff <(git grep -l '#include ' -- src/) <(git grep -l 'cbfs_boot_map_optionrom\|cbfs_boot_map_optionrom_revision\|cbfs_boot_locate\|cbfs_boot_map_with_leak\|cbfs_locate_file_in_region\|cbfs_boot_load_file\|cbfs_load_and_decompress\|cbfs_prog_stage_load\|cbfs_boot_region_device' -- src/) |grep '<' |grep -v vendorcode Also add missing 'include ' in src/soc/qualcomm/sc7180/qupv3_config.c Change-Id: Icaecb5b910888f34cddedab7b2f64eaf6d01ad66 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41682 Reviewed-by: Angel Pons Reviewed-by: Wim Vervoorn Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/arch/riscv/fit_payload.c | 1 - src/drivers/pc80/rtc/mc146818rtc.c | 1 - src/mainboard/facebook/fbg1701/romstage.c | 1 - src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c | 1 - src/mainboard/intel/kblrvp/romstage.c | 1 - src/mainboard/intel/tglrvp/romstage_fsp_params.c | 1 - src/mainboard/portwell/m107/romstage.c | 1 - src/mainboard/sifive/hifive-unleashed/media.c | 1 - src/soc/intel/apollolake/mmap_boot.c | 1 - src/soc/intel/xeon_sp/cpx/chip.c | 1 - 10 files changed, 10 deletions(-) diff --git a/src/arch/riscv/fit_payload.c b/src/arch/riscv/fit_payload.c index 2e676c799d..abce57ee08 100644 --- a/src/arch/riscv/fit_payload.c +++ b/src/arch/riscv/fit_payload.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ -#include #include #include #include diff --git a/src/drivers/pc80/rtc/mc146818rtc.c b/src/drivers/pc80/rtc/mc146818rtc.c index 79bb5eb34a..3227510941 100644 --- a/src/drivers/pc80/rtc/mc146818rtc.c +++ b/src/drivers/pc80/rtc/mc146818rtc.c @@ -9,7 +9,6 @@ #include #include #include -#include #include #include #include diff --git a/src/mainboard/facebook/fbg1701/romstage.c b/src/mainboard/facebook/fbg1701/romstage.c index 6dafd8a290..f307f95d73 100644 --- a/src/mainboard/facebook/fbg1701/romstage.c +++ b/src/mainboard/facebook/fbg1701/romstage.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include diff --git a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c index 2cd86379b4..5b7445f067 100644 --- a/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c +++ b/src/mainboard/intel/cannonlake_rvp/romstage_fsp_params.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/intel/kblrvp/romstage.c b/src/mainboard/intel/kblrvp/romstage.c index 281a24f8b5..a3fb285d54 100644 --- a/src/mainboard/intel/kblrvp/romstage.c +++ b/src/mainboard/intel/kblrvp/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index d4433a1d66..47507f4eed 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -6,7 +6,6 @@ #include #include #include -#include #include "board_id.h" #include "spd/spd.h" diff --git a/src/mainboard/portwell/m107/romstage.c b/src/mainboard/portwell/m107/romstage.c index 4f666e2ebf..3ba12f30ff 100644 --- a/src/mainboard/portwell/m107/romstage.c +++ b/src/mainboard/portwell/m107/romstage.c @@ -1,6 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#include #include #include #include diff --git a/src/mainboard/sifive/hifive-unleashed/media.c b/src/mainboard/sifive/hifive-unleashed/media.c index 9f91bcb309..2ba6d2b870 100644 --- a/src/mainboard/sifive/hifive-unleashed/media.c +++ b/src/mainboard/sifive/hifive-unleashed/media.c @@ -2,7 +2,6 @@ #include #include -#include #include #include #include diff --git a/src/soc/intel/apollolake/mmap_boot.c b/src/soc/intel/apollolake/mmap_boot.c index b37d760ed0..30c629e4de 100644 --- a/src/soc/intel/apollolake/mmap_boot.c +++ b/src/soc/intel/apollolake/mmap_boot.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include -#include #include #include #include diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 2125f0a891..c19c0cf93c 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -1,7 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include -#include #include #include #include From c5dd57ab655ba6b82c1adb9f58861155852e39fb Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Sun, 24 May 2020 18:04:16 +0200 Subject: [PATCH 0034/1155] mb/google/{daisy,veyron{_mickey,_rialto}}: Remove unused 'include ' Change-Id: I7c0be437e8cb49934913563c6d21056034a50095 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/41684 Reviewed-by: Angel Pons Reviewed-by: Julius Werner Tested-by: build bot (Jenkins) --- src/mainboard/google/daisy/mainboard.c | 1 - src/mainboard/google/veyron/mainboard.c | 1 - src/mainboard/google/veyron_mickey/mainboard.c | 1 - src/mainboard/google/veyron_rialto/mainboard.c | 1 - 4 files changed, 4 deletions(-) diff --git a/src/mainboard/google/daisy/mainboard.c b/src/mainboard/google/daisy/mainboard.c index de600244ed..2f07937475 100644 --- a/src/mainboard/google/daisy/mainboard.c +++ b/src/mainboard/google/daisy/mainboard.c @@ -18,7 +18,6 @@ #include #include #include -#include #include "exynos5250.h" diff --git a/src/mainboard/google/veyron/mainboard.c b/src/mainboard/google/veyron/mainboard.c index 60c9737df9..b270466a1c 100644 --- a/src/mainboard/google/veyron/mainboard.c +++ b/src/mainboard/google/veyron/mainboard.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include "board.h" diff --git a/src/mainboard/google/veyron_mickey/mainboard.c b/src/mainboard/google/veyron_mickey/mainboard.c index f9feb2f81d..25672498d9 100644 --- a/src/mainboard/google/veyron_mickey/mainboard.c +++ b/src/mainboard/google/veyron_mickey/mainboard.c @@ -15,7 +15,6 @@ #include #include #include -#include #include #include "board.h" diff --git a/src/mainboard/google/veyron_rialto/mainboard.c b/src/mainboard/google/veyron_rialto/mainboard.c index 1a5a944a56..9a9ce79e35 100644 --- a/src/mainboard/google/veyron_rialto/mainboard.c +++ b/src/mainboard/google/veyron_rialto/mainboard.c @@ -16,7 +16,6 @@ #include #include #include -#include #include #include From 729c0695e5e93d7f7e48ddd72787769ff62cd8b9 Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 19:50:44 +0200 Subject: [PATCH 0035/1155] sb/intel/bd82x6x: Fix 16-bit read/write PCI_COMMAND register Change-Id: I1589fd8df4ec0fcdcde283513734dfd8458df2f7 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40807 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/southbridge/intel/bd82x6x/azalia.c | 3 +-- src/southbridge/intel/bd82x6x/early_usb_mrc.c | 9 ++----- src/southbridge/intel/bd82x6x/me.c | 12 ++++------ src/southbridge/intel/bd82x6x/me_8.x.c | 12 ++++------ src/southbridge/intel/bd82x6x/pch.c | 24 ++++++++----------- src/southbridge/intel/bd82x6x/pcie.c | 6 ++--- src/southbridge/intel/bd82x6x/smihandler.c | 13 +++++----- src/southbridge/intel/bd82x6x/usb_ehci.c | 6 ++--- 8 files changed, 33 insertions(+), 52 deletions(-) diff --git a/src/southbridge/intel/bd82x6x/azalia.c b/src/southbridge/intel/bd82x6x/azalia.c index 0b460d9b0d..3be7b44676 100644 --- a/src/southbridge/intel/bd82x6x/azalia.c +++ b/src/southbridge/intel/bd82x6x/azalia.c @@ -281,8 +281,7 @@ static void azalia_init(struct device *dev) } /* Set Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); pci_write_config8(dev, 0x3c, 0x0a); // unused? diff --git a/src/southbridge/intel/bd82x6x/early_usb_mrc.c b/src/southbridge/intel/bd82x6x/early_usb_mrc.c index 0896a4d966..f60cc0b706 100644 --- a/src/southbridge/intel/bd82x6x/early_usb_mrc.c +++ b/src/southbridge/intel/bd82x6x/early_usb_mrc.c @@ -18,19 +18,14 @@ void enable_usb_bar(void) { pci_devfn_t usb0 = PCH_EHCI1_DEV; pci_devfn_t usb1 = PCH_EHCI2_DEV; - u32 cmd; /* USB Controller 1 */ pci_write_config32(usb0, PCI_BASE_ADDRESS_0, PCH_EHCI1_TEMP_BAR0); - cmd = pci_read_config32(usb0, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb0, PCI_COMMAND, cmd); + pci_or_config16(usb0, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* USB Controller 2 */ pci_write_config32(usb1, PCI_BASE_ADDRESS_0, PCH_EHCI2_TEMP_BAR0); - cmd = pci_read_config32(usb1, PCI_COMMAND); - cmd |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(usb1, PCI_COMMAND, cmd); + pci_or_config16(usb1, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); } diff --git a/src/southbridge/intel/bd82x6x/me.c b/src/southbridge/intel/bd82x6x/me.c index e1a1edc5ab..4550f7eca7 100644 --- a/src/southbridge/intel/bd82x6x/me.c +++ b/src/southbridge/intel/bd82x6x/me.c @@ -471,6 +471,7 @@ static void intel_me7_finalize_smm(void) { struct me_hfs hfs; u32 reg32; + u16 reg16; mei_base_address = (u32 *) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); @@ -493,10 +494,10 @@ static void intel_me7_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -589,7 +590,6 @@ static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; - u32 reg32; /* Find the MMIO base for the ME interface */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -600,9 +600,7 @@ static int intel_mei_setup(struct device *dev) mei_base_address = (u32*)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/bd82x6x/me_8.x.c b/src/southbridge/intel/bd82x6x/me_8.x.c index 56303e1c78..4fcc090a38 100644 --- a/src/southbridge/intel/bd82x6x/me_8.x.c +++ b/src/southbridge/intel/bd82x6x/me_8.x.c @@ -435,6 +435,7 @@ void intel_me8_finalize_smm(void) { struct me_hfs hfs; u32 reg32; + u16 reg16; mei_base_address = (void *) (pci_read_config32(PCH_ME_DEV, PCI_BASE_ADDRESS_0) & ~0xf); @@ -457,10 +458,10 @@ void intel_me8_finalize_smm(void) mkhi_end_of_post(); /* Make sure IO is disabled */ - reg32 = pci_read_config32(PCH_ME_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(PCH_ME_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(PCH_ME_DEV, PCI_COMMAND, reg32); + pci_write_config16(PCH_ME_DEV, PCI_COMMAND, reg16); /* Hide the PCI device */ RCBA32_OR(FD2, PCH_DISABLE_MEI1); @@ -545,7 +546,6 @@ static int intel_mei_setup(struct device *dev) { struct resource *res; struct mei_csr host; - u32 reg32; /* Find the MMIO base for the ME interface */ res = find_resource(dev, PCI_BASE_ADDRESS_0); @@ -556,9 +556,7 @@ static int intel_mei_setup(struct device *dev) mei_base_address = (u32 *)(uintptr_t)res->base; /* Ensure Memory and Bus Master bits are set */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); /* Clean up status for next message */ read_host_csr(&host); diff --git a/src/southbridge/intel/bd82x6x/pch.c b/src/southbridge/intel/bd82x6x/pch.c index 4fb77a1795..00d5e12408 100644 --- a/src/southbridge/intel/bd82x6x/pch.c +++ b/src/southbridge/intel/bd82x6x/pch.c @@ -301,7 +301,7 @@ static void pch_pcie_devicetree_update( static void pch_pcie_enable(struct device *dev) { struct southbridge_intel_bd82x6x_config *config = dev->chip_info; - u32 reg32; + u16 reg16; if (!config) return; @@ -358,10 +358,10 @@ static void pch_pcie_enable(struct device *dev) } /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Do not claim downstream transactions for PCIe ports */ new_rpfn |= RPFN_HIDE(PCI_FUNC(dev->path.pci.devfn)); @@ -388,9 +388,7 @@ static void pch_pcie_enable(struct device *dev) } /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } /* @@ -410,7 +408,7 @@ static void pch_pcie_enable(struct device *dev) void pch_enable(struct device *dev) { - u32 reg32; + u16 reg16; /* PCH PCIe Root Ports get special handling */ if (PCI_SLOT(dev->path.pci.devfn) == PCH_PCIE_DEV_SLOT) @@ -420,18 +418,16 @@ void pch_enable(struct device *dev) printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); /* Ensure memory, io, and bus master are all disabled */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | + reg16 = pci_read_config16(dev, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY | PCI_COMMAND_IO); - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_write_config16(dev, PCI_COMMAND, reg16); /* Hide this device if possible */ pch_hide_devfn(dev->path.pci.devfn); } else { /* Enable SERR */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); } } diff --git a/src/southbridge/intel/bd82x6x/pcie.c b/src/southbridge/intel/bd82x6x/pcie.c index 15c79ba440..86935f8efd 100644 --- a/src/southbridge/intel/bd82x6x/pcie.c +++ b/src/southbridge/intel/bd82x6x/pcie.c @@ -205,15 +205,12 @@ static void pch_pcie_pm_late(struct device *dev) static void pci_init(struct device *dev) { u16 reg16; - u32 reg32; struct southbridge_intel_bd82x6x_config *config = dev->chip_info; printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); /* Enable Bus Master */ - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); /* Set Cache Line Size to 0x10 */ // This has no effect but the OS might expect it @@ -225,6 +222,7 @@ static void pci_init(struct device *dev) pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); #ifdef EVEN_MORE_DEBUG + u32 reg32; reg32 = pci_read_config32(dev, 0x20); printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); reg32 = pci_read_config32(dev, 0x24); diff --git a/src/southbridge/intel/bd82x6x/smihandler.c b/src/southbridge/intel/bd82x6x/smihandler.c index f778f7aec1..57b595999a 100644 --- a/src/southbridge/intel/bd82x6x/smihandler.c +++ b/src/southbridge/intel/bd82x6x/smihandler.c @@ -93,7 +93,7 @@ void southbridge_gate_memory_reset(void) static void xhci_sleep(u8 slp_typ) { - u32 reg32, xhci_bar; + u32 xhci_bar; u16 reg16; switch (slp_typ) { @@ -103,9 +103,8 @@ static void xhci_sleep(u8 slp_typ) reg16 &= ~0x03UL; pci_write_config32(PCH_XHCI_DEV, 0x74, reg16); - reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); - reg32 |= (PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + pci_or_config16(PCH_XHCI_DEV, PCI_COMMAND, PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY); xhci_bar = pci_read_config32(PCH_XHCI_DEV, PCI_BASE_ADDRESS_0) & ~0xFUL; @@ -119,9 +118,9 @@ static void xhci_sleep(u8 slp_typ) if ((xhci_bar + 0x4F0) & 1) pch_iobp_update(0xEC000382, ~0UL, (3 << 2)); - reg32 = pci_read_config32(PCH_XHCI_DEV, PCI_COMMAND); - reg32 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); - pci_write_config32(PCH_XHCI_DEV, PCI_COMMAND, reg32); + reg16 = pci_read_config16(PCH_XHCI_DEV, PCI_COMMAND); + reg16 &= ~(PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY); + pci_write_config16(PCH_XHCI_DEV, PCI_COMMAND, reg16); reg16 = pci_read_config16(PCH_XHCI_DEV, 0x74); reg16 |= 0x03; diff --git a/src/southbridge/intel/bd82x6x/usb_ehci.c b/src/southbridge/intel/bd82x6x/usb_ehci.c index 0f3a1b9ca3..8bc45f69da 100644 --- a/src/southbridge/intel/bd82x6x/usb_ehci.c +++ b/src/southbridge/intel/bd82x6x/usb_ehci.c @@ -30,10 +30,8 @@ static void usb_ehci_init(struct device *dev) pci_write_config32(dev, 0xfc, 0x205b1708); #endif - reg32 = pci_read_config32(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_MASTER; - //reg32 |= PCI_COMMAND_SERR; - pci_write_config32(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER); + //pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR); /* For others, done in MRC. */ #if CONFIG(USE_NATIVE_RAMINIT) From cb4672885e636206101a3266fd6ae001447d4f5d Mon Sep 17 00:00:00 2001 From: Elyes HAOUAS Date: Tue, 28 Apr 2020 19:55:10 +0200 Subject: [PATCH 0036/1155] sb/intel/i82371eb: Fix 16-bit read/write PCI_COMMAND register Change-Id: Icecda127a7229c1410c73a6fdd0898430f7eceb2 Signed-off-by: Elyes HAOUAS Reviewed-on: https://review.coreboot.org/c/coreboot/+/40809 Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/southbridge/intel/i82371eb/isa.c | 4 +--- 1 file changed, 1 insertion(+), 3 deletions(-) diff --git a/src/southbridge/intel/i82371eb/isa.c b/src/southbridge/intel/i82371eb/isa.c index efbfb22470..ae35d90b2c 100644 --- a/src/southbridge/intel/i82371eb/isa.c +++ b/src/southbridge/intel/i82371eb/isa.c @@ -27,9 +27,7 @@ static void isa_init(struct device *dev) /* * Enable special cycles, needed for soft poweroff. */ - reg32 = pci_read_config16(dev, PCI_COMMAND); - reg32 |= PCI_COMMAND_SPECIAL; - pci_write_config16(dev, PCI_COMMAND, reg32); + pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SPECIAL); /* * The PIIX4 can support the full ISA bus, or the Extended I/O (EIO) From f01a7696f6f17de182ef6153f5dca4893d084910 Mon Sep 17 00:00:00 2001 From: Stefan Ott Date: Wed, 22 Apr 2020 23:20:03 +0200 Subject: [PATCH 0037/1155] mb/lenovo/x230: Add support for ThinkLight With this patch, the ThinkLight on the ThinkPad X230 can be controlled through the OS. This was initially done for the X201 in f63fbdb6: mb/lenovo/x201: Add support for ThinkLight. After applying this patch, the light can be controlled like this: echo on >/proc/acpi/ibm/light echo off >/proc/acpi/ibm/light Or through sysfs at /sys/class/leds/tpacpi::thinklight Change-Id: Idd93b26f52eccb8fc79888f1e45117f26d694291 Signed-off-by: Stefan Ott Tested-by: Alexander Couzens Reviewed-on: https://review.coreboot.org/c/coreboot/+/40669 Reviewed-by: Alexander Couzens Reviewed-by: Angel Pons Tested-by: build bot (Jenkins) --- src/mainboard/lenovo/x230/dsdt.asl | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index f0964d3561..b83fe38daa 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -35,4 +35,5 @@ DefinitionBlock( } #include + #include } From 2fc0b1c0184fa74acd7c1003f717039bc4b1457e Mon Sep 17 00:00:00 2001 From: Johnny Lin Date: Mon, 20 Apr 2020 18:56:52 +0800 Subject: [PATCH 0038/1155] soc/xeon_sp/skx: Define MSR PPIN related registers MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit These changes are in accordance with the documentation: [*] page 208-209 Intel(R) 64 and IA-32 Architectures, Software Developer’s Manual, Volume 4: Model-Specific Registers. May 2019. Order Number: 335592-070US Tested on OCP Tioga Pass. Signed-off-by: Johnny Lin Change-Id: I5e1de8bcb651fb8ae8b106db1978235b0dd84c47 Reviewed-on: https://review.coreboot.org/c/coreboot/+/40523 Reviewed-by: Frans Hendriks Reviewed-by: Maxim Polyakov Tested-by: build bot (Jenkins) --- src/soc/intel/xeon_sp/skx/include/soc/msr.h | 9 +++++++++ 1 file changed, 9 insertions(+) diff --git a/src/soc/intel/xeon_sp/skx/include/soc/msr.h b/src/soc/intel/xeon_sp/skx/include/soc/msr.h index 2b1597bb4f..dd05adc83f 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/msr.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/msr.h @@ -96,4 +96,13 @@ #define EPB_ENERGY_POLICY_SHIFT 3 #define EPB_ENERGY_POLICY_MASK (0xf << EPB_ENERGY_POLICY_SHIFT) +/* MSR Protected Processor Inventory Number */ +#define MSR_PPIN_CTL 0x04e +#define MSR_PPIN_CTL_LOCK 0x1 +#define MSR_PPIN_CTL_ENABLE_SHIFT 1 +#define MSR_PPIN_CTL_ENABLE (0x1 << MSR_PPIN_CTL_ENABLE_SHIFT) +#define MSR_PPIN 0x04f +#define MSR_PPIN_CAP_SHIFT 23 +#define MSR_PPIN_CAP (0x1 << MSR_PPIN_CAP_SHIFT) + #endif /* _SOC_MSR_H_ */ From 6258ec9f7019bfb644e1666fed17a2b302da39e3 Mon Sep 17 00:00:00 2001 From: Matt DeVillier Date: Wed, 27 May 2020 12:23:24 -0500 Subject: [PATCH 0039/1155] mb/purism/librem*: drop EC chip device CB:35086 exposed that the devicetree listed an EC chip for which there is no actual driver; the EC is entirely ACPI code (.asl) included by the board's ec.asl. Remove the unnecessary EC chip driver from both boards, as well as the unnecessary Kconfig selection for librem_bdw. Test: build/boot Librem 13v1, 13v4, verify battery info etc still correct. Signed-off-by: Matt DeVillier Change-Id: I5cb0b51881ab8f14e9ec693485f673f4284b5f14 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41788 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons --- src/mainboard/purism/librem_bdw/Kconfig | 1 - src/mainboard/purism/librem_bdw/devicetree.cb | 6 +----- src/mainboard/purism/librem_skl/devicetree.cb | 3 --- 3 files changed, 1 insertion(+), 9 deletions(-) diff --git a/src/mainboard/purism/librem_bdw/Kconfig b/src/mainboard/purism/librem_bdw/Kconfig index dcfe78e752..202a35d79e 100644 --- a/src/mainboard/purism/librem_bdw/Kconfig +++ b/src/mainboard/purism/librem_bdw/Kconfig @@ -2,7 +2,6 @@ config BOARD_PURISM_BASEBOARD_LIBREM_BDW def_bool n select SYSTEM_TYPE_LAPTOP select BOARD_ROMSIZE_KB_8192 - select EC_PURISM_LIBREM select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES select INTEL_GMA_HAVE_VBT diff --git a/src/mainboard/purism/librem_bdw/devicetree.cb b/src/mainboard/purism/librem_bdw/devicetree.cb index 13b9e5e729..0d44cd734f 100644 --- a/src/mainboard/purism/librem_bdw/devicetree.cb +++ b/src/mainboard/purism/librem_bdw/devicetree.cb @@ -52,11 +52,7 @@ chip soc/intel/broadwell device pci 1c.5 on end # PCIe Port #6 - M.2 NVMe device pci 1d.0 off end # USB2 EHCI device pci 1e.0 off end # PCI bridge - device pci 1f.0 on - chip ec/purism/librem - device pnp 0c09.0 on end - end - end # LPC bridge + device pci 1f.0 on end # LPC bridge device pci 1f.2 on end # SATA Controller device pci 1f.3 on end # SMBus device pci 1f.6 off end # Thermal diff --git a/src/mainboard/purism/librem_skl/devicetree.cb b/src/mainboard/purism/librem_skl/devicetree.cb index a439e02689..d44d2ada73 100644 --- a/src/mainboard/purism/librem_skl/devicetree.cb +++ b/src/mainboard/purism/librem_skl/devicetree.cb @@ -208,9 +208,6 @@ chip soc/intel/skylake device pci 1d.2 off end # PCI Express Port 11 device pci 1d.3 off end # PCI Express Port 12 device pci 1f.0 on - chip ec/purism/librem - device pnp 0c09.0 on end - end chip drivers/pc80/tpm device pnp 0c31.0 on end end From e76149767479808c9208812b8809b03078ba4566 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Tue, 26 May 2020 08:11:33 +0300 Subject: [PATCH 0040/1155] mb/asrock/h110m: Select MAINBOARD_HAS_LPC_TPM MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Change-Id: I6d6a24cb66a104c549790f039049a17ecbef208f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/41714 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Maxim Polyakov --- src/mainboard/asrock/h110m/Kconfig | 1 + 1 file changed, 1 insertion(+) diff --git a/src/mainboard/asrock/h110m/Kconfig b/src/mainboard/asrock/h110m/Kconfig index eebce57d49..425aff4868 100644 --- a/src/mainboard/asrock/h110m/Kconfig +++ b/src/mainboard/asrock/h110m/Kconfig @@ -16,6 +16,7 @@ config BOARD_SPECIFIC_OPTIONS select SUPERIO_NUVOTON_NCT6791D_COM_A select REALTEK_8168_RESET select RT8168_SET_LED_MODE + select MAINBOARD_HAS_LPC_TPM config IRQ_SLOT_COUNT int From 641642e11ce9a7e9509a54cb1e917ed89b965e3d Mon Sep 17 00:00:00 2001 From: Jonathan Zhang Date: Tue, 26 May 2020 13:42:28 -0700 Subject: [PATCH 0041/1155] vendorcode/intel/fsp/fsp2_0/cpx_sp: update to FSP WW20 release Update Cooperlake-SP (CPX-SP) FSP header files to WW20 release. As CPX-SP FSP engineering is on-going (the processor Mass Production is some time in this year). These header files will be adjusted when changes are necessary with newer FSP release. This commit corresponds to FSP release WW20 (tag WHITLEY.0.PRB.0016.D.65). Also update soc/xeon_sp code file and Skylake-SP header file accordingly to use FsptPort80RouteDisable instead of PcdPort80RouteDisable. Signed-off-by: Jonathan Zhang Signed-off-by: Johnny Lin Signed-off-by: Reddy Chagam Change-Id: I8bc6882e47de23d83ba0f521bb12a10dace523ce Reviewed-on: https://review.coreboot.org/c/coreboot/+/40034 Tested-by: build bot (Jenkins) Reviewed-by: Philipp Deppenwiese --- src/soc/intel/xeon_sp/bootblock.c | 2 +- .../cooperlake_sp/FirmwareVersionInfoHob.h | 68 +++ .../intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h | 48 +- .../intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h | 566 +++++++++++++++++- .../intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h | 188 +++++- .../intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h | 96 ++- .../intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h | 205 +++++++ .../fsp/fsp2_0/cooperlake_sp/hob_iiouds.h | 306 ++++++++++ .../fsp/fsp2_0/cooperlake_sp/hob_memmap.h | 109 ++++ .../intel/fsp/fsp2_0/skylake_sp/FsptUpd.h | 2 +- 10 files changed, 1547 insertions(+), 43 deletions(-) create mode 100644 src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h create mode 100644 src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h diff --git a/src/soc/intel/xeon_sp/bootblock.c b/src/soc/intel/xeon_sp/bootblock.c index 72d9742af8..f6653e2034 100644 --- a/src/soc/intel/xeon_sp/bootblock.c +++ b/src/soc/intel/xeon_sp/bootblock.c @@ -25,7 +25,7 @@ const FSPT_UPD temp_ram_init_params = { .Reserved1 = {0}, }, .FsptConfig = { - .PcdFsptPort80RouteDisable = 0, + .FsptPort80RouteDisable = 0, .ReservedTempRamInitUpd = {0}, }, .UnusedUpdSpace0 = {0}, diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h new file mode 100644 index 0000000000..98a16d7752 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FirmwareVersionInfoHob.h @@ -0,0 +1,68 @@ +/** @file + Header file for Firmware Version Information + + @copyright + Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.
+ + This program and the accompanying materials are licensed and made available under + the terms and conditions of the BSD License which accompanies this distribution. + The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _FIRMWARE_VERSION_INFO_HOB_H_ +#define _FIRMWARE_VERSION_INFO_HOB_H_ + +#include +#include +#include + +#pragma pack(1) +/// +/// Firmware Version Structure +/// +typedef struct { + UINT8 MajorVersion; + UINT8 MinorVersion; + UINT8 Revision; + UINT16 BuildNumber; +} FIRMWARE_VERSION; + +/// +/// Firmware Version Information Structure +/// +typedef struct { + UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name + UINT8 VersionStringIndex; ///< Offset 1 Index of Version String + FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version +} FIRMWARE_VERSION_INFO; + +#ifndef __SMBIOS_STANDARD_H__ +/// +/// The Smbios structure header. +/// +typedef struct { + UINT8 Type; + UINT8 Length; + UINT16 Handle; +} SMBIOS_STRUCTURE; +#endif + +/// +/// Firmware Version Information HOB Structure +/// +typedef struct { + EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB + SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB + UINT8 Count; ///< Offset 28 Number of FVI elements included. +/// +/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer +/// +} FIRMWARE_VERSION_INFO_HOB; +#pragma pack() + +#endif // _FIRMWARE_VERSION_INFO_HOB_H_ diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h index 086c1181ef..7491aca9a8 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspUpd.h @@ -1,18 +1,48 @@ -/* - * These are fake files which only contain padding and some known - * data structures from FSP2.x spec. - */ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ #ifndef __FSPUPD_H__ #define __FSPUPD_H__ -#include #include -#define FSP_M_CONFIG FSPM_CONFIG +#pragma pack(1) -#define FSPT_UPD_SIGNATURE 0x545F445055434F53ULL /* 'SOCUPD_T' */ -#define FSPM_UPD_SIGNATURE 0x4D5F445055434F53ULL /* 'SOCUPD_M' */ -#define FSPS_UPD_SIGNATURE 0x535F445055434F53ULL /* 'SOCUPD_S' */ +#define FSPT_UPD_SIGNATURE 0x545F445055434F53 /* 'SOCUPD_T' */ + +#define FSPM_UPD_SIGNATURE 0x4D5F445055434F53 /* 'SOCUPD_M' */ + +#define FSPS_UPD_SIGNATURE 0x535F445055434F53 /* 'SOCUPD_S' */ + +#pragma pack() #endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h index bdd80ece7d..c4c23dfb94 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspmUpd.h @@ -1,22 +1,566 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + #ifndef __FSPMUPD_H__ #define __FSPMUPD_H__ -#include #include -#pragma pack (1) +#define SPEED_REC_96GT 0 +#define SPEED_REC_104GT 1 +#define ADAPTIVE_CTLE 0x3f -typedef struct { -uint8_t padding[208]; -} FSPM_CONFIG; +#define CPXSP_2S6KTI_EPARAM_TABLE \ + /* Socket 0 */ \ + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), 0x2C33383F, ADAPTIVE_CTLE}, \ + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), 0x2B35353F, ADAPTIVE_CTLE}, \ + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), 0x2D37353F, ADAPTIVE_CTLE}, \ + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), 0x2D37353F, ADAPTIVE_CTLE}, \ + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), 0x2D37353F, ADAPTIVE_CTLE}, \ + {0x0, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), 0x2C35363F, ADAPTIVE_CTLE}, \ + /* Socket 1 */ \ + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK0), 0x2C33383F, ADAPTIVE_CTLE}, \ + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK1), 0x2B35353F, ADAPTIVE_CTLE}, \ + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK2), 0x2D35373F, ADAPTIVE_CTLE}, \ + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK3), 0x2D35373F, ADAPTIVE_CTLE}, \ + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK4), 0x2A2F3A3F, ADAPTIVE_CTLE}, \ + {0x1, (1 << SPEED_REC_96GT) | (1 << SPEED_REC_104GT), (1 << KTI_LINK5), 0x2C35363F, ADAPTIVE_CTLE} + +#define CPXSP_2S6KTI_EPARAM_TABLE_COUNT 12 // NOTE - needs to match number of elements in CPXSP_2S6KTI_EPARAM_TABLE -typedef struct { - FSP_UPD_HEADER FspUpdHeader; - FSPM_ARCH_UPD FspmArchUpd; - FSPM_CONFIG FspmConfig; - uint16_t UpdTerminator; -} FSPM_UPD; #pragma pack(1) +typedef struct { + UINT8 SocketID; + UINT8 Freq; + UINT32 Link; + UINT32 AllLanesTXEQ; + UINT8 CTLEPEAK; +} ALL_LANES_EPARAM_LINK_INFO; + +typedef enum { + KTI_LINK0 = 0x0, + KTI_LINK1, + KTI_LINK2, + KTI_LINK3, + KTI_LINK4, + KTI_LINK5 +} KTI_LOGIC_LINK; + +#define IIO_BIFURCATE_xxxxxxxx 0xFE +#define IIO_BIFURCATE_x4x4x4x4 0x0 +#define IIO_BIFURCATE_x4x4xxx8 0x1 +#define IIO_BIFURCATE_xxx8x4x4 0x2 +#define IIO_BIFURCATE_xxx8xxx8 0x3 +#define IIO_BIFURCATE_xxxxxx16 0x4 +#define IIO_BIFURCATE_x2x2x4x8 0x5 +#define IIO_BIFURCATE_x4x2x2x8 0x6 +#define IIO_BIFURCATE_x8x2x2x4 0x7 +#define IIO_BIFURCATE_x8x4x2x2 0x8 +#define IIO_BIFURCATE_x2x2x4x4x4 0x9 +#define IIO_BIFURCATE_x4x2x2x4x4 0xA +#define IIO_BIFURCATE_x4x4x2x2x4 0xB +#define IIO_BIFURCATE_x4x4x4x2x2 0xC +#define IIO_BIFURCATE_x2x2x2x2x8 0xD +#define IIO_BIFURCATE_x8x2x2x2x2 0xE +#define IIO_BIFURCATE_x2x2x2x2x4x4 0xF +#define IIO_BIFURCATE_x2x2x4x2x2x4 0x10 +#define IIO_BIFURCATE_x2x2x4x4x2x2 0x11 +#define IIO_BIFURCATE_x4x2x2x2x2x4 0x12 +#define IIO_BIFURCATE_x4x2x2x4x2x2 0x13 +#define IIO_BIFURCATE_x4x4x2x2x2x2 0x14 +#define IIO_BIFURCATE_x2x2x2x2x2x2x4 0x15 +#define IIO_BIFURCATE_x2x2x2x2x4x2x2 0x16 +#define IIO_BIFURCATE_x2x2x4x2x2x2x2 0x17 +#define IIO_BIFURCATE_x4x2x2x2x2x2x2 0x18 +#define IIO_BIFURCATE_x2x2x2x2x2x2x2x2 0x19 +#define IIO_BIFURCATE_AUTO 0xFF + +typedef struct { + UINT8 Socket; + UINT8 IouNumber; + UINT8 Bifurcation; +} UPD_IIO_BIFURCATION_DATA_ENTRY; + +typedef enum { + Iio_Socket0 = 0, + Iio_Socket1, + Iio_Socket2, + Iio_Socket3, + Iio_Socket4, + Iio_Socket5, + Iio_Socket6, + Iio_Socket7 +} IIO_SOCKETS; + +typedef enum { + Iio_Iou0 = 0, + Iio_Iou1, + Iio_Iou2, + Iio_Iou3, + Iio_Mcp0, + Iio_Mcp1, + Iio_IouMax +} IIO_IOUS; + +/** FSP-M Configuration +**/ +typedef struct { + +/** Offset 0x0040 - Customer Revision + The Customer can set this revision string for their own purpose. +**/ + UINT8 CustomerRevision[32]; + +/** Offset 0x0060 - Bus Ratio + Indicates the ratio of Bus/MMIOL/IO resource to be allocated for each CPU's IIO +**/ + UINT8 BusRatio[8]; + +/** Offset 0x0068 - D2K Credit Config + Set the D2K Credit Config + 1:Min, 2:Med, 3:Max +**/ + UINT8 D2KCreditConfig; + +/** Offset 0x0069 - Snoop Throttle Config + Set the Snoop Throttle Config + 0:DIS, 1:Min, 2:Med, 3:Max +**/ + UINT8 SnoopThrottleConfig; + +/** Offset 0x006A - Legacy VGA Soc + Socket that claims the legacy VGA range +**/ + UINT8 LegacyVgaSoc; + +/** Offset 0x006B - Legacy VGA Stack + Stack that claims the legacy VGA range +**/ + UINT8 LegacyVgaStack; + +/** Offset 0x006C - Pcie P2P Performance Mode + Determine if to enable PCIe P2P Performance Mode + $EN_DIS +**/ + UINT8 P2pRelaxedOrdering; + +/** Offset 0x006D - Debug Print Level + Set Debug Print Level + 1:Fatal, 2:Warning, 4:Summary, 8:Detail, 0x0F:All +**/ + UINT8 DebugPrintLevel; + +/** Offset 0x006E - SNC + Enable or Disable SNC + $EN_DIS +**/ + UINT8 SncEn; + +/** Offset 0x006F - UMA Clustering + Set UMA Clusters + 0:Disable, 2:Two Clusters, 4:Four Clusters +**/ + UINT8 UmaClustering; + +/** Offset 0x0070 - IODC Mode + IODC Setup Option + 0:Disable, 1:Auto, 2:Push, 3:AllocFlow 4:NonAlloc, 5:WCILF +**/ + UINT8 IoDcMode; + +/** Offset 0x0071 - Degrade Precedence + Setup Degrade Precedence + 0:Topology, 1:Feature +**/ + UINT8 DegradePrecedence; + +/** Offset 0x0072 - Degrade 4 Socket Preference + Setup Degrade 4 Socket Preference + 0:Fully Connect, 1:Dual Link Ring +**/ + UINT8 Degrade4SPreference; + +/** Offset 0x0073 - Directory Mode + Enable or Disable Directory Mode + $EN_DIS +**/ + UINT8 DirectoryModeEn; + +/** Offset 0x0074 - XPT Prefetch Enable + Enable or Disable XPT Prefetch +**/ + UINT8 XptPrefetchEn; + +/** Offset 0x0075 - KTI Prefetch Enable + Enable or Disable KTI Prefetch + $EN_DIS +**/ + UINT8 KtiPrefetchEn; + +/** Offset 0x0076 - XPT Remote Prefetch Enable + Enable or Disable XPT Remote Prefetch Enable + $EN_DIS +**/ + UINT8 XptRemotePrefetchEn; + +/** Offset 0x0077 - KTI FPGA + Enable or Disable KTI FPGA + $EN_DIS +**/ + UINT8 KtiFpgaEnable[8]; + +/** Offset 0x007F - DDRT QoS Mode + Setup DDRT QoS +**/ + UINT8 DdrtQosMode; + +/** Offset 0x0080 - KTI Link Speed Mode + Choose KTI Link Speed Mode +**/ + UINT8 KtiLinkSpeedMode; + +/** Offset 0x0081 - KTI Link Speed + Setup KTI Link Speed +**/ + UINT8 KtiLinkSpeed; + +/** Offset 0x0082 - KTI Link L0p + Enable or Disable KTI Link L0p +**/ + UINT8 KtiLinkL0pEn; + +/** Offset 0x0083 - KTI Link L1 + Enable or Disable KTI Link L1 +**/ + UINT8 KtiLinkL1En; + +/** Offset 0x0084 - KTI Failover + Enable or Disable KTI Failover +**/ + UINT8 KtiFailoverEn; + +/** Offset 0x0085 - KTI LB Enable + Enable or Disable KTI LB + $EN_DIS +**/ + UINT8 KtiLbEn; + +/** Offset 0x0086 - KTI CRC Mode + Select KTI CRC Mode + 0:16bit, 1:32bit, 2:Auto +**/ + UINT8 KtiCrcMode; + +/** Offset 0x0087 - KTI CPU Socket Hotplug + Enable or Disable KTI CPU Socket Hotplug + $EN_DIS +**/ + UINT8 KtiCpuSktHotPlugEn; + +/** Offset 0x0088 - KTI CPU Socket HotPlug Topology + Select KTI CPU Socket HotPlug Topology + 0:4Socket, 1:8Socket +**/ + UINT8 KtiCpuSktHotPlugTopology; + +/** Offset 0x0089 - KTI SKU Mismatch Check + Enable or Disable KTI SKU Mismatch Check + $EN_DIS +**/ + UINT8 KtiSkuMismatchCheck; + +/** Offset 0x008A - IRQ Threshold + Select IRQ Threshold + 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High +**/ + UINT8 IrqThreshold; + +/** Offset 0x008B - IRQ Threshold + Enable or Disable + 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High +**/ + UINT8 TorThresLoctoremNorm; + +/** Offset 0x008C - TOR threshold - Loctorem threshold empty + Select TOR threshold - Loctorem threshold empty + 0:Disable, 1:Auto, 2:Low, 3:Medium, 4:High +**/ + UINT8 TorThresLoctoremEmpty; + +/** Offset 0x008D - TSC Sync in Sockets + Enable or Disable TSC Sync in Sockets +**/ + UINT8 TscSyncEn; + +/** Offset 0x008E - HA A to S directory optimization + Enable or Disable HA A to S directory optimization +**/ + UINT8 StaleAtoSOptEn; + +/** Offset 0x008F - LLC Deadline Allocation + Enable or Disable LLC Deadline Allocation + $EN_DIS +**/ + UINT8 LLCDeadLineAlloc; + +/** Offset 0x0090 - Split Lock + Enable or Disable Split Lock +**/ + UINT8 SplitLock; + +/** Offset 0x0091 - MMCFG Base Address + Setup MMCFG Base Address + 0:1G, 1:1.5G, 2:1.75G, 3:2G, 4:2.25G, 5:3G, 6:Auto +**/ + UINT8 mmCfgBase; + +/** Offset 0x0092 - MMCFG Size + Select MMCFG Size + 0:64M, 1:128M, 2:256M, 3:512M, 4:1G, 5:2G, 6: Auto +**/ + UINT8 mmCfgSize; + +/** Offset 0x0093 +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x0094 - MMIO Low Base Address + Select MMIO Low Base Address + 0:, 1:, 2:, 3:, 4:, 5:, 6: +**/ + UINT32 mmiolBase; + +/** Offset 0x0098 - MMIO Low Size + Select MMIO Low Size + $EN_DIS +**/ + UINT32 mmiolSize; + +/** Offset 0x009C - MMIO High Base Address + Select MMIO High Base Address + 0:, 1:, 2:, 3:, 4:, 5:, 6: +**/ + UINT32 mmiohBase; + +/** Offset 0x00A0 - High Gap + Enable or Disable High Gap + $EN_DIS +**/ + UINT8 highGap; + +/** Offset 0x00A1 +**/ + UINT8 UnusedUpdSpace1; + +/** Offset 0x00A2 - MMIO High Size + Select MMIO High Size + 0:, 1:, 2:, 3:, 4:, 5:, 6: +**/ + UINT16 mmiohSize; + +/** Offset 0x00A4 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT8 isocEn; + +/** Offset 0x00A5 - DCA + Enable or Disable DCA + $EN_DIS +**/ + UINT8 dcaEn; + +/** Offset 0x00A6 +**/ + UINT8 UnusedUpdSpace2[2]; + +/** Offset 0x00A8 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 BoardTypeBitmask; + +/** Offset 0x00AC - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 AllLanesPtr; + +/** Offset 0x00B0 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 PerLanePtr; + +/** Offset 0x00B4 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 AllLanesSizeOfTable; + +/** Offset 0x00B8 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 PerLaneSizeOfTable; + +/** Offset 0x00BC - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 WaitTimeForPSBP; + +/** Offset 0x00C0 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT8 IsKtiNvramDataReady; + +/** Offset 0x00C1 +**/ + UINT8 UnusedUpdSpace3[3]; + +/** Offset 0x00C4 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 OemHookPostTopologyDiscovery; + +/** Offset 0x00C8 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT32 OemGetResourceMapUpdate; + +/** Offset 0x00CC - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT8 BoardId; + +/** Offset 0x00CD - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT8 WaSerializationEn; + +/** Offset 0x00CE - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT8 KtiInEnableMktme; + +/** Offset 0x00CF +**/ + UINT8 UnusedUpdSpace4; + +/** Offset 0x00D0 - Address of IIoBifurcationTable. + The address of the table of IIoBifurcation. + $EN_DIS +**/ + UINT32 IIoBifurcationTablePtr; + +/** Offset 0x00D4 - Number of IIoBifurcationTable Entry + Number of IIoBifurcationTable Entry. If this is not zero, the IIoBifurcationTablePtr + must not be NULL. +**/ + UINT8 NumOfIIoBifurcationTable; + +/** Offset 0x00D5 - PchAdrEn + Enable or Disable PchAdr +**/ + UINT8 PchAdrEn; + +/** Offset 0x00D6 - } TYPE:{Combo + Enable or Disable + $EN_DIS +**/ + UINT8 PchPcieRootPortFunctionSwap; + +/** Offset 0x00D7 - PCH PCIE PLL Ssc + Valid spread range : 0x00-0x14 (A value of 0 is SSC of 0.0%. A value of 20 is SSC + of 2.0%), Auto : 0xFE(Set to hardware default), Disable : 0xFF +**/ + UINT8 PchPciePllSsc; + +/** Offset 0x00D8 - Usage type for PCH PCIE Root Port Index + Index assigned to every PCH PCIE Root Port +**/ + UINT8 PchPciePortIndex[20]; + +/** Offset 0x00EC - Usage type for PCH PCIE Root Port Enable or Disable + 0-19: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PchPcieForceEnable[20]; + +/** Offset 0x0100 - Usage type for PCH PCIE Root Port Link Speed + 0-19: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use + (free running), 0xFF: not used +**/ + UINT8 PchPciePortLinkSpeed[20]; + +/** Offset 0x0114 +**/ + UINT8 ReservedMemoryInitUpd[16]; +} FSP_M_CONFIG; + +/** Fsp M UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPM_ARCH_UPD FspmArchUpd; + +/** Offset 0x0040 +**/ + FSP_M_CONFIG FspmConfig; + +/** Offset 0x0124 +**/ + UINT8 UnusedUpdSpace5[2]; + +/** Offset 0x0126 +**/ + UINT16 UpdTerminator; +} FSPM_UPD; + +#pragma pack() + #endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h index 646c1e2fe6..fc0808430f 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FspsUpd.h @@ -1,20 +1,184 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + #ifndef __FSPSUPD_H__ #define __FSPSUPD_H__ -#pragma pack(1) - #include -typedef struct { - uint8_t padding[54]; -} FSPS_CONFIG; - -typedef struct { - FSP_UPD_HEADER FspUpdHeader; - FSPS_CONFIG FspsConfig; - uint16_t UpdTerminator; -} FSPS_UPD; - #pragma pack(1) + +/** FSP-S Configuration +**/ +typedef struct { + +/** Offset 0x0020 - PCIe Controller 0 Bifurcation + Configure PCI Express controller 0 bifurcation. + 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +**/ + UINT8 BifurcationPcie0; + +/** Offset 0x0021 - PCIe Controller 1 Bifurcation + Configure PCI Express controller 1 bifurcation. + 0:X2X2X2X2, 1:X2X2X4, 2:X4X2X2, 3:X4X4, 4:X8 +**/ + UINT8 BifurcationPcie1; + +/** Offset 0x0022 - Active Core Count + Select # of Active Cores (Default: 0, 0:ALL, 1..15 = 1..15 Cores) + 0:ALL, 1:1, 2:2, 3:3, 4:4, 5:5, 6:6, 7:7, 8:8, 9:9, 10:10, 11:11, 12:12, 13:13, + 14:14, 15:15 +**/ + UINT8 ActiveCoreCount; + +/** Offset 0x0023 +**/ + UINT8 UnusedUpdSpace0; + +/** Offset 0x0024 +**/ + UINT32 CpuMicrocodePatchBase; + +/** Offset 0x0028 +**/ + UINT32 CpuMicrocodePatchSize; + +/** Offset 0x002C - PCIe Controller 0 + Enable / Disable PCI Express controller 0 + $EN_DIS +**/ + UINT8 EnablePcie0; + +/** Offset 0x002D - PCIe Controller 1 + Enable / Disable PCI Express controller 1 + $EN_DIS +**/ + UINT8 EnablePcie1; + +/** Offset 0x002E - Embedded Multi-Media Controller (eMMC) + Enable / Disable Embedded Multi-Media controller + $EN_DIS +**/ + UINT8 EnableEmmc; + +/** Offset 0x002F - LAN Controllers + Enable / Disable LAN controllers, refer to FSP Integration Guide for details. + 0:Disable LAN 0 & LAN 1, 1:Enable LAN 0 & LAN 1, 2:Disable LAN 1 only +**/ + UINT8 EnableGbE; + +/** Offset 0x0030 +**/ + UINT32 FiaMuxConfigRequestPtr; + +/** Offset 0x0034 - PCIe Root Port 0 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort0DeEmphasis; + +/** Offset 0x0035 - PCIe Root Port 1 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort1DeEmphasis; + +/** Offset 0x0036 - PCIe Root Port 2 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort2DeEmphasis; + +/** Offset 0x0037 - PCIe Root Port 3 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort3DeEmphasis; + +/** Offset 0x0038 - PCIe Root Port 4 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort4DeEmphasis; + +/** Offset 0x0039 - PCIe Root Port 5 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort5DeEmphasis; + +/** Offset 0x003A - PCIe Root Port 6 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort6DeEmphasis; + +/** Offset 0x003B - PCIe Root Port 7 DeEmphasis + Desired DeEmphasis level for PCIE root port + 0:6dB, 1:3.5dB +**/ + UINT8 PcieRootPort7DeEmphasis; + +/** Offset 0x003C +**/ + UINT32 EMMCDLLConfigPtr; + +/** Offset 0x0040 +**/ + UINT8 ReservedSiliconInitUpd[16]; +} FSPS_CONFIG; + +/** Fsp S UPD Configuration +**/ +typedef struct { + +/** Offset 0x0000 +**/ + FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ + FSPS_CONFIG FspsConfig; + +/** Offset 0x0050 +**/ + UINT8 UnusedUpdSpace1[6]; + +/** Offset 0x0056 +**/ + UINT16 UpdTerminator; +} FSPS_UPD; + +#pragma pack() + #endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h index a792e703f3..b3c96617c0 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/FsptUpd.h @@ -1,3 +1,35 @@ +/** @file + +Copyright (c) 2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + + This file is automatically generated. Please do NOT modify !!! + +**/ + #ifndef __FSPTUPD_H__ #define __FSPTUPD_H__ @@ -5,25 +37,71 @@ #pragma pack(1) + +/** FSP-T Core UPD +**/ typedef struct { - uint32_t MicrocodeRegionBase; - uint32_t MicrocodeRegionLength; - uint32_t CodeRegionBase; - uint32_t CodeRegionLength; - uint8_t Reserved1[16]; + +/** Offset 0x0020 +**/ + UINT32 MicrocodeRegionBase; + +/** Offset 0x0024 +**/ + UINT32 MicrocodeRegionLength; + +/** Offset 0x0028 +**/ + UINT32 CodeRegionBase; + +/** Offset 0x002C +**/ + UINT32 CodeRegionLength; + +/** Offset 0x0030 +**/ + UINT8 Reserved1[16]; } FSPT_CORE_UPD; +/** FSP-T Configuration +**/ typedef struct { - uint8_t PcdFsptPort80RouteDisable; - uint8_t ReservedTempRamInitUpd[31]; + +/** Offset 0x0040 - Disable Port80 output in FSP-T + Select Port80 Control in FSP-T (0:VPD-Style, 1:Enable Port80 Output, 2:Disable Port80 + Output, refer to FSP Integration Guide for details + 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output +**/ + UINT8 FsptPort80RouteDisable; + +/** Offset 0x0041 +**/ + UINT8 ReservedTempRamInitUpd[31]; } FSPT_CONFIG; +/** Fsp T UPD Configuration +**/ typedef struct { + +/** Offset 0x0000 +**/ FSP_UPD_HEADER FspUpdHeader; + +/** Offset 0x0020 +**/ FSPT_CORE_UPD FsptCoreUpd; + +/** Offset 0x0040 +**/ FSPT_CONFIG FsptConfig; - uint8_t UnusedUpdSpace0[6]; - uint16_t UpdTerminator; + +/** Offset 0x0060 +**/ + UINT8 UnusedUpdSpace0[6]; + +/** Offset 0x0066 +**/ + UINT16 UpdTerminator; } FSPT_UPD; #pragma pack() diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h new file mode 100644 index 0000000000..be9d33f860 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/gpio_fsp.h @@ -0,0 +1,205 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _GPIO_FSP_H_ +#define _GPIO_FSP_H_ + +// +// Below defines are based on GPIO_CONFIG structure fields +// +#define GPIO_CONF_PAD_MODE_MASK 0xF +#define GPIO_CONF_PAD_MODE_BIT_POS 0 +#define GPIO_CONF_HOST_OWN_MASK 0x3 +#define GPIO_CONF_HOST_OWN_BIT_POS 0 +#define GPIO_CONF_DIR_MASK 0x7 +#define GPIO_CONF_DIR_BIT_POS 0 +#define GPIO_CONF_INV_MASK 0x18 +#define GPIO_CONF_INV_BIT_POS 3 +#define GPIO_CONF_OUTPUT_MASK 0x3 +#define GPIO_CONF_OUTPUT_BIT_POS 0 +#define GPIO_CONF_INT_ROUTE_MASK 0x1F +#define GPIO_CONF_INT_ROUTE_BIT_POS 0 +#define GPIO_CONF_INT_TRIG_MASK 0xE0 +#define GPIO_CONF_INT_TRIG_BIT_POS 5 +#define GPIO_CONF_RESET_MASK 0x7 +#define GPIO_CONF_RESET_BIT_POS 0 +#define GPIO_CONF_TERM_MASK 0x1F +#define GPIO_CONF_TERM_BIT_POS 0 +#define GPIO_CONF_PADTOL_MASK 0x60 +#define GPIO_CONF_PADTOL_BIT_POS 5 +#define GPIO_CONF_LOCK_MASK 0x7 +#define GPIO_CONF_LOCK_BIT_POS 0 +#define GPIO_CONF_RXRAW_MASK 0x3 +#define GPIO_CONF_RXRAW_BIT_POS 0 + +typedef enum { GpioHardwareDefault = 0x0 } GPIO_HARDWARE_DEFAULT; + +/// +/// GPIO Pad Mode +/// +typedef enum { + GpioPadModeGpio = 0x1, + GpioPadModeNative1 = 0x3, + GpioPadModeNative2 = 0x5, + GpioPadModeNative3 = 0x7, + GpioPadModeNative4 = 0x9 +} GPIO_PAD_MODE; + +/// +/// Host Software Pad Ownership modes +/// +typedef enum { + GpioHostOwnDefault = 0x0, ///< Leave ownership value unmodified + GpioHostOwnAcpi = 0x1, ///< Set HOST ownership to ACPI + GpioHostOwnGpio = 0x3 ///< Set HOST ownership to GPIO +} GPIO_HOSTSW_OWN; + +/// +/// GPIO Direction +/// +typedef enum { + GpioDirDefault = 0x0, ///< Leave pad direction setting unmodified + GpioDirInOut = + (0x1 | (0x1 << 3)), ///< Set pad for both output and input + GpioDirInInvOut = (0x1 | (0x3 << 3)), ///< Set pad for both output and + ///input with inversion + GpioDirIn = (0x3 | (0x1 << 3)), ///< Set pad for input only + GpioDirInInv = (0x3 | (0x3 << 3)), ///< Set pad for input with inversion + GpioDirOut = 0x5, ///< Set pad for output only + GpioDirNone = 0x7 ///< Disable both output and input +} GPIO_DIRECTION; + +/// +/// GPIO Output State +/// +typedef enum { + GpioOutDefault = 0x0, ///< Leave output value unmodified + GpioOutLow = 0x1, ///< Set output to low + GpioOutHigh = 0x3 ///< Set output to high +} GPIO_OUTPUT_STATE; + +/// +/// GPIO interrupt configuration +/// This setting is applicable only if GPIO is in input mode. +/// GPIO_INT_CONFIG allows to choose which interrupt is generated +/// (IOxAPIC/SCI/SMI/NMI) +/// and how it is triggered (edge or level). +/// Field from GpioIntNmi to GpioIntApic can be OR'ed with GpioIntLevel to +/// GpioIntBothEdgecan +/// to describe an interrupt e.g. GpioIntApic | GpioIntLevel +/// If GPIO is set to cause an SCI then also Gpe is enabled for this pad. +/// Not all GPIO are capable of generating an SMI or NMI interrupt +/// + +typedef enum { + GpioIntDefault = 0x0, ///< Leave value of interrupt routing unmodified + GpioIntDis = 0x1, ///< Disable IOxAPIC/SCI/SMI/NMI interrupt generation + GpioIntNmi = 0x3, ///< Enable NMI interrupt only + GpioIntSmi = 0x5, ///< Enable SMI interrupt only + GpioIntSci = 0x9, ///< Enable SCI interrupt only + GpioIntApic = 0x11, ///< Enable IOxAPIC interrupt only + GpioIntLevel = (0x1 << 5), ///< Set interrupt as level triggered + GpioIntEdge = (0x3 << 5), ///< Set interrupt as edge triggered (type of + ///edge depends on input inversion) + GpioIntLvlEdgDis = (0x5 << 5), ///< Disable interrupt trigger + GpioIntBothEdge = (0x7 << 5) ///< Set interrupt as both edge triggered +} GPIO_INT_CONFIG; + +/// +/// GPIO Power Configuration +/// GPIO_RESET_CONFIG allows to set GPIO Reset (used to reset the specified +/// Pad Register fields). +/// +typedef enum { + GpioResetDefault = 0x0, ///< Leave value of pad reset unmodified + GpioResetPwrGood = 0x1, ///< Powergood reset + GpioResetDeep = 0x3, ///< Deep GPIO Reset + GpioResetNormal = 0x5, ///< GPIO Reset + GpioResetResume = 0x7 ///< Resume Reset (applicable only for GPD group) +} GPIO_RESET_CONFIG; + +/// +/// GPIO Electrical Configuration +/// Set GPIO termination and Pad Tolerance (applicable only for some pads) +/// Field from GpioTermDefault to GpioTermNative can be OR'ed with +/// GpioTolerance1v8. +/// +typedef enum { + GpioTermDefault = 0x0, ///< Leave termination setting unmodified + GpioTermNone = 0x1, ///< none + GpioTermWpd5K = 0x5, ///< 5kOhm weak pull-down + GpioTermWpd20K = 0x9, ///< 20kOhm weak pull-down + GpioTermWpu1K = 0x13, ///< 1kOhm weak pull-up + GpioTermWpu2K = 0x17, ///< 2kOhm weak pull-up + GpioTermWpu5K = 0x15, ///< 5kOhm weak pull-up + GpioTermWpu20K = 0x19, ///< 20kOhm weak pull-up + GpioTermWpu1K2K = 0x1B, ///< 1kOhm & 2kOhm weak pull-up + GpioTermNative = 0x1F, ///< Native function controls pads termination + GpioNoTolerance1v8 = (0x1 << 5), ///< Disable 1.8V pad tolerance + GpioTolerance1v8 = (0x3 << 5) ///< Enable 1.8V pad tolerance +} GPIO_ELECTRICAL_CONFIG; + +/// +/// GPIO LockConfiguration +/// Set GPIO configuration lock and output state lock +/// GpioLockPadConfig and GpioLockOutputState can be OR'ed +/// +typedef enum { + GpioLockDefault = 0x0, ///< Leave lock setting unmodified + GpioPadConfigLock = 0x3, ///< Lock Pad Configuration + GpioOutputStateLock = 0x5 ///< Lock GPIO pad output value +} GPIO_LOCK_CONFIG; + +/// +/// Other GPIO Configuration +/// GPIO_OTHER_CONFIG is used for less often settings and for future extensions +/// Supported settings: +/// - RX raw override to '1' - allows to override input value to '1' +/// This setting is applicable only if in input mode (both in GPIO and +/// native usage). +/// The override takes place at the internal pad state directly from buffer +/// and before the RXINV. +/// +typedef enum { + GpioRxRaw1Default = 0x0, ///< Use default input override value + GpioRxRaw1Dis = 0x1, ///< Don't override input + GpioRxRaw1En = 0x3 ///< Override input to '1' +} GPIO_OTHER_CONFIG; + +// +// Possible values of Pad Ownership +// +typedef enum { + GpioPadOwnHost = 0x0, + GpioPadOwnCsme = 0x1, + GpioPadOwnIsh = 0x2, +} GPIO_PAD_OWN; + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h new file mode 100644 index 0000000000..1ce5d3077a --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_iiouds.h @@ -0,0 +1,306 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _HOB_IIOUDS_H_ +#define _HOB_IIOUDS_H_ + +#include + +#define FSP_HOB_IIO_UNIVERSAL_DATA_GUID { \ + 0xa1, 0x96, 0xf3, 0x7f, 0x7d, 0xee, 0x1e, 0x43, \ + 0xba, 0x53, 0x8f, 0xCa, 0x12, 0x7c, 0x44, 0xc0 \ +} + +#define NUMBER_PORTS_PER_SOCKET 21 +#define MAX_SOCKET 8 // CONFIG_MAX_SOCKET +#define MaxIIO MAX_SOCKET +#define MAX_IIO_STACK 6 +#define MAX_IMC 2 +#define MAX_CH 6 +#define MC_MAX_NODE (MAX_SOCKET * MAX_IMC) + +// Maximum KTI PORTS to be used in structure definition +#if (MAX_SOCKET == 1) + #define MAX_FW_KTI_PORTS 3 +#else + #define MAX_FW_KTI_PORTS 6 +#endif //(MAX_SOCKET == 1) + +#define MAX_LOGIC_IIO_STACK (MAX_IIO_STACK+2) + +#pragma pack(1) + +//--------------------------------------------------------------------------------------// +// Structure definitions for Universal Data Store (UDS) +//--------------------------------------------------------------------------------------// + +typedef enum { + TYPE_SCF_BAR = 0, + TYPE_PCU_BAR, + TYPE_MEM_BAR0, + TYPE_MEM_BAR1, + TYPE_MEM_BAR2, + TYPE_MEM_BAR3, + TYPE_MEM_BAR4, + TYPE_MEM_BAR5, + TYPE_MEM_BAR6, + TYPE_MEM_BAR7, + TYPE_SBREG_BAR, + TYPE_MAX_MMIO_BAR +} MMIO_BARS; + +/// +/// RC version number structure. +/// +typedef struct { + uint8_t Major; + uint8_t Minor; + uint8_t Revision; + uint16_t BuildNumber; +} RC_VERSION; + +/** + IIO PCIe Ports + **/ +typedef enum { + PORT_0 = 0, + // IOU0 + PORT_1A, + PORT_1B, + PORT_1C, + PORT_1D, + // IOU1 + PORT_2A, + PORT_2B, + PORT_2C, + PORT_2D, + // IOU2 + PORT_4A, + PORT_4B, + PORT_4C, + PORT_4D, + // MCP0 + PORT_5A, + PORT_5B, + PORT_5C, + PORT_5D, + // MCP1 + PORT_6A, + PORT_6B, + PORT_6C, + PORT_6D, + MAX_PORTS +} PCIE_PORTS; + +/** + IIO Stacks + **/ +typedef enum { + CSTACK = 0, + PSTACK0, + PSTACK1, + PSTACK2, + PSTACK3, + PSTACK4, + MAX_STACKS +} IIO_STACKS; + +typedef struct uint64_t_struct { + uint32_t lo; + uint32_t hi; +} UINT64_STRUCT; + +typedef struct { + uint8_t Device; + uint8_t Function; +} IIO_PORT_INFO; + +typedef struct { + uint8_t Valid; // TRUE, if the link is valid (i.e reached normal operation) + uint8_t PeerSocId; // Socket ID + uint8_t PeerSocType; // Socket Type (0 - CPU; 1 - IIO) + uint8_t PeerPort; // Port of the peer socket +} QPI_PEER_DATA; + +typedef struct { + uint8_t Valid; + uint32_t MmioBar[TYPE_MAX_MMIO_BAR]; + uint8_t PcieSegment; + UINT64_STRUCT SegMmcfgBase; + uint16_t stackPresentBitmap; + uint16_t M2PciePresentBitmap; + uint8_t TotM3Kti; + uint8_t TotCha; + uint32_t ChaList; + uint32_t SocId; + QPI_PEER_DATA PeerInfo[MAX_FW_KTI_PORTS]; // QPI LEP info +} QPI_CPU_DATA; + +typedef struct { + uint8_t Valid; + uint8_t SocId; + QPI_PEER_DATA PeerInfo[MAX_SOCKET]; // QPI LEP info +} QPI_IIO_DATA; + +typedef struct { + IIO_PORT_INFO PortInfo[NUMBER_PORTS_PER_SOCKET]; +} IIO_DMI_PCIE_INFO; + +typedef enum { + TYPE_UBOX = 0, + TYPE_UBOX_IIO, + TYPE_MCP, + TYPE_FPGA, + TYPE_HFI, + TYPE_NAC, + TYPE_GRAPHICS, + TYPE_DINO, + TYPE_RESERVED, + TYPE_DISABLED, // This item must be prior to stack specific disable types + TYPE_UBOX_IIO_DIS, + TYPE_MCP_DIS, + TYPE_FPGA_DIS, + TYPE_HFI_DIS, + TYPE_NAC_DIS, + TYPE_GRAPHICS_DIS, + TYPE_DINO_DIS, + TYPE_RESERVED_DIS, + TYPE_NONE +} STACK_TYPE; + +typedef struct _STACK_RES { + uint8_t Personality; // see STACK_TYPE for details + uint8_t BusBase; + uint8_t BusLimit; + uint16_t PciResourceIoBase; + uint16_t PciResourceIoLimit; + uint32_t IoApicBase; + uint32_t IoApicLimit; + uint32_t PciResourceMem32Base; + uint32_t PciResourceMem32Limit; + uint64_t PciResourceMem64Base; + uint64_t PciResourceMem64Limit; + uint32_t VtdBarAddress; + uint32_t Slt2HfiBarAddress; // KNH Only +} STACK_RES; + +typedef struct { + uint8_t Valid; + uint8_t SocketID; // Socket ID of the IIO (0..3) + uint8_t BusBase; + uint8_t BusLimit; + uint16_t PciResourceIoBase; + uint16_t PciResourceIoLimit; + uint32_t IoApicBase; + uint32_t IoApicLimit; + uint32_t PciResourceMem32Base; + uint32_t PciResourceMem32Limit; + uint64_t PciResourceMem64Base; + uint64_t PciResourceMem64Limit; + STACK_RES StackRes[MAX_LOGIC_IIO_STACK]; + uint32_t RcBaseAddress; + IIO_DMI_PCIE_INFO PcieInfo; + uint8_t DmaDeviceCount; +} IIO_RESOURCE_INSTANCE; + +typedef struct { + uint16_t PlatGlobalIoBase; // Global IO Base + uint16_t PlatGlobalIoLimit; // Global IO Limit + uint32_t PlatGlobalMmiolBase; // Global Mmiol base + uint32_t PlatGlobalMmiolLimit; // Global Mmiol limit + uint64_t PlatGlobalMmiohBase; // Global Mmioh Base [43:0] + uint64_t PlatGlobalMmiohLimit; // Global Mmioh Limit [43:0] + QPI_CPU_DATA CpuQpiInfo[MAX_SOCKET]; // QPI related info per CPU + QPI_IIO_DATA IioQpiInfo[MAX_SOCKET]; // QPI related info per IIO + uint32_t MemTsegSize; + uint32_t MemIedSize; + uint64_t PciExpressBase; + uint32_t PciExpressSize; + uint32_t MemTolm; + IIO_RESOURCE_INSTANCE IIO_resource[MAX_SOCKET]; + uint8_t numofIIO; + uint8_t MaxBusNumber; + uint32_t packageBspApicID[MAX_SOCKET]; // This data array is valid only for SBSP, not for non-SBSP CPUs. + uint8_t EVMode; + uint8_t Pci64BitResourceAllocation; + uint8_t SkuPersonality[MAX_SOCKET]; + uint8_t VMDStackEnable[MaxIIO][MAX_IIO_STACK]; + uint16_t IoGranularity; + uint32_t MmiolGranularity; + UINT64_STRUCT MmiohGranularity; + uint8_t RemoteRequestThreshold; //5370389 + uint64_t softskuSocketPresentBitMap; // bitmap of Softsku sockets with CPUs present detected + uint32_t UboxMmioSize; + uint32_t MaxAddressBits; + uint32_t DmiReservedMmiolSize[MAX_SOCKET]; +} PLATFORM_DATA; + +typedef struct { + uint8_t CurrentUpiiLinkSpeed; // Current programmed UPI Link speed (Slow/Full speed mode) + uint8_t CurrentUpiLinkFrequency; // Current requested UPI Link frequency (in GT) + uint8_t OutKtiCpuSktHotPlugEn; // 0 - Disabled, 1 - Enabled for PM X2APIC + uint32_t OutKtiPerLinkL1En[MAX_SOCKET]; // output kti link enabled status for PM + uint8_t IsocEnable; + uint32_t meRequestedSize; // Size of the memory range requested by ME FW, in MB + uint32_t ieRequestedSize; // Size of the memory range requested by IE FW, in MB + uint8_t DmiVc1; + uint8_t DmiVcm; + uint32_t CpuPCPSInfo; + uint8_t LtsxEnable; + uint8_t MctpEn; + uint8_t cpuSubType; + uint8_t SystemRasType; + uint8_t numCpus; // 1,..4. Total number of CPU packages installed and detected (1..4)by QPI RC + uint16_t tolmLimit; + uint32_t tohmLimit; + RC_VERSION RcVersion; + BOOLEAN MsrTraceEnable; + uint8_t DdrXoverMode; // DDR 2.2 Mode + // For RAS + uint8_t bootMode; + uint8_t OutClusterOnDieEn; // Whether RC enabled COD support + uint8_t OutSncEn; + uint8_t OutNumOfCluster; + uint8_t imcEnabled[MAX_SOCKET][MAX_IMC]; + uint16_t LlcSizeReg; + uint8_t chEnabled[MAX_SOCKET][MAX_CH]; + uint8_t memNode[MC_MAX_NODE]; + uint8_t IoDcMode; + uint8_t DfxRstCplBitsEn; +} SYSTEM_STATUS; + +typedef struct { + PLATFORM_DATA PlatformData; + SYSTEM_STATUS SystemStatus; + uint32_t OemValue; +} IIO_UDS; +#pragma pack() + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h new file mode 100644 index 0000000000..6b0823cb51 --- /dev/null +++ b/src/vendorcode/intel/fsp/fsp2_0/cooperlake_sp/hob_memmap.h @@ -0,0 +1,109 @@ +/** +Copyright (c) 2019-2020, Intel Corporation. All rights reserved.
+ +Redistribution and use in source and binary forms, with or without modification, +are permitted provided that the following conditions are met: + +* Redistributions of source code must retain the above copyright notice, this + list of conditions and the following disclaimer. +* Redistributions in binary form must reproduce the above copyright notice, this + list of conditions and the following disclaimer in the documentation and/or + other materials provided with the distribution. +* Neither the name of Intel Corporation nor the names of its contributors may + be used to endorse or promote products derived from this software without + specific prior written permission. + + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF + THE POSSIBILITY OF SUCH DAMAGE. + +**/ + + +#ifndef _MEMORY_MAP_GUID_H_ +#define _MEMORY_MAP_GUID_H_ + +#define FSP_SYSTEM_MEMORYMAP_HOB_GUID { \ + 0x15, 0x00, 0x87, 0xf8, 0x94, 0x69, 0x98, 0x4b, 0x95, 0xa2, \ + 0xbd, 0x56, 0xda, 0x91, 0xc0, 0x7f \ + } + +#define MEMTYPE_1LM_MASK (1 << 0) +#define MEMTYPE_2LM_MASK (1 << 1) +#define MEMTYPE_VOLATILE_MASK (MEMTYPE_1LM_MASK | MEMTYPE_2LM_MASK) + +#define MAX_SAD_RULES 24 +#define MAX_DRAM_CLUSTERS 1 +#define MAX_IMC_PER_SOCKET 2 +#define MAX_SRAT_MEM_ENTRIES_PER_IMC 8 +#define MAX_ACPI_MEMORY_AFFINITY_COUNT ( \ + MAX_SOCKET * MAX_IMC_PER_SOCKET * MAX_SRAT_MEM_ENTRIES_PER_IMC \ + ) + +/* ACPI SRAT Memory Flags */ +#define SRAT_ACPI_MEMORY_ENABLED (1 << 0) +#define SRAT_ACPI_MEMORY_HOT_REMOVE_SUPPORTED (1 << 1) +#define SRAT_ACPI_MEMORY_NONVOLATILE (1 << 2) + +#define MEM_TYPE_RESERVED (1 << 8) +#define MEM_ADDR_64MB_SHIFT_BITS 26 + +// +// System Memory Map HOB information +// + +#pragma pack(1) + +typedef struct SystemMemoryMapElement { + // Type of this memory element; Bit0: 1LM Bit1: 2LM Bit2: PMEM Bit3: PMEM-cache + // Bit4: BLK Window Bit5: CSR/Mailbox/Ctrl region + UINT16 Type; + // Node ID of the HA Owning the memory + UINT8 NodeId; + // Socket Id of socket that has his memory - ONLY IN NUMA + UINT8 SocketId; + // Socket interleave bitmap, if more that on socket then ImcInterBitmap and ChInterBitmap are identical in all sockets + UINT8 SktInterBitmap; + // IMC interleave bitmap for this memory + UINT8 ImcInterBitmap; + // Bit map to denote which channels are interleaved per IMC eg: 111b - Ch 2,1 & 0 are interleaved; + // 011b denotes Ch1 & 0 are interleaved + UINT8 ChInterBitmap[MAX_IMC]; + // Base Address of the element in 64MB chunks + UINT32 BaseAddress; + // Size of this memory element in 64MB chunks + UINT32 ElementSize; +} SYSTEM_MEMORY_MAP_ELEMENT; + +/* NOTE - Reserved sizes need to be calibrated if any of the above #define values change */ +typedef struct SystemMemoryMapHob { + UINT8 reserved1[61]; + + UINT32 lowMemBase; // Mem base in 64MB units for below 4GB mem. + UINT32 lowMemSize; // Mem size in 64MB units for below 4GB mem. + UINT32 highMemBase; // Mem base in 64MB units for above 4GB mem. + UINT32 highMemSize; // Mem size in 64MB units for above 4GB mem. + UINT32 memSize; // Total physical memory size + UINT16 memFreq; // Mem Frequency + + UINT8 reserved2[61]; + + UINT8 numberEntries; // Number of Memory Map Elements + SYSTEM_MEMORY_MAP_ELEMENT Element[MAX_SOCKET * MAX_DRAM_CLUSTERS * MAX_SAD_RULES]; + + UINT8 reserved3[24409]; +} SYSTEM_MEMORY_MAP_HOB; + +#pragma pack() + +void soc_display_memmap_hob(void); + +#endif diff --git a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h index 23b4a04283..1568f2b7e9 100644 --- a/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h +++ b/src/vendorcode/intel/fsp/fsp2_0/skylake_sp/FsptUpd.h @@ -71,7 +71,7 @@ typedef struct { Output, refer to FSP Integration Guide for details 0:VPD-Style, 1:Enable Port80 Output[Default], 2:Disable Port80 Output **/ - UINT8 PcdFsptPort80RouteDisable; + UINT8 FsptPort80RouteDisable; /** Offset 0x0041 **/ From 4b3995c25fd57ec4e76215c55d905947c9da1429 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Thu, 28 May 2020 22:26:34 +0530 Subject: [PATCH 0042/1155] soc/intel/jasperlake: Update platform.asl to ASL2.0 syntax This change updates platform.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for wdoo. Change-Id: Ie55bcd9ac2ca746c046ebe05140b2ac291fb0459 Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/41861 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik Reviewed-by: Arthur Heymans --- src/soc/intel/jasperlake/acpi/platform.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/jasperlake/acpi/platform.asl b/src/soc/intel/jasperlake/acpi/platform.asl index 73458641fa..4b01aeb464 100644 --- a/src/soc/intel/jasperlake/acpi/platform.asl +++ b/src/soc/intel/jasperlake/acpi/platform.asl @@ -16,5 +16,5 @@ Method (_PIC, 1) { /* Remember the OS' IRQ routing choice. */ - Store (Arg0, PICM) + PICM = Arg0 } From be63cf46e50b69f14b23c49d1aec6c7d243ba0fe Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Thu, 28 May 2020 22:28:25 +0530 Subject: [PATCH 0043/1155] soc/intel/jasperlake: Update scs.asl to ASL2.0 syntax This change updates scs.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for wdoo. Change-Id: Ic1b5f3395a1ea8a3dd2ac6b109f9a5abe65d137f Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/41862 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Subrata Banik --- src/soc/intel/jasperlake/acpi/scs.asl | 24 ++++++++++++------------ 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/src/soc/intel/jasperlake/acpi/scs.asl b/src/soc/intel/jasperlake/acpi/scs.asl index bee862db72..508fb9bd41 100644 --- a/src/soc/intel/jasperlake/acpi/scs.asl +++ b/src/soc/intel/jasperlake/acpi/scs.asl @@ -37,22 +37,22 @@ Scope (\_SB.PCI0) { Method(_PS0, 0, Serialized) { Stall (50) // Sleep 50 us - Store(0, PGEN) // Disable PG + PGEN = 0 // Disable PG /* Clear register 0x1C20/0x4820 */ SCSC (PID_EMMC) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, TEMP) + PMCR = PMCR & 0xFFFC + TEMP = PMCR } Method(_PS3, 0, Serialized) { - Store(1, PGEN) // Enable PG + PGEN = 1 // Enable PG /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, TEMP) + PMCR = PMCR | 0x0003 + TEMP = PMCR } Device (CARD) @@ -90,23 +90,23 @@ Scope (\_SB.PCI0) { Method (_PS0, 0, Serialized) { - Store (0, PGEN) /* Disable PG */ + PGEN = 0 /* Disable PG */ /* Clear register 0x1C20/0x4820 */ SCSC (PID_SDX) /* Set Power State to D0 */ - And (PMCR, 0xFFFC, PMCR) - Store (PMCR, TEMP) + PMCR = PMCR & 0xFFFC + TEMP = PMCR } Method (_PS3, 0, Serialized) { - Store (1, PGEN) /* Enable PG */ + PGEN = 1 /* Enable PG */ /* Set Power State to D3 */ - Or (PMCR, 0x0003, PMCR) - Store (PMCR, TEMP) + PMCR = PMCR | 0x0003 + TEMP = PMCR } Device (CARD) From 226715877611ab2307945f872b1cf324a4d2bf64 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Thu, 28 May 2020 22:31:19 +0530 Subject: [PATCH 0044/1155] soc/intel/jasperlake: Update pch_hda.asl to ASL2.0 syntax This change updates pch_hda.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for wdoo. Change-Id: I8e965560518decbfafabe9ac06066d28d59240d0 Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/41863 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Subrata Banik --- src/soc/intel/jasperlake/acpi/pch_hda.asl | 16 +++++++--------- 1 file changed, 7 insertions(+), 9 deletions(-) diff --git a/src/soc/intel/jasperlake/acpi/pch_hda.asl b/src/soc/intel/jasperlake/acpi/pch_hda.asl index f292901b05..340c76528d 100644 --- a/src/soc/intel/jasperlake/acpi/pch_hda.asl +++ b/src/soc/intel/jasperlake/acpi/pch_hda.asl @@ -26,19 +26,17 @@ Device (HDAS) */ Method (_DSM, 4) { - If (LEqual (Arg0, ^UUID)) { + If (Arg0 == ^UUID) { /* * Function 0: Function Support Query * Returns a bitmask of functions supported. */ - If (LEqual (Arg2, Zero)) { + If (Arg2 == Zero) { /* * NHLT Query only supported for revision 1 and * if NHLT address and length are set in NVS. */ - If (LAnd (LEqual (Arg1, One), - LAnd (LNotEqual (NHLA, Zero), - LNotEqual (NHLL, Zero)))) { + If ((Arg1 == One) && ((NHLA != Zero) && (NHLL != Zero))) { Return (Buffer (One) { 0x03 }) } Else { Return (Buffer (One) { 0x01 }) @@ -52,14 +50,14 @@ Device (HDAS) * * Returns a pointer to NHLT table in memory. */ - If (LEqual (Arg2, One)) { + If (Arg2 == One) { CreateQWordField (NBUF, ^NHLT._MIN, NBAS) CreateQWordField (NBUF, ^NHLT._MAX, NMAS) CreateQWordField (NBUF, ^NHLT._LEN, NLEN) - Store (NHLA, NBAS) - Store (NHLA, NMAS) - Store (NHLL, NLEN) + NBAS = NHLA + NMAS = NHLA + NLEN = NHLL Return (NBUF) } From 8e6fa57e523c594d278afa34fe0cc00d3e82b606 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Thu, 28 May 2020 22:29:52 +0530 Subject: [PATCH 0045/1155] soc/intel/jasperlake: Update gpio_op.asl to ASL2.0 syntax This change updates gpio_op.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for wdoo. Change-Id: I3ec442ad85f408135642a112873231ce7d39524e Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/41864 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans Reviewed-by: Subrata Banik --- src/soc/intel/jasperlake/acpi/gpio_op.asl | 32 +++++++++++------------ 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/src/soc/intel/jasperlake/acpi/gpio_op.asl b/src/soc/intel/jasperlake/acpi/gpio_op.asl index 16e7690565..683686f3ca 100644 --- a/src/soc/intel/jasperlake/acpi/gpio_op.asl +++ b/src/soc/intel/jasperlake/acpi/gpio_op.asl @@ -11,7 +11,7 @@ Method (GRXS, 1, Serialized) { VAL0, 32 } - And (PAD_CFG0_RX_STATE, ShiftRight (VAL0, PAD_CFG0_RX_STATE_BIT), Local0) + Local0 = PAD_CFG0_RX_STATE & (VAL0 >> PAD_CFG0_RX_STATE_BIT) Return (Local0) } @@ -27,7 +27,7 @@ Method (GTXS, 1, Serialized) { VAL0, 32 } - And (PAD_CFG0_TX_STATE, VAL0, Local0) + Local0 = PAD_CFG0_TX_STATE & VAL0 Return (Local0) } @@ -43,7 +43,7 @@ Method (STXS, 1, Serialized) { VAL0, 32 } - Or (PAD_CFG0_TX_STATE, VAL0, VAL0) + VAL0 = PAD_CFG0_TX_STATE | VAL0 } /* @@ -57,7 +57,7 @@ Method (CTXS, 1, Serialized) { VAL0, 32 } - And (Not (PAD_CFG0_TX_STATE), VAL0, VAL0) + VAL0 = ~PAD_CFG0_TX_STATE & VAL0 } /* @@ -76,10 +76,10 @@ Method (GPMO, 2, Serialized) { VAL0, 32 } - Store (VAL0, Local0) - And (Not (PAD_CFG0_MODE_MASK), Local0, Local0) - And (ShiftLeft (Arg1, PAD_CFG0_MODE_SHIFT, Arg1), PAD_CFG0_MODE_MASK, Arg1) - Or (Local0, Arg1, VAL0) + Local0 = VAL0 + Local0 = ~PAD_CFG0_MODE_MASK & Local0 + Arg1 = (Arg1 <<= PAD_CFG0_MODE_SHIFT) & PAD_CFG0_MODE_MASK + VAL0 = Local0 | Arg1 } /* @@ -97,10 +97,10 @@ Method (GTXE, 2, Serialized) VAL0, 32 } - If (LEqual (Arg1, 1)) { - And (Not (PAD_CFG0_TX_DISABLE), VAL0, VAL0) - } ElseIf (LEqual (Arg1, 0)){ - Or (PAD_CFG0_TX_DISABLE, VAL0, VAL0) + If (Arg1 == 1) { + VAL0 = ~PAD_CFG0_TX_DISABLE & VAL0 + } ElseIf (Arg1 == 0){ + VAL0 = PAD_CFG0_TX_DISABLE | VAL0 } } @@ -119,9 +119,9 @@ Method (GRXE, 2, Serialized) VAL0, 32 } - If (LEqual (Arg1, 1)) { - And (Not (PAD_CFG0_RX_DISABLE), VAL0, VAL0) - } ElseIf (LEqual (Arg1, 0)){ - Or (PAD_CFG0_RX_DISABLE, VAL0, VAL0) + If (Arg1 == 1) { + VAL0 = ~PAD_CFG0_RX_DISABLE & VAL0 + } ElseIf (Arg1 == 0){ + VAL0 = PAD_CFG0_RX_DISABLE | VAL0 } } From 9eb85b1292182690874cb534b97ffa8a7f031077 Mon Sep 17 00:00:00 2001 From: V Sowmya Date: Thu, 28 May 2020 22:01:57 +0530 Subject: [PATCH 0046/1155] soc/intel/jasperlake: Update camera_clock_ctl.asl to ASL2.0 syntax This change updates camera_clock_ctl.asl to use ASL2.0 syntax. This increases the readability of the ASL code. TEST=Verified using --timeless option to abuild that the resulting coreboot.rom is same as without the ASL2.0 syntax changes for wdoo. Change-Id: I76ec29210ecdde728ce55531d2b6657be87ce9da Signed-off-by: V Sowmya Reviewed-on: https://review.coreboot.org/c/coreboot/+/41954 Tested-by: build bot (Jenkins) Reviewed-by: Subrata Banik --- src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl index 3d31502526..d76cb5dd0a 100644 --- a/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl +++ b/src/soc/intel/jasperlake/acpi/camera_clock_ctl.asl @@ -11,7 +11,7 @@ Scope (\_SB.PCI0) { /* IsCLK PCH base register for clock settings */ Name (ICKB, 0) - Store (PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1, ICKB) + ICKB = PCRB (PID_ISCLK) + R_ICLK_PCR_CAMERA1 /* * Arg0 : Clock Number From 1f572b9276ae3d20b37dbdb52e466ecfe5bbe06b Mon Sep 17 00:00:00 2001 From: Keith Hui Date: Sun, 10 May 2020 23:00:16 -0400 Subject: [PATCH 0047/1155] superio/nuvoton/nct6779d: Open some LDN config registers The porting of Asus P8Z77-M mainboard required changing certain Super I/O configuration registers that were ignored in devicetree.cb because they aren't listed as resources. Add the declaration so they can be changed. This change is nowhere near enough as the current structure is insufficient to allow changing configuration registers in the 0xE? range, which this board also needs. TEST=Changes to config regs 0xf4, 0xf5 in LDN 9 are reflected when inspected using superiotool -d. Change-Id: Ia31aafda3fa9423d516b5d839ef5265e8e8ccdd2 Signed-off-by: Keith Hui Reviewed-on: https://review.coreboot.org/c/coreboot/+/41226 Tested-by: build bot (Jenkins) Reviewed-by: Angel Pons Reviewed-by: Felix Held --- src/superio/nuvoton/nct6779d/superio.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/superio/nuvoton/nct6779d/superio.c b/src/superio/nuvoton/nct6779d/superio.c index 843857c7f3..ef50aa6c05 100644 --- a/src/superio/nuvoton/nct6779d/superio.c +++ b/src/superio/nuvoton/nct6779d/superio.c @@ -37,8 +37,8 @@ static struct pnp_info pnp_dev_info[] = { { NULL, NCT6779D_KBC, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_IRQ1, 0x0fff, 0x0fff, }, { NULL, NCT6779D_CIR, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, - { NULL, NCT6779D_ACPI}, - { NULL, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0, + { NULL, NCT6779D_ACPI, PNP_MSC2,}, + { NULL, NCT6779D_HWM_FPLED, PNP_IO0 | PNP_IO1 | PNP_IRQ0 | PNP_MSC0, 0x0ffe, 0x0ffe, }, { NULL, NCT6779D_WDT1}, { NULL, NCT6779D_CIRWKUP, PNP_IO0 | PNP_IRQ0, 0x0ff8, }, @@ -51,8 +51,8 @@ static struct pnp_info pnp_dev_info[] = { { NULL, NCT6779D_GPIO2}, { NULL, NCT6779D_GPIO3}, { NULL, NCT6779D_GPIO4}, - { NULL, NCT6779D_GPIO5}, - { NULL, NCT6779D_GPIO6}, + { NULL, NCT6779D_GPIO5, PNP_MSC4 | PNP_MSC5}, + { NULL, NCT6779D_GPIO6, PNP_MSC4 | PNP_MSC5}, { NULL, NCT6779D_GPIO7}, { NULL, NCT6779D_GPIO8}, }; From 061cd78a1aba4a31ee61dc6f6bafc3a35537cf3e Mon Sep 17 00:00:00 2001 From: Christian Walter Date: Sat, 23 May 2020 15:54:43 +0200 Subject: [PATCH 0048/1155] soc/intel/cannonlake: Add RP configuration settings Add RP configuration settings like Advanced Error Reporting(AER), Latency Tolerence Reporting (LTR), Max Payload and Active State Power Management (ASPM). Tested on CFL platform Change-Id: Ifaf0cc86ea412ce246723613f99908946d89ccb0 Signed-off-by: Christian Walter Reviewed-on: https://review.coreboot.org/c/coreboot/+/41679 Reviewed-by: Philipp Deppenwiese Tested-by: build bot (Jenkins) --- src/soc/intel/cannonlake/chip.h | 23 +++++++++++++++++++++++ src/soc/intel/cannonlake/fsp_params.c | 14 +++++++++++++- 2 files changed, 36 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/cannonlake/chip.h b/src/soc/intel/cannonlake/chip.h index a30f732ce3..4b48a2184a 100644 --- a/src/soc/intel/cannonlake/chip.h +++ b/src/soc/intel/cannonlake/chip.h @@ -181,6 +181,29 @@ struct soc_intel_cannonlake_config { /* Enable/Disable HotPlug support for Root Port */ uint8_t PcieRpHotPlug[CONFIG_MAX_ROOT_PORTS]; + /* + * Enable/Disable AER (Advanced Error Reporting) for Root Port + * 0: Disable AER + * 1: Enable AER + */ + uint8_t PcieRpAdvancedErrorReporting[CONFIG_MAX_ROOT_PORTS]; + + /* PCIE RP ASPM, ASPM support for the root port */ + enum { + AspmDefault, + AspmDisabled, + AspmL0s, + AspmL1, + AspmL0sL1, + AspmAutoConfig, + } PcieRpAspm[CONFIG_MAX_ROOT_PORTS]; + + /* PCIE RP Max Payload, Max Payload Size supported */ + enum { + RpMaxPayload_128, + RpMaxPayload_256, + } PcieRpMaxPayload[CONFIG_MAX_ROOT_PORTS]; + /* eMMC and SD */ uint8_t ScsEmmcHs400Enabled; /* Need to update DLL setting to get Emmc running at HS400 speed */ diff --git a/src/soc/intel/cannonlake/fsp_params.c b/src/soc/intel/cannonlake/fsp_params.c index 8788838c3f..a3b5588b77 100644 --- a/src/soc/intel/cannonlake/fsp_params.c +++ b/src/soc/intel/cannonlake/fsp_params.c @@ -319,10 +319,22 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) sizeof(config->PcieClkSrcUsage)); memcpy(params->PcieClkSrcClkReq, config->PcieClkSrcClkReq, sizeof(config->PcieClkSrcClkReq)); + + memcpy(params->PcieRpAdvancedErrorReporting, + config->PcieRpAdvancedErrorReporting, + sizeof(params->PcieRpAdvancedErrorReporting)); + memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(config->PcieRpLtrEnable)); memcpy(params->PcieRpHotPlug, config->PcieRpHotPlug, - sizeof(config->PcieRpHotPlug)); + sizeof(params->PcieRpHotPlug)); + + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) { + params->PcieRpMaxPayload[i] = config->PcieRpMaxPayload[i]; + if (config->PcieRpAspm[i]) + params->PcieRpAspm[i] = config->PcieRpAspm[i] - 1; + }; + /* eMMC and SD */ dev = pcidev_path_on_root(PCH_DEVFN_EMMC); From a21eae0441209d596fd39ad6f394136c87b9ff91 Mon Sep 17 00:00:00 2001 From: Matt Papageorge Date: Wed, 13 Nov 2019 17:00:12 -0600 Subject: [PATCH 0049/1155] soc/amd/picasso: Install AGESA ACPI tables AGESA FSP provides additional ACPI tables that are required. BUG=b:133337564, b:153675915 TEST=Boot trembyle to OS and dump ACPI tables. ACPI: added table 2/32, length now 44 ACPI: * MCFG ACPI: added table 3/32, length now 48 ACPI: * TPM2 TPM2 log created at 0xcc513000 ACPI: added table 4/32, length now 52 ACPI: * MADT ACPI: added table 5/32, length now 56 current = cc635af0 Searching for AGESA FSP ACPI Tables ACPI: * SSDT (AGESA). ACPI: added table 6/32, length now 60 ACPI: * CRAT (AGESA). ACPI: added table 7/32, length now 64 ACPI: * ALIB (AGESA). ACPI: added table 8/32, length now 68 ACPI: * IVRS (AGESA). ACPI: added table 9/32, length now 72 ACPI: * HPET ACPI: added table 10/32, length now 76 Copying initialized VBIOS image from 0x000c0000 ACPI: * VFCT at cc63ca30 ACPI: added table 11/32, length now 80 ACPI: done. ACPI tables: 102048 bytes. [ 0.042326] ACPI: Early table checksum verification disabled [ 0.048621] ACPI: RSDP 0x00000000000F0000 000024 (v02 COREv4) [ 0.055011] ACPI: XSDT 0x00000000CC6310E0 00007C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.064506] ACPI: FACP 0x00000000CC634850 000114 (v06 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.073998] ACPI: DSDT 0x00000000CC631280 0035CF (v02 COREv4 COREBOOT 00010001 INTL 20200110) [ 0.083488] ACPI: FACS 0x00000000CC631240 000040 [ 0.088623] ACPI: SSDT 0x00000000CC634970 00103D (v02 COREv4 COREBOOT 0000002A CORE 20200110) [ 0.098114] ACPI: MCFG 0x00000000CC6359B0 00003C (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.107606] ACPI: TPM2 0x00000000CC6359F0 00004C (v04 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.117100] ACPI: APIC 0x00000000CC635A40 0000A6 (v03 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.126592] ACPI: SSDT 0x00000000CC635AF0 00119C (v01 AMD AMD CPU 00000001 AMD 00000001) [ 0.136082] ACPI: CRAT 0x00000000CC636C90 000810 (v01 AMD AMD CRAT 00000001 AMD 00000001) [ 0.145573] ACPI: SSDT 0x00000000CC6374A0 005419 (v02 AMD AmdTable 00000002 MSFT 02000002) [ 0.155064] ACPI: IVRS 0x00000000CC63C8C0 000126 (v02 AMD AMD IVRS 00000001 AMD 00000000) [ 0.164556] ACPI: HPET 0x00000000CC63C9F0 000038 (v01 COREv4 COREBOOT 00000000 CORE 20200110) [ 0.174047] ACPI: VFCT 0x00000000CC63CA30 00D469 (v01 COREv4 COREBOOT 00000000 CORE 20200110) Signed-off-by: Matt Papageorge Signed-off-by: Raul E Rangel Change-Id: Ic1e87c0f7a7c736592dd8c5c6765ef9a37ed7a40 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41804 Reviewed-by: Aaron Durbin Reviewed-by: Felix Held Tested-by: build bot (Jenkins) --- src/soc/amd/picasso/Makefile.inc | 1 + src/soc/amd/picasso/agesa_acpi.c | 55 +++++++++++++++++++++++ src/soc/amd/picasso/chip.c | 2 + src/soc/amd/picasso/include/soc/acpi.h | 3 ++ src/vendorcode/amd/fsp/picasso/FspGuids.h | 16 +++++++ 5 files changed, 77 insertions(+) create mode 100644 src/soc/amd/picasso/agesa_acpi.c diff --git a/src/soc/amd/picasso/Makefile.inc b/src/soc/amd/picasso/Makefile.inc index d62ccda74d..ce0a7a8f43 100644 --- a/src/soc/amd/picasso/Makefile.inc +++ b/src/soc/amd/picasso/Makefile.inc @@ -47,6 +47,7 @@ ramstage-y += data_fabric_util.c ramstage-y += root_complex.c ramstage-y += mca.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c +ramstage-$(CONFIG_HAVE_ACPI_TABLES) += agesa_acpi.c ramstage-y += gpio.c ramstage-y += southbridge.c ramstage-y += pmutil.c diff --git a/src/soc/amd/picasso/agesa_acpi.c b/src/soc/amd/picasso/agesa_acpi.c new file mode 100644 index 0000000000..fb168a1f5a --- /dev/null +++ b/src/soc/amd/picasso/agesa_acpi.c @@ -0,0 +1,55 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include + +struct amd_fsp_acpi_hob_info { + uint32_t table_size_in_bytes; + uint8_t total_hobs_for_table; + uint8_t sequence_number; + uint16_t reserved; + uint16_t hob_payload[0xffc8]; +} __packed; + +static uintptr_t add_agesa_acpi_table(guid_t guid, const char *name, acpi_rsdp_t *rsdp, + uintptr_t current) +{ + const struct amd_fsp_acpi_hob_info *data; + void *table = (void *)current; + size_t hob_size; + + data = fsp_find_extension_hob_by_guid(guid.b, &hob_size); + if (!data) { + printk(BIOS_ERR, "AGESA %s ACPI table was not found.\n", name); + return current; + } + + printk(BIOS_INFO, "ACPI: * %s (AGESA).\n", name); + + memcpy(table, data->hob_payload, data->table_size_in_bytes); + + current += data->table_size_in_bytes; + acpi_add_table(rsdp, table); + current = acpi_align_current(current); + + return current; +} + +uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, + acpi_rsdp_t *rsdp) +{ + printk(BIOS_DEBUG, "Searching for AGESA FSP ACPI Tables\n"); + + current = add_agesa_acpi_table(AMD_FSP_ACPI_SSDT_HOB_GUID, "SSDT", rsdp, current); + current = add_agesa_acpi_table(AMD_FSP_ACPI_CRAT_HOB_GUID, "CRAT", rsdp, current); + current = add_agesa_acpi_table(AMD_FSP_ACPI_ALIB_HOB_GUID, "ALIB", rsdp, current); + current = add_agesa_acpi_table(AMD_FSP_ACPI_IVRS_HOB_GUID, "IVRS", rsdp, current); + + /* Add SRAT, MSCT, SLIT if needed in the future */ + + return current; +} diff --git a/src/soc/amd/picasso/chip.c b/src/soc/amd/picasso/chip.c index 4ea962f715..7c6e6fb967 100644 --- a/src/soc/amd/picasso/chip.c +++ b/src/soc/amd/picasso/chip.c @@ -143,6 +143,8 @@ static void enable_dev(struct device *dev) static void soc_init(void *chip_info) { + default_dev_ops_root.write_acpi_tables = agesa_write_acpi_tables; + fsp_silicon_init(acpi_is_wakeup_s3()); data_fabric_set_mmio_np(); diff --git a/src/soc/amd/picasso/include/soc/acpi.h b/src/soc/amd/picasso/include/soc/acpi.h index 6250f8682a..77f836cec2 100644 --- a/src/soc/amd/picasso/include/soc/acpi.h +++ b/src/soc/amd/picasso/include/soc/acpi.h @@ -14,6 +14,9 @@ unsigned long southbridge_write_acpi_tables(const struct device *device, void southbridge_inject_dsdt(const struct device *device); +uintptr_t agesa_write_acpi_tables(const struct device *device, uintptr_t current, + acpi_rsdp_t *rsdp); + const char *soc_acpi_name(const struct device *dev); #endif /* __SOC_PICASSO_ACPI_H__ */ diff --git a/src/vendorcode/amd/fsp/picasso/FspGuids.h b/src/vendorcode/amd/fsp/picasso/FspGuids.h index 24b185d4a8..64bf97c8f3 100644 --- a/src/vendorcode/amd/fsp/picasso/FspGuids.h +++ b/src/vendorcode/amd/fsp/picasso/FspGuids.h @@ -9,6 +9,22 @@ GUID_INIT(0x5fc7897a, 0x5aff, 0x4c61, \ 0xaa, 0x7a, 0xdd, 0xcf, 0xa9, 0x18, 0x43, 0x0c) +#define AMD_FSP_ACPI_SSDT_HOB_GUID \ + GUID_INIT(0x54445353, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_ACPI_CRAT_HOB_GUID \ + GUID_INIT(0x54415243, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_ACPI_ALIB_HOB_GUID \ + GUID_INIT(0x42494c41, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + +#define AMD_FSP_ACPI_IVRS_HOB_GUID \ + GUID_INIT(0x53525649, 0x4002, 0x403b, \ + 0x87, 0xE1, 0x3F, 0xEB, 0x13, 0xC5, 0x66, 0x9A) + #define PICASSO_MISC_DATA_HOB_GUID \ GUID_INIT(0xf2784616, 0xb9bf, 0x4e1e, \ 0x99, 0xe0, 0x96, 0x26, 0xda, 0x7e, 0xa5, 0xf5) From fa5eded303ac25c95ca4300ebfb4788c149bf2ab Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 28 May 2020 21:21:49 -0600 Subject: [PATCH 0050/1155] cpu/x86/mtrr: add helper for setting multiple MTRRs Introduce concept of var_mtrr_context object for tracking and assigning MTRR values. The algorithm is lifted from postcar_loader code, but it's generalized for different type of users: setting MSRs explicitly or deferring to a particular caller's desired actions. BUG=b:155426691,b:155322763 Change-Id: Ic03b4b617196f04071093bbba4cf28d23fa482d8 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/41849 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- src/cpu/x86/mtrr/earlymtrr.c | 67 ++++++++++++++++++++++++++++++++++++ src/include/cpu/x86/mtrr.h | 31 +++++++++++++++++ 2 files changed, 98 insertions(+) diff --git a/src/cpu/x86/mtrr/earlymtrr.c b/src/cpu/x86/mtrr/earlymtrr.c index 5a2ce554fa..879b8eff27 100644 --- a/src/cpu/x86/mtrr/earlymtrr.c +++ b/src/cpu/x86/mtrr/earlymtrr.c @@ -65,3 +65,70 @@ void clear_all_var_mtrr(void) wrmsr(MTRR_PHYS_BASE(i), mtrr); } } + +void var_mtrr_context_init(struct var_mtrr_context *ctx, void *arg) +{ + ctx->upper_mask = (1U << (cpu_phys_address_size() - 32)) - 1; + ctx->max_var_mtrrs = get_var_mtrr_count(); + ctx->used_var_mtrrs = 0; + ctx->arg = arg; +} + +int var_mtrr_set_with_cb(struct var_mtrr_context *ctx, uintptr_t addr, size_t size, + int type, void (*callback)(const struct var_mtrr_context *ctx, + uintptr_t base_addr, size_t size, + msr_t base, msr_t mask)) +{ + /* Utilize additional MTRRs if the specified size is greater than the + base address alignment. */ + while (size != 0) { + uint32_t addr_lsb; + uint32_t size_msb; + uint32_t mtrr_size; + msr_t base; + msr_t mask; + + if (ctx->used_var_mtrrs >= ctx->max_var_mtrrs) { + printk(BIOS_ERR, "No more variable MTRRs: %d\n", + ctx->max_var_mtrrs); + return -1; + } + + addr_lsb = fls(addr); + size_msb = fms(size); + + /* All MTRR entries need to have their base aligned to the mask + size. The maximum size is calculated by a function of the + min base bit set and maximum size bit set. */ + if (addr_lsb > size_msb) + mtrr_size = 1 << size_msb; + else + mtrr_size = 1 << addr_lsb; + + base.hi = (uint64_t)addr >> 32; + base.lo = addr | type; + mask.hi = ctx->upper_mask; + mask.lo = ~(mtrr_size - 1) | MTRR_PHYS_MASK_VALID; + callback(ctx, addr, mtrr_size, base, mask); + ctx->used_var_mtrrs++; + + size -= mtrr_size; + addr += mtrr_size; + } + + return 0; +} + +static void set_mtrr(const struct var_mtrr_context *ctx, uintptr_t base_addr, size_t size, + msr_t base, msr_t mask) +{ + int i = var_mtrr_context_current_mtrr(ctx); + + wrmsr(MTRR_PHYS_BASE(i), base); + wrmsr(MTRR_PHYS_MASK(i), mask); +} + +int var_mtrr_set(struct var_mtrr_context *ctx, uintptr_t addr, size_t size, int type) +{ + return var_mtrr_set_with_cb(ctx, addr, size, type, set_mtrr); +} diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index 301ea3052d..c1ee51accf 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -110,6 +110,37 @@ void clear_all_var_mtrr(void); asmlinkage void display_mtrrs(void); +/* Variable MTRR structure to help track and set MTRRs prior to ramstage. This + and the following APIs can be used to set up more complex MTRR solutions + instead of open coding get_free_var_mtrr() and set_var_mtrr() or for determining + a future solution, such as postcar_loader. */ +struct var_mtrr_context { + uint32_t upper_mask; + int max_var_mtrrs; + int used_var_mtrrs; + void *arg; /* optional callback parameter */ +}; + +/* Returns 0-relative MTRR from context. Use MTRR_PHYS_BASE|MASK macros for calculating + MSR address value. */ +static inline int var_mtrr_context_current_mtrr(const struct var_mtrr_context *ctx) +{ + return ctx->used_var_mtrrs; +} + +/* Initialize var_mtrr_context object. Assumes all variable MTRRs are not yet used. */ +void var_mtrr_context_init(struct var_mtrr_context *ctx, void *arg); +/* Allocate a variable mtrr base and mask, calling the provided callback for each MTRR + MSR base-mask pair needed to accommodate the address and size request. + Returns < 0 on error and 0 on success. */ +int var_mtrr_set_with_cb(struct var_mtrr_context *ctx, + uintptr_t addr, size_t size, int type, + void (*callback)(const struct var_mtrr_context *ctx, + uintptr_t base_addr, size_t size, + msr_t base, msr_t mask)); +/* Same as var_mtrr_set_with_cb() but just write the MSRs directly. */ +int var_mtrr_set(struct var_mtrr_context *ctx, uintptr_t addr, size_t size, int type); + /* * Set the MTRRs using the data on the stack from setup_stack_and_mtrrs. * Return a new top_of_stack value which removes the setup_stack_and_mtrrs data. From e1bf0656afaf4cdbb9759178b6b2af21baba42d7 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 28 May 2020 21:34:43 -0600 Subject: [PATCH 0051/1155] arch/x86/postcar_loader: utilize var_mtrr_context API Now that there is a generic solution in mtrr subsystem utilize the API. BUG=b:155426691,b:155322763 Change-Id: Ie349d5669808928c7470c99d25c57c784174b4e9 Signed-off-by: Aaron Durbin Reviewed-on: https://review.coreboot.org/c/coreboot/+/41850 Reviewed-by: Furquan Shaikh Tested-by: build bot (Jenkins) --- src/arch/x86/include/arch/romstage.h | 5 +-- src/arch/x86/postcar_loader.c | 65 ++++++++-------------------- src/drivers/amd/agesa/mtrr_fixme.c | 2 +- 3 files changed, 22 insertions(+), 50 deletions(-) diff --git a/src/arch/x86/include/arch/romstage.h b/src/arch/x86/include/arch/romstage.h index 8418366d6c..28d29bfdd8 100644 --- a/src/arch/x86/include/arch/romstage.h +++ b/src/arch/x86/include/arch/romstage.h @@ -5,6 +5,7 @@ #include #include +#include void mainboard_romstage_entry(void); @@ -16,10 +17,8 @@ void mainboard_romstage_entry(void); struct postcar_frame { uintptr_t stack; - uint32_t upper_mask; - int max_var_mtrrs; - int num_var_mtrrs; int skip_common_mtrr; + struct var_mtrr_context ctx; }; /* diff --git a/src/arch/x86/postcar_loader.c b/src/arch/x86/postcar_loader.c index 58c6db92e7..084384e58a 100644 --- a/src/arch/x86/postcar_loader.c +++ b/src/arch/x86/postcar_loader.c @@ -26,12 +26,7 @@ static inline void stack_push(struct postcar_frame *pcf, uint32_t val) static void postcar_frame_prepare(struct postcar_frame *pcf) { - msr_t msr; - msr = rdmsr(MTRR_CAP_MSR); - - pcf->upper_mask = (1 << (cpu_phys_address_size() - 32)) - 1; - pcf->max_var_mtrrs = msr.lo & MTRR_CAP_VCNT; - pcf->num_var_mtrrs = 0; + var_mtrr_context_init(&pcf->ctx, pcf); } int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size) @@ -60,47 +55,25 @@ int postcar_frame_init(struct postcar_frame *pcf, size_t stack_size) return 0; } +static void postcar_var_mtrr_set(const struct var_mtrr_context *ctx, + uintptr_t addr, size_t size, + msr_t base, msr_t mask) +{ + struct postcar_frame *pcf = ctx->arg; + + printk(BIOS_DEBUG, "MTRR Range: Start=%lx End=%lx (Size %zx)\n", + addr, addr + size, size); + + stack_push(pcf, mask.hi); + stack_push(pcf, mask.lo); + stack_push(pcf, base.hi); + stack_push(pcf, base.lo); +} + void postcar_frame_add_mtrr(struct postcar_frame *pcf, uintptr_t addr, size_t size, int type) { - /* - * Utilize additional MTRRs if the specified size is greater than the - * base address alignment. - */ - while (size != 0) { - uint32_t addr_lsb; - uint32_t size_msb; - uint32_t mtrr_size; - - if (pcf->num_var_mtrrs >= pcf->max_var_mtrrs) { - printk(BIOS_ERR, "No more variable MTRRs: %d\n", - pcf->max_var_mtrrs); - return; - } - - addr_lsb = fls(addr); - size_msb = fms(size); - - /* All MTRR entries need to have their base aligned to the mask - * size. The maximum size is calculated by a function of the - * min base bit set and maximum size bit set. */ - if (addr_lsb > size_msb) - mtrr_size = 1 << size_msb; - else - mtrr_size = 1 << addr_lsb; - - printk(BIOS_DEBUG, "MTRR Range: Start=%lx End=%lx (Size %x)\n", - addr, addr + mtrr_size, mtrr_size); - - stack_push(pcf, pcf->upper_mask); - stack_push(pcf, ~(mtrr_size - 1) | MTRR_PHYS_MASK_VALID); - stack_push(pcf, 0); - stack_push(pcf, addr | type); - pcf->num_var_mtrrs++; - - size -= mtrr_size; - addr += mtrr_size; - } + var_mtrr_set_with_cb(&pcf->ctx, addr, size, type, postcar_var_mtrr_set); } void postcar_frame_add_romcache(struct postcar_frame *pcf, int type) @@ -140,8 +113,8 @@ static void postcar_commit_mtrrs(struct postcar_frame *pcf) * Place the number of used variable MTRRs on stack then max number * of variable MTRRs supported in the system. */ - stack_push(pcf, pcf->num_var_mtrrs); - stack_push(pcf, pcf->max_var_mtrrs); + stack_push(pcf, pcf->ctx.used_var_mtrrs); + stack_push(pcf, pcf->ctx.max_var_mtrrs); } static void finalize_load(uintptr_t *stack_top_ptr, uintptr_t stack_top) diff --git a/src/drivers/amd/agesa/mtrr_fixme.c b/src/drivers/amd/agesa/mtrr_fixme.c index 0a4f29a30d..a880ce7e01 100644 --- a/src/drivers/amd/agesa/mtrr_fixme.c +++ b/src/drivers/amd/agesa/mtrr_fixme.c @@ -59,7 +59,7 @@ void recover_postcar_frame(struct postcar_frame *pcf, int s3resume) /* Replicate non-UC MTRRs as left behind by AGESA. */ - for (i = 0; i < pcf->max_var_mtrrs; i++) { + for (i = 0; i < pcf->ctx.max_var_mtrrs; i++) { mask = rdmsr(MTRR_PHYS_MASK(i)); base = rdmsr(MTRR_PHYS_BASE(i)); u32 size = ~(mask.lo & ~0xfff) + 1; From 1ebbb165efe71e83fbf19a9ce6c4bf14e2448d81 Mon Sep 17 00:00:00 2001 From: Aaron Durbin Date: Thu, 28 May 2020 10:17:34 -0600 Subject: [PATCH 0052/1155] cpu/x86/mtrr: add x86_setup_mtrrs_with_detect_no_above_4gb() There's not a function that is the equivalent to x86_setup_mtrrs_with_detect() but not solving for above 4GiB. Provide x86_setup_mtrrs_with_detect_no_above_4gb() which is the equivalent to x86_setup_mtrrs_with_detect() but instructs the MTRR solver to not take into account memory above 4GiB. BUG=b:155426691 Signed-off-by: Aaron Durbin Change-Id: Ia1b5d67d6f139aaa929e03ddbc394d57dfb949e0 Reviewed-on: https://review.coreboot.org/c/coreboot/+/41897 Reviewed-by: Furquan Shaikh Reviewed-by: Paul Menzel Tested-by: build bot (Jenkins) --- src/cpu/x86/mtrr/mtrr.c | 18 +++++++++++++++--- src/include/cpu/x86/mtrr.h | 1 + 2 files changed, 16 insertions(+), 3 deletions(-) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index 1f37659503..77525a7907 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -774,7 +774,7 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb) commit_var_mtrrs(sol); } -void x86_setup_mtrrs(void) +static void _x86_setup_mtrrs(unsigned int above4gb) { int address_size; @@ -782,14 +782,26 @@ void x86_setup_mtrrs(void) address_size = cpu_phys_address_size(); printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size); + x86_setup_var_mtrrs(address_size, above4gb); +} + +void x86_setup_mtrrs(void) +{ /* Always handle addresses above 4GiB. */ - x86_setup_var_mtrrs(address_size, 1); + _x86_setup_mtrrs(1); } void x86_setup_mtrrs_with_detect(void) { detect_var_mtrrs(); - x86_setup_mtrrs(); + /* Always handle addresses above 4GiB. */ + _x86_setup_mtrrs(1); +} + +void x86_setup_mtrrs_with_detect_no_above_4gb(void) +{ + detect_var_mtrrs(); + _x86_setup_mtrrs(0); } void x86_mtrr_check(void) diff --git a/src/include/cpu/x86/mtrr.h b/src/include/cpu/x86/mtrr.h index c1ee51accf..412330449f 100644 --- a/src/include/cpu/x86/mtrr.h +++ b/src/include/cpu/x86/mtrr.h @@ -77,6 +77,7 @@ void x86_setup_mtrrs(void); * it always dynamically detects the number of variable MTRRs available. */ void x86_setup_mtrrs_with_detect(void); +void x86_setup_mtrrs_with_detect_no_above_4gb(void); /* * x86_setup_var_mtrrs() parameters: * address_bits - number of physical address bits supported by cpu From 36e6c6f8d2b63428b0829ff615903715766b8c20 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Sat, 9 May 2020 19:20:10 -0700 Subject: [PATCH 0053/1155] fw_config: Add firmware configuration interface This change introduces a new top-level interface for interacting with a bitmask providing firmware configuration information. This is motivated by Chromebook mainboards that need to support multiple different configurations at runtime with the same BIOS. In these devices the Embedded Controller provides a bitmask that can be broken down into different fields and each field can then be broken down into different options. The firmware configuration value could also be stored in CBFS and this interface will look in CBFS first to allow the Embedded Controller value to be overridden. The firmware configuration interface is intended to easily integrate into devicetree.cb and lead to less code duplication for new mainboards that make use of this feature. BUG=b:147462631 TEST=this provides a new interface that is tested in subsequent commits Change-Id: I1e889c235a81545e2ec0e3a34dfa750ac828a330 Signed-off-by: Duncan Laurie Reviewed-on: https://review.coreboot.org/c/coreboot/+/41209 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- Documentation/lib/fw_config.md | 353 +++++++++++++++++++++++++++++++++ Documentation/lib/index.md | 2 +- src/Kconfig | 27 +++ src/include/device/device.h | 4 + src/include/fw_config.h | 53 +++++ src/lib/Makefile.inc | 5 + src/lib/fw_config.c | 94 +++++++++ 7 files changed, 537 insertions(+), 1 deletion(-) create mode 100644 Documentation/lib/fw_config.md create mode 100644 src/include/fw_config.h create mode 100644 src/lib/fw_config.c diff --git a/Documentation/lib/fw_config.md b/Documentation/lib/fw_config.md new file mode 100644 index 0000000000..63a56dcd7b --- /dev/null +++ b/Documentation/lib/fw_config.md @@ -0,0 +1,353 @@ +# Firmware Configuration Interface in coreboot + +## Motivation + +The firmware configuration interface in coreboot is designed to support a wide variety of +configuration options in that are dictated by the hardware at runtime. This allows a single +BIOS image to be used across a wide variety of devices which may have key differences but are +otherwise similar enough to use the same coreboot build target. + +The initial implementation is designed to take advantage of a bitmask returned by the Embedded +Controller on Google Chrome OS devices which allows the manufacturer to use the same firmware +image across multiple devices by selecting various options at runtime. See the Chromium OS +[Firmware Config][1] documentation for more information. + +This firmware configuration interface differs from the CMOS option interface in that this +bitmask value is not intended as a user-configurable setting as the configuration values must +match the actual hardware. In the case where a user was to swap their hardware this value +would need to be updated or overridden. + +## Device Presence + +One common example of why a firmware configuration interface is important is determining if a +device is present in the system. With some bus topologies and hardware mechanisms it is +possible to probe and enumerate this at runtime: + +- PCI is a self-discoverable bus and is very easy to handle. +- I2C devices can often be probed with a combination of bus and address. +- The use of GPIOs with external strap to ground or different voltages can be used to detect +presence of a device. + +However there are several cases where this is insufficient: + +- I2C peripherals that require different drivers but have the same bus address cannot be +uniquely identified at runtime. +- A mainboard may be designed with multiple daughter board combinations which contain devices +and configurations that cannot be detected. +- While presence detect GPIOs are a convenient way for a single device presence, they are +unable to distinguish between different devices so it can require a large number of GPIOs to +support relatively few options. + +This presence detection can impact different stages of boot: + +### ACPI + +Devices that are not present should not provide an ACPI device indicating that they are +present or the operating system may not be able to handle it correctly. + +The ACPI devices are largely driven by chips defined in the mainboard `devicetree.cb` and +the variant overridetree.cb. This means it is important to be able to specify when a device +is present or not directly in `devicetree.cb` itself. Otherwise each mainboard needs custom +code to parse the tree and disable unused devices. + +### GPIO + +GPIOs with multiple functions may need to be configured correctly depending on the attached +device. Given the wide variety of GPIO configuration possibilities it is not feasible to +specify all combinations directly in `devicetree.cb` and it is best left to code provided by +the mainboard. + +### FSP UPD + +Enabling and disabling devices may require altering FSP UPD values that are provided to the +various stages of FSP. These options are also not easy to specify multiple times for +different configurations in `devicetree.cb` and can be provided by the mainboard as code. + +## Firmware Configuration Interface + +The firmware configuration interface can be enabled by selecting `CONFIG_FW_CONFIG` and also +providing a source for the value by defining an additional Kconfig option defined below. + +If the firmware configuration interface is disabled via Kconfig then all probe attempts will +return true. + +## Firmware Configuration Value + +The 32bit value used as the firmware configuration bitmask is meant to be determined at runtime +but could also be defined at compile time if needed. + +There are two supported sources for providing this information to coreboot. + +### CBFS + +The value can be provided with a 32bit raw value in CBFS that is read by coreboot. The value +can be set at build time but also adjusted in an existing image with `cbfstool`. + +To enable this select the `CONFIG_FW_CONFIG_CBFS` option in the build configuration and add a +raw 32bit value to CBFS with the name of the current prefix at `CONFIG_FW_PREFIX/fw_config`. + +When `fw_config_probe_device()` or `fw_config_probe()` is called it will look for the specified +file in CBFS use the value it contains when matching fields and options. + +### Embedded Controller + +Google Chrome OS devices support an Embedded Controller interface for reading and writing the +firmware configuration value, along with other board-specific information. It is possible for +coreboot to read this value at boot on systems that support this feature. + +This option is selected by default for the mainboards that use it with +`CONFIG_FW_CONFIG_CHROME_EC_CBI` and it is not typically necessary to adjust the value. It is +possible by enabling the CBFS source and coreboot will look in CBFS first for a valid value +before asking the embedded controller. + +It is also possible to adjust the value in the embedded controller *(after disabling write +protection)* with the `ectool` command in a Chrome OS environment. + +For more information on the firmware configuration field on Chrome OS devices see the Chromium +documentation for [Firmware Config][1] and [Board Info][2]. + +[1]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/firmware_config.md +[2]: http://chromium.googlesource.com/chromiumos/docs/+/master/design_docs/cros_board_info.md + +## Firmware Configuration Table + +The firmware configuration table itself is defined in the mainboard `devicetree.cb` with +special tokens for defining fields and options. + +The table itself is enclosed in a `fw_config` token and terminated with `end` and it contains +a mix of field and option definitions. + +Each field is defined by providing the field name and the start and end bit marking the exact +location in the bitmask. Field names must be at least three characters long in order to +satisfy the sconfig parser requirements and they must be unique with non-overlapping masks. + + field [option...] end + +For single-bit fields only one number is needed: + + field [option...] end + +Each `field` definition starts a new block that can be composed of zero or more field options, +and it is terminated with `end`. + +Inside the field block the options can be defined by providing the option name and the field +value that this option represents when the bit offsets are used to apply a mask and shift. +Option names must also be at least three characters for the sconfig parser. + + option + +It is possible for there to be multiple `fw_config` blocks and for subsequent `field` blocks +to add additional `option` definitions to the existing field. These subsequent definitions +should not provide the field bitmask as it has already been defined earlier in the file and +this is just matching an existing field by name. + + field [option...] end + +This allows a baseboard to define the major fields and options in `devicetree.cb` and a board +variant to add specific options to fields in or define new fields in the unused bitmask in +`overridetree.cb`. + +It is not possible to redefine a field mask or override the value of an existing option this +way, only to add new options to a field or new fields to the table. + +### Firmware Configuration Table Example + +In this example a baseboard defines a simple boolean feature that is enabled or disabled +depending on the value of bit 0, and a field at bits 1-2 that indicates which daughter board +is attached. + +The baseboard itself defines one daughter board and the variant adds two more possibilities. +This way each variant can support multiple possible daughter boards in addition to the one +that was defined by the baseboard. + +#### devicetree.cb + + fw_config + field FEATURE 0 + option DISABLED 0 + option ENABLED 1 + end + field DAUGHTER_BOARD 1 2 + option NONE 0 + option REFERENCE_DB 1 + end + end + +#### overridetree.cb + + fw_config + field DAUGHTER_BOARD + option VARIANT_DB_ONE 2 + option VARIANT_DB_TWO 3 + end + end + +The result of this table defined in `devicetree.cb` is a list of constants that can be used +to check if fields match the firmware configuration options determined at runtime with a +simple check of the field mask and the option value. + +#### static.h + +```c +/* field: FEATURE */ +#define FW_CONFIG_FIELD_FEATURE_NAME "FEATURE" +#define FW_CONFIG_FIELD_FEATURE_MASK 0x00000001 +#define FW_CONFIG_FIELD_FEATURE_OPTION_DISABLED_NAME "DISABLED" +#define FW_CONFIG_FIELD_FEATURE_OPTION_DISABLED_VALUE 0x00000000 +#define FW_CONFIG_FIELD_FEATURE_OPTION_ENABLED_NAME "ENABLED" +#define FW_CONFIG_FIELD_FEATURE_OPTION_ENABLED_VALUE 0x00000001 + +/* field: DAUGHTER_BOARD */ +#define FW_CONFIG_FIELD_DAUGHTER_BOARD_NAME "DAUGHTER_BOARD" +#define FW_CONFIG_FIELD_DAUGHTER_BOARD_MASK 0x00000006 +#define FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_NONE_NAME "NONE" +#define FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_NONE_VALUE 0x00000000 +#define FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_REFERENCE_DB_NAME "REFERENCE_DB" +#define FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_REFERENCE_DB_VALUE 0x00000002 +#define FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_ONE_NAME "VARIANT_DB_ONE" +#define FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_ONE_VALUE 0x00000004 +#define FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_TWO_NAME "VARIANT_DB_TWO" +#define FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_TWO_VALUE 0x00000006 +``` + +## Device Probing + +One use of the firmware configuration interface in devicetree is to allow device probing to be +specified directly with the devices themselves. A new `probe` token is introduced to allow a +device to be probed by field and option name. Multiple `probe` entries may be present for +each device and any successful probe will consider the device to be present. + +### Probing Example + +Continuing with the previous example this device would be considered present if the field +`DAUGHTER_BOARD` was set to either `VARIANT_DB_ONE` or `VARIANT_DB_TWO`: + +#### overridetree.cb + + chip drivers/generic/example + device generic 0 on + probe DAUGHTER_BOARD VARIANT_DB_ONE + probe DAUGHTER_BOARD VARIANT_DB_TWO + end + end + +If the field were set to any other option, including `NONE` and `REFERENCE_DB` and any +undefined value then the device would be disabled. + +### Probe Overrides + +When a device is declared with a probe in the baseboard `devicetree.cb` and the same device +is also present in the `overridetree.cb` then the probing information from the baseboard +is discarded and the override device must provide all necessary probing information. + +In this example a device is listed in the baseboard with `DAUGHTER_BOARD` field probing for +`REFERENCE_DB` as a field option, It is also defined as an override device with the field +probing for the `VARIANT_DB_ONE` option instead. + +In this case only the probe listed in the override is checked and a field option of +`REFERENCE_DB` will not mark this device present. If both options are desired then the +override device must list both. This allows an override device to remove a probe entry that +was defined in the baseboard. + +#### devicetree.cb + + chip drivers/generic/example + device generic 0 on + probe DAUGHTER_BOARD REFERENCE_DB + end + end + +#### overridetree.cb + + chip drivers/generic/example + device generic 0 on + probe DAUGHTER_BOARD VARIANT_DB_ONE + end + end + +### Automatic Device Probing + +At boot time the firmware configuration interface will walk the device tree and apply any +probe entries that were defined in `devicetree.cb`. This probing takes effect before the +`BS_DEV_ENUMERATE` step during the boot state machine in ramstage. + +Devices that have a probe list but do do not find a match are disabled by setting +`dev->enabled = 0` but the chip `enable_dev()` and device `enable()` handlers will still +be executed to allow any device disable code to execute. + +The result of this probe definition is to provide an array of structures describing each +field and option to check. + +#### fw_config.h + +```c +/** + * struct fw_config - Firmware configuration field and option. + * @field_name: Name of the field that this option belongs to. + * @option_name: Name of the option within this field. + * @mask: Bitmask of the field. + * @value: Value of the option within the mask. + */ +struct fw_config { + const char *field_name; + const char *option_name; + uint32_t mask; + uint32_t value; +}; +``` + +#### static.c + +```c +STORAGE struct fw_config __devN_probe_list[] = { + { + .field_name = FW_CONFIG_FIELD_DAUGHTER_BOARD_NAME, + .option_name = FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_ONE_NAME, + .mask = FW_CONFIG_FIELD_DAUGHTER_BOARD_MASK, + .value = FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_ONE_VALUE + }, + { + .field_name = FW_CONFIG_FIELD_DAUGHTER_BOARD_NAME, + .option_name = FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_TWO_NAME, + .mask = FW_CONFIG_FIELD_DAUGHTER_BOARD_MASK, + .value = FW_CONFIG_FIELD_DAUGHTER_BOARD_OPTION_VARIANT_DB_TWO_VALUE + }, + { } +}; +``` + +### Runtime Probing + +The device driver probing allows for seamless integration with the mainboard but it is only +effective in ramstage and for specific devices declared in devicetree.cb. There are other +situations where code may need to probe or check the value of a field in romstage or at other +points in ramstage. For this reason it is also possible to use the firmware configuration +interface directly. + +```c +/** + * fw_config_probe() - Check if field and option matches. + * @match: Structure containing field and option to probe. + * + * Return %true if match is found, %false if match is not found. + */ +bool fw_config_probe(const struct fw_config *match); +``` + +The argument provided to this function can be created from a macro for easy use: + + FW_CONFIG(field, option) + +This example has a mainboard check if a feature is disabled and set an FSP UPD before memory +training. This example expects that the default value of this `register` is set to `true` in +`devicetree.cb` and this code is disabling that feature before FSP is executed. + +```c +#include + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + if (fw_config_probe_one(FW_CONFIG(FEATURE, DISABLED)) + mupd->ExampleFeature = false; +} +``` diff --git a/Documentation/lib/index.md b/Documentation/lib/index.md index 99b8061325..d64b4e999e 100644 --- a/Documentation/lib/index.md +++ b/Documentation/lib/index.md @@ -3,7 +3,7 @@ This section contains documentation about coreboot internal technical information and libraries. -## Structure and layout - [Flashmap and Flashmap Descriptor](flashmap.md) - [ABI data consumption](abi-data-consumption.md) - [Timestamps](timestamp.md) +- [Firmware Configuration Interface](fw_config.md) diff --git a/src/Kconfig b/src/Kconfig index 2a2a144235..b96d51f526 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -323,6 +323,33 @@ config BOOTSPLASH_FILE The path and filename of the file to use as graphical bootsplash screen. The file format has to be jpg. +config FW_CONFIG + bool "Firmware Configuration Probing" + default n + help + Enable support for probing devices with fw_config. This is a simple + bitmask broken into fields and options for probing. + +config FW_CONFIG_SOURCE_CBFS + bool "Obtain Firmware Configuration value from CBFS" + depends on FW_CONFIG + default n + help + With this option enabled coreboot will look for the 32bit firmware + configuration value in CBFS at the selected prefix with the file name + "fw_config". This option will override other sources and allow the + local image to preempt the mainboard selected source. + +config FW_CONFIG_SOURCE_CHROMEEC_CBI + bool "Obtain Firmware Configuration value from Google Chrome EC CBI" + depends on FW_CONFIG && EC_GOOGLE_CHROMEEC + default n + help + This option tells coreboot to read the firmware configuration value + from the Google Chrome Embedded Controller CBI interface. This source + is not tried if FW_CONFIG_SOURCE_CBFS is enabled and the value was + found in CBFS. + config HAVE_RAMPAYLOAD bool diff --git a/src/include/device/device.h b/src/include/device/device.h index 46efbfe679..082dcbb4d3 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -8,6 +8,7 @@ #include #include +struct fw_config; struct device; struct pci_operations; struct i2c_bus_operations; @@ -147,6 +148,9 @@ struct device { #endif #endif DEVTREE_CONST void *chip_info; + + /* Zero-terminated array of fields and options to probe. */ + DEVTREE_CONST struct fw_config *probe_list; }; /** diff --git a/src/include/fw_config.h b/src/include/fw_config.h new file mode 100644 index 0000000000..d41afd6c5d --- /dev/null +++ b/src/include/fw_config.h @@ -0,0 +1,53 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __FW_CONFIG__ +#define __FW_CONFIG__ + +#include +#include /* Provides fw_config definitions from devicetree.cb */ +#include +#include + +/** + * struct fw_config - Firmware configuration field and option. + * @field_name: Name of the field that this option belongs to. + * @option_name: Name of the option within this field. + * @mask: Bitmask of the field. + * @value: Value of the option within the mask. + */ +struct fw_config { + const char *field_name; + const char *option_name; + uint32_t mask; + uint32_t value; +}; + +/* Generate a pointer to a compound literal of the fw_config structure. */ +#define FW_CONFIG(__field, __option) (&(const struct fw_config) { \ + .field_name = FW_CONFIG_FIELD_##__field##_NAME, \ + .option_name = FW_CONFIG_FIELD_##__field##_OPTION_##__option##_NAME, \ + .mask = FW_CONFIG_FIELD_##__field##_MASK, \ + .value = FW_CONFIG_FIELD_##__field##_OPTION_##__option##_VALUE \ +}) + +#if CONFIG(FW_CONFIG) + +/** + * fw_config_probe() - Check if field and option matches. + * @match: Structure containing field and option to probe. + * + * Return %true if match is found, %false if match is not found. + */ +bool fw_config_probe(const struct fw_config *match); + +#else + +static inline bool fw_config_probe(const struct fw_config *match) +{ + /* Always return true when probing with disabled fw_config. */ + return true; +} + +#endif /* CONFIG(FW_CONFIG) */ + +#endif /* __FW_CONFIG__ */ diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 6511c0c328..e0003bd1cf 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -159,6 +159,11 @@ romstage-y += hexdump.c verstage-y += hexdump.c smm-y += hexdump.c +bootblock-$(CONFIG_FW_CONFIG) += fw_config.c +verstage-$(CONFIG_FW_CONFIG) += fw_config.c +romstage-$(CONFIG_FW_CONFIG) += fw_config.c +ramstage-$(CONFIG_FW_CONFIG) += fw_config.c + bootblock-$(CONFIG_ESPI_DEBUG) += espi_debug.c verstage-$(CONFIG_ESPI_DEBUG) += espi_debug.c romstage-$(CONFIG_ESPI_DEBUG) += espi_debug.c diff --git a/src/lib/fw_config.c b/src/lib/fw_config.c new file mode 100644 index 0000000000..e97cfdc72a --- /dev/null +++ b/src/lib/fw_config.c @@ -0,0 +1,94 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include +#include +#include +#include +#include +#include +#include +#include + +/** + * fw_config_get() - Provide firmware configuration value. + * + * Return 32bit firmware configuration value determined for the system. + */ +static uint32_t fw_config_get(void) +{ + static uint32_t fw_config_value; + static bool fw_config_value_initialized; + + /* Nothing to prepare if setup is already done. */ + if (fw_config_value_initialized) + return fw_config_value; + fw_config_value_initialized = true; + + /* Look in CBFS to allow override of value. */ + if (CONFIG(FW_CONFIG_SOURCE_CBFS)) { + if (cbfs_boot_load_file(CONFIG_CBFS_PREFIX "/fw_config", + &fw_config_value, sizeof(fw_config_value), + CBFS_TYPE_RAW) != sizeof(fw_config_value)) { + printk(BIOS_WARNING, "%s: Could not get fw_config from CBFS\n", + __func__); + fw_config_value = 0; + } else { + printk(BIOS_INFO, "FW_CONFIG value from CBFS is 0x%08x\n", + fw_config_value); + return fw_config_value; + } + } + + /* Read the value from EC CBI. */ + if (CONFIG(FW_CONFIG_SOURCE_CHROMEEC_CBI)) { + if (google_chromeec_cbi_get_fw_config(&fw_config_value)) + printk(BIOS_WARNING, "%s: Could not get fw_config from EC\n", __func__); + } + + printk(BIOS_INFO, "FW_CONFIG value is 0x%08x\n", fw_config_value); + return fw_config_value; +} + +bool fw_config_probe(const struct fw_config *match) +{ + /* Compare to system value. */ + if ((fw_config_get() & match->mask) == match->value) { + if (match->field_name && match->option_name) + printk(BIOS_INFO, "fw_config match found: %s=%s\n", match->field_name, + match->option_name); + else + printk(BIOS_INFO, "fw_config match found: mask=0x%08x value=0x%08x\n", + match->mask, match->value); + return true; + } + + return false; +} + +#if ENV_RAMSTAGE +static void fw_config_init(void *unused) +{ + struct device *dev; + + for (dev = all_devices; dev; dev = dev->next) { + const struct fw_config *probe; + bool match = false; + + if (!dev->probe_list) + continue; + + for (probe = dev->probe_list; probe && probe->mask != 0; probe++) { + if (fw_config_probe(probe)) { + match = true; + break; + } + } + + if (!match) { + printk(BIOS_INFO, "%s disabled by fw_config\n", dev_path(dev)); + dev->enabled = 0; + } + } +} +BOOT_STATE_INIT_ENTRY(BS_DEV_ENUMERATE, BS_ON_ENTRY, fw_config_init, NULL); +#endif From 47b7b3402b0864e5c782705bc24e4bf143c3c7f3 Mon Sep 17 00:00:00 2001 From: Duncan Laurie Date: Fri, 15 May 2020 15:39:08 -0700 Subject: [PATCH 0054/1155] sconfig: Add support for firmware configuration This change adds support to sconfig for generating the firmware configuration field and option definitions in devicetree.cb. In addition these fields and options can be used to probe for a device and have that device be disabled if it is not found at boot time. New tokens: fw_config: top level token, table can be defined before chips field: define field in the mask with the start and end bits option: define option in a field with the value of the field probe: indicate that a device should probe by field and option Example: fw_config field FEATURE 0 0 option DISABLE 0 option ENABLE 1 end end chip drivers/generic/feature device generic 0 on probe FEATURE ENABLE end end Variants can add new fields and add new options to existing fields in overridetree.cb but cannot redefine an existing option. Devices can have multiple probe tokens, and the device will be considered to be found if any of them return true. The output from defining this field are: 1) the various fields and options will be added as macro constants to static.h and can be used by fw_config for probing. 2) the probe entries will result in a list of fields/options to probe that is added to the resulting struct device and handled by coreboot. BUG=b:147462631 Signed-off-by: Duncan Laurie Change-Id: I8aea63e577d933aea09e0d0b09470929cc96e0de Reviewed-on: https://review.coreboot.org/c/coreboot/+/41440 Tested-by: build bot (Jenkins) Reviewed-by: Furquan Shaikh --- util/sconfig/lex.yy.c_shipped | 360 +++++++++++++++-------------- util/sconfig/main.c | 278 ++++++++++++++++++++++ util/sconfig/sconfig.h | 34 +++ util/sconfig/sconfig.l | 4 + util/sconfig/sconfig.tab.c_shipped | 209 +++++++++++------ util/sconfig/sconfig.tab.h_shipped | 14 +- util/sconfig/sconfig.y | 41 +++- 7 files changed, 694 insertions(+), 246 deletions(-) diff --git a/util/sconfig/lex.yy.c_shipped b/util/sconfig/lex.yy.c_shipped index 61928e6397..998505e69b 100644 --- a/util/sconfig/lex.yy.c_shipped +++ b/util/sconfig/lex.yy.c_shipped @@ -349,8 +349,8 @@ static void yynoreturn yy_fatal_error ( const char* msg ); (yy_hold_char) = *yy_cp; \ *yy_cp = '\0'; \ (yy_c_buf_p) = yy_cp; -#define YY_NUM_RULES 41 -#define YY_END_OF_BUFFER 42 +#define YY_NUM_RULES 45 +#define YY_END_OF_BUFFER 46 /* This struct is not used in this scanner, but its presence is necessary. */ struct yy_trans_info @@ -358,27 +358,30 @@ struct yy_trans_info flex_int32_t yy_verify; flex_int32_t yy_nxt; }; -static const flex_int16_t yy_accept[173] = +static const flex_int16_t yy_accept[195] = { 0, - 0, 0, 42, 40, 1, 3, 40, 40, 40, 35, - 35, 33, 36, 40, 36, 36, 36, 40, 40, 40, - 40, 40, 40, 40, 40, 40, 40, 40, 1, 3, - 40, 0, 40, 40, 0, 2, 35, 36, 40, 40, - 40, 40, 36, 40, 40, 40, 40, 40, 40, 40, - 40, 27, 40, 40, 40, 40, 40, 40, 7, 40, - 40, 40, 40, 40, 40, 40, 39, 39, 40, 0, - 34, 40, 40, 17, 40, 40, 26, 31, 40, 40, - 40, 14, 40, 40, 25, 40, 23, 40, 40, 8, - 11, 13, 40, 40, 21, 40, 22, 40, 0, 37, + 0, 0, 46, 44, 1, 3, 44, 44, 44, 39, + 39, 37, 40, 44, 40, 40, 40, 40, 44, 44, + 44, 44, 44, 44, 44, 44, 44, 44, 44, 1, + 3, 44, 0, 44, 44, 0, 2, 39, 40, 44, + 44, 44, 44, 40, 44, 44, 44, 44, 44, 44, + 44, 44, 44, 44, 31, 44, 44, 44, 44, 44, + 44, 11, 44, 44, 44, 44, 44, 44, 44, 44, + 44, 43, 43, 44, 0, 38, 44, 44, 21, 44, + 44, 30, 35, 44, 44, 44, 44, 44, 18, 44, + 44, 29, 44, 27, 44, 44, 12, 44, 15, 17, + + 44, 44, 44, 25, 44, 26, 44, 0, 41, 4, + 44, 44, 44, 28, 44, 44, 44, 44, 44, 44, + 44, 44, 24, 44, 44, 44, 44, 44, 42, 42, + 44, 44, 44, 8, 44, 44, 44, 44, 44, 19, + 44, 44, 10, 44, 44, 44, 44, 5, 22, 44, + 44, 13, 44, 16, 44, 9, 44, 44, 44, 44, + 44, 23, 33, 44, 44, 44, 44, 44, 44, 44, + 44, 44, 6, 44, 44, 44, 7, 44, 14, 44, + 44, 44, 32, 44, 44, 20, 44, 34, 44, 44, + 44, 44, 36, 0 - 4, 40, 40, 40, 24, 40, 40, 40, 40, 40, - 40, 20, 40, 40, 40, 38, 38, 40, 40, 40, - 40, 40, 40, 40, 15, 40, 40, 40, 40, 40, - 5, 18, 40, 9, 40, 12, 40, 40, 40, 40, - 40, 19, 29, 40, 40, 40, 40, 40, 40, 40, - 40, 6, 40, 40, 40, 40, 10, 40, 40, 40, - 28, 40, 40, 16, 40, 30, 40, 40, 40, 40, - 32, 0 } ; static const YY_CHAR yy_ec[256] = @@ -395,8 +398,8 @@ static const YY_CHAR yy_ec[256] = 1, 1, 1, 1, 16, 1, 17, 18, 19, 20, 21, 22, 23, 24, 25, 1, 1, 26, 27, 28, - 29, 30, 31, 32, 33, 34, 35, 36, 1, 37, - 38, 1, 1, 1, 1, 1, 1, 1, 1, 1, + 29, 30, 31, 32, 33, 34, 35, 36, 37, 38, + 39, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, @@ -413,126 +416,142 @@ static const YY_CHAR yy_ec[256] = 1, 1, 1, 1, 1 } ; -static const YY_CHAR yy_meta[39] = +static const YY_CHAR yy_meta[40] = { 0, 1, 2, 2, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1 + 1, 1, 1, 1, 1, 1, 1, 1, 1 } ; -static const flex_int16_t yy_base[180] = +static const flex_int16_t yy_base[202] = { 0, - 0, 0, 240, 0, 237, 241, 235, 37, 41, 38, - 200, 0, 44, 222, 54, 78, 60, 214, 209, 45, - 49, 48, 42, 52, 212, 62, 199, 0, 229, 241, - 93, 225, 98, 79, 226, 241, 0, 97, 104, 213, - 202, 191, 110, 198, 193, 203, 192, 193, 200, 200, - 194, 200, 185, 185, 195, 185, 187, 189, 0, 185, - 179, 185, 189, 181, 187, 186, 0, 241, 125, 198, - 0, 191, 171, 184, 174, 181, 0, 0, 172, 175, - 175, 0, 173, 163, 0, 167, 0, 171, 161, 0, - 0, 0, 164, 163, 0, 154, 0, 181, 180, 0, + 0, 0, 265, 0, 262, 266, 260, 38, 42, 39, + 224, 0, 45, 247, 55, 79, 61, 58, 239, 234, + 46, 54, 55, 68, 73, 237, 46, 224, 0, 254, + 266, 101, 250, 107, 111, 251, 266, 0, 108, 111, + 238, 227, 216, 117, 223, 218, 228, 217, 225, 229, + 216, 223, 223, 217, 223, 208, 208, 218, 208, 210, + 212, 0, 199, 207, 201, 201, 206, 210, 202, 208, + 207, 0, 266, 132, 219, 0, 212, 192, 205, 195, + 202, 0, 0, 193, 191, 197, 194, 194, 0, 192, + 182, 0, 186, 0, 190, 180, 0, 183, 0, 0, - 0, 165, 164, 157, 0, 149, 159, 147, 153, 158, - 159, 0, 142, 145, 135, 0, 241, 146, 150, 142, - 144, 140, 142, 147, 0, 131, 130, 130, 129, 126, - 0, 0, 141, 0, 125, 129, 115, 122, 126, 107, - 107, 0, 0, 114, 106, 105, 103, 114, 100, 101, - 94, 0, 105, 102, 99, 83, 0, 80, 83, 70, - 0, 60, 71, 0, 74, 0, 63, 55, 39, 29, - 0, 241, 40, 146, 148, 150, 152, 154, 156 + 189, 181, 180, 0, 171, 0, 198, 197, 0, 0, + 182, 181, 174, 0, 178, 168, 164, 174, 162, 168, + 173, 174, 0, 161, 168, 155, 158, 147, 0, 266, + 159, 163, 155, 0, 154, 156, 152, 154, 159, 0, + 143, 148, 0, 141, 141, 140, 137, 0, 0, 149, + 151, 0, 135, 152, 138, 0, 145, 136, 117, 117, + 124, 0, 0, 123, 115, 114, 112, 123, 109, 119, + 109, 101, 0, 113, 111, 115, 0, 96, 0, 92, + 82, 70, 0, 65, 77, 0, 77, 0, 71, 59, + 44, 30, 0, 266, 41, 153, 155, 157, 159, 161, + + 163 } ; -static const flex_int16_t yy_def[180] = +static const flex_int16_t yy_def[202] = { 0, - 172, 1, 172, 173, 172, 172, 173, 174, 175, 173, - 10, 173, 10, 173, 10, 10, 10, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 172, 172, - 174, 176, 177, 175, 178, 172, 10, 10, 10, 173, - 173, 173, 10, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 172, 177, 179, - 39, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 172, 173, + 194, 1, 194, 195, 194, 194, 195, 196, 197, 195, + 10, 195, 10, 195, 10, 10, 10, 10, 195, 195, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 194, + 194, 196, 198, 199, 197, 200, 194, 10, 10, 10, + 195, 195, 195, 10, 195, 195, 195, 195, 195, 195, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 195, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 195, + 195, 195, 194, 199, 201, 40, 195, 195, 195, 195, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 195, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 195, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 172, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 173, 173, 173, 173, 173, 173, 173, 173, 173, - 173, 0, 172, 172, 172, 172, 172, 172, 172 + 195, 195, 195, 195, 195, 195, 195, 194, 195, 195, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 195, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 194, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 195, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 195, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 195, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 195, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 195, + 195, 195, 195, 195, 195, 195, 195, 195, 195, 195, + 195, 195, 195, 0, 194, 194, 194, 194, 194, 194, + + 194 } ; -static const flex_int16_t yy_nxt[280] = +static const flex_int16_t yy_nxt[306] = { 0, 4, 5, 6, 7, 8, 9, 10, 11, 10, 12, 13, 13, 14, 4, 4, 4, 13, 13, 15, 16, - 17, 13, 18, 19, 20, 21, 22, 4, 23, 24, - 4, 25, 26, 4, 27, 4, 4, 4, 32, 32, - 28, 33, 35, 36, 37, 37, 37, 171, 38, 38, - 38, 38, 38, 50, 38, 38, 38, 38, 38, 38, - 38, 38, 38, 58, 56, 54, 38, 38, 38, 59, - 60, 170, 51, 52, 57, 169, 53, 41, 55, 61, - 35, 36, 168, 42, 38, 38, 38, 46, 63, 167, - 166, 64, 47, 165, 32, 32, 65, 67, 43, 70, + 17, 18, 19, 20, 21, 22, 23, 4, 24, 25, + 4, 26, 27, 4, 28, 4, 4, 4, 4, 33, + 33, 29, 34, 36, 37, 38, 38, 38, 193, 39, + 39, 39, 39, 39, 53, 39, 39, 39, 39, 39, + 39, 39, 39, 39, 39, 39, 39, 39, 39, 39, + 57, 59, 68, 54, 55, 69, 192, 56, 42, 191, + 70, 60, 49, 58, 43, 39, 39, 39, 47, 61, + 190, 64, 189, 48, 50, 62, 188, 63, 187, 44, - 70, 164, 28, 38, 38, 38, 44, 163, 162, 45, - 71, 71, 71, 161, 71, 71, 38, 38, 38, 160, - 71, 71, 71, 71, 71, 71, 70, 70, 159, 98, - 158, 157, 156, 155, 154, 153, 152, 151, 150, 149, - 148, 147, 146, 145, 144, 75, 31, 31, 34, 34, - 32, 32, 69, 69, 35, 35, 70, 70, 143, 142, + 65, 186, 33, 33, 66, 72, 185, 45, 75, 75, + 46, 29, 36, 37, 39, 39, 39, 76, 76, 76, + 184, 76, 76, 39, 39, 39, 183, 76, 76, 76, + 76, 76, 76, 75, 75, 182, 107, 181, 180, 179, + 178, 177, 176, 175, 174, 173, 172, 171, 170, 169, + 168, 167, 80, 32, 32, 35, 35, 33, 33, 74, + 74, 36, 36, 75, 75, 166, 165, 164, 163, 162, + 161, 160, 159, 158, 157, 156, 155, 154, 153, 152, + 151, 150, 149, 148, 147, 146, 145, 144, 143, 142, 141, 140, 139, 138, 137, 136, 135, 134, 133, 132, + 131, 130, 129, 128, 127, 126, 125, 124, 123, 122, 121, 120, 119, 118, 117, 116, 115, 114, 113, 112, - 111, 110, 109, 108, 107, 106, 105, 104, 103, 102, - - 101, 100, 99, 97, 96, 95, 94, 93, 92, 91, + 111, 110, 109, 108, 106, 105, 104, 103, 102, 101, + 100, 99, 98, 97, 96, 95, 94, 93, 92, 91, 90, 89, 88, 87, 86, 85, 84, 83, 82, 81, - 80, 79, 78, 77, 76, 74, 73, 72, 36, 68, - 29, 66, 62, 49, 48, 40, 39, 30, 29, 172, - 3, 172, 172, 172, 172, 172, 172, 172, 172, 172, - 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, - 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, - 172, 172, 172, 172, 172, 172, 172, 172, 172 + 79, 78, 77, 37, 73, 30, 71, 67, 52, 51, + 41, 40, 31, 30, 194, 3, 194, 194, 194, 194, + 194, 194, 194, 194, 194, 194, 194, 194, 194, 194, + 194, 194, 194, 194, 194, 194, 194, 194, 194, 194, + 194, 194, 194, 194, 194, 194, 194, 194, 194, 194, + + 194, 194, 194, 194, 194 } ; -static const flex_int16_t yy_chk[280] = +static const flex_int16_t yy_chk[306] = { 0, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, - 1, 1, 1, 1, 1, 1, 1, 1, 8, 8, - 173, 8, 9, 9, 10, 10, 10, 170, 10, 10, - 13, 13, 13, 20, 10, 10, 10, 10, 10, 10, - 15, 15, 15, 23, 22, 21, 17, 17, 17, 23, - 24, 169, 20, 20, 22, 168, 20, 15, 21, 24, - 34, 34, 167, 15, 16, 16, 16, 17, 26, 165, - 163, 26, 17, 162, 31, 31, 26, 31, 16, 33, + 1, 1, 1, 1, 1, 1, 1, 1, 1, 8, + 8, 195, 8, 9, 9, 10, 10, 10, 192, 10, + 10, 13, 13, 13, 21, 10, 10, 10, 10, 10, + 10, 15, 15, 15, 18, 18, 18, 17, 17, 17, + 22, 23, 27, 21, 21, 27, 191, 21, 15, 190, + 27, 23, 18, 22, 15, 16, 16, 16, 17, 24, + 189, 25, 187, 17, 18, 24, 185, 24, 184, 16, - 33, 160, 33, 38, 38, 38, 16, 159, 158, 16, - 39, 39, 39, 156, 39, 39, 43, 43, 43, 155, - 39, 39, 39, 39, 39, 39, 69, 69, 154, 69, - 153, 151, 150, 149, 148, 147, 146, 145, 144, 141, - 140, 139, 138, 137, 136, 43, 174, 174, 175, 175, - 176, 176, 177, 177, 178, 178, 179, 179, 135, 133, - 130, 129, 128, 127, 126, 124, 123, 122, 121, 120, - 119, 118, 115, 114, 113, 111, 110, 109, 108, 107, - 106, 104, 103, 102, 99, 98, 96, 94, 93, 89, - 88, 86, 84, 83, 81, 80, 79, 76, 75, 74, + 25, 182, 32, 32, 25, 32, 181, 16, 34, 34, + 16, 34, 35, 35, 39, 39, 39, 40, 40, 40, + 180, 40, 40, 44, 44, 44, 178, 40, 40, 40, + 40, 40, 40, 74, 74, 176, 74, 175, 174, 172, + 171, 170, 169, 168, 167, 166, 165, 164, 161, 160, + 159, 158, 44, 196, 196, 197, 197, 198, 198, 199, + 199, 200, 200, 201, 201, 157, 155, 154, 153, 151, + 150, 147, 146, 145, 144, 142, 141, 139, 138, 137, + 136, 135, 133, 132, 131, 128, 127, 126, 125, 124, + 122, 121, 120, 119, 118, 117, 116, 115, 113, 112, - 73, 72, 70, 66, 65, 64, 63, 62, 61, 60, - 58, 57, 56, 55, 54, 53, 52, 51, 50, 49, - 48, 47, 46, 45, 44, 42, 41, 40, 35, 32, - 29, 27, 25, 19, 18, 14, 11, 7, 5, 3, - 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, - 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, - 172, 172, 172, 172, 172, 172, 172, 172, 172, 172, - 172, 172, 172, 172, 172, 172, 172, 172, 172 + 111, 108, 107, 105, 103, 102, 101, 98, 96, 95, + 93, 91, 90, 88, 87, 86, 85, 84, 81, 80, + 79, 78, 77, 75, 71, 70, 69, 68, 67, 66, + 65, 64, 63, 61, 60, 59, 58, 57, 56, 55, + 54, 53, 52, 51, 50, 49, 48, 47, 46, 45, + 43, 42, 41, 36, 33, 30, 28, 26, 20, 19, + 14, 11, 7, 5, 3, 194, 194, 194, 194, 194, + 194, 194, 194, 194, 194, 194, 194, 194, 194, 194, + 194, 194, 194, 194, 194, 194, 194, 194, 194, 194, + 194, 194, 194, 194, 194, 194, 194, 194, 194, 194, + + 194, 194, 194, 194, 194 } ; static yy_state_type yy_last_accepting_state; @@ -549,21 +568,8 @@ int yy_flex_debug = 0; #define YY_MORE_ADJ 0 #define YY_RESTORE_YY_MORE_OFFSET char *yytext; -/* - * sconfig, coreboot device tree compiler - * - * Copyright (C) 2010 coresystems GmbH - * written by Patrick Georgi - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ +/* sconfig, coreboot device tree compiler */ +/* SPDX-License-Identifier: GPL-2.0-only */ #include "sconfig.tab.h" @@ -810,13 +816,13 @@ yy_match: while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 173 ) + if ( yy_current_state >= 195 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; ++yy_cp; } - while ( yy_base[yy_current_state] != 241 ); + while ( yy_base[yy_current_state] != 266 ); yy_find_action: yy_act = yy_accept[yy_current_state]; @@ -868,144 +874,160 @@ YY_RULE_SETUP YY_BREAK case 7: YY_RULE_SETUP -{yylval.number=1; return(BOOL);} +{return(FW_CONFIG_TABLE);} YY_BREAK case 8: YY_RULE_SETUP -{yylval.number=0; return(BOOL);} +{return(FW_CONFIG_FIELD);} YY_BREAK case 9: YY_RULE_SETUP -{yylval.number=3; return(STATUS);} +{return(FW_CONFIG_OPTION);} YY_BREAK case 10: YY_RULE_SETUP -{yylval.number=5; return(STATUS);} +{return(FW_CONFIG_PROBE);} YY_BREAK case 11: YY_RULE_SETUP -{yylval.number=PCI; return(BUS);} +{yylval.number=1; return(BOOL);} YY_BREAK case 12: YY_RULE_SETUP -{yylval.number=IOAPIC; return(BUS);} +{yylval.number=0; return(BOOL);} YY_BREAK case 13: YY_RULE_SETUP -{yylval.number=PNP; return(BUS);} +{yylval.number=3; return(STATUS);} YY_BREAK case 14: YY_RULE_SETUP -{yylval.number=I2C; return(BUS);} +{yylval.number=5; return(STATUS);} YY_BREAK case 15: YY_RULE_SETUP -{yylval.number=APIC; return(BUS);} +{yylval.number=PCI; return(BUS);} YY_BREAK case 16: YY_RULE_SETUP -{yylval.number=CPU_CLUSTER; return(BUS);} +{yylval.number=IOAPIC; return(BUS);} YY_BREAK case 17: YY_RULE_SETUP -{yylval.number=CPU; return(BUS);} +{yylval.number=PNP; return(BUS);} YY_BREAK case 18: YY_RULE_SETUP -{yylval.number=DOMAIN; return(BUS);} +{yylval.number=I2C; return(BUS);} YY_BREAK case 19: YY_RULE_SETUP -{yylval.number=GENERIC; return(BUS);} +{yylval.number=APIC; return(BUS);} YY_BREAK case 20: YY_RULE_SETUP -{yylval.number=MMIO; return(BUS);} +{yylval.number=CPU_CLUSTER; return(BUS);} YY_BREAK case 21: YY_RULE_SETUP -{yylval.number=SPI; return(BUS);} +{yylval.number=CPU; return(BUS);} YY_BREAK case 22: YY_RULE_SETUP -{yylval.number=USB; return(BUS);} +{yylval.number=DOMAIN; return(BUS);} YY_BREAK case 23: YY_RULE_SETUP -{yylval.number=LPC; return(BUS);} +{yylval.number=GENERIC; return(BUS);} YY_BREAK case 24: YY_RULE_SETUP -{yylval.number=ESPI; return(BUS);} +{yylval.number=MMIO; return(BUS);} YY_BREAK case 25: YY_RULE_SETUP -{yylval.number=IRQ; return(RESOURCE);} +{yylval.number=SPI; return(BUS);} YY_BREAK case 26: YY_RULE_SETUP -{yylval.number=DRQ; return(RESOURCE);} +{yylval.number=USB; return(BUS);} YY_BREAK case 27: YY_RULE_SETUP -{yylval.number=IO; return(RESOURCE);} +{yylval.number=LPC; return(BUS);} YY_BREAK case 28: YY_RULE_SETUP -{return(IOAPIC_IRQ);} +{yylval.number=ESPI; return(BUS);} YY_BREAK case 29: YY_RULE_SETUP -{return(INHERIT);} +{yylval.number=IRQ; return(RESOURCE);} YY_BREAK case 30: YY_RULE_SETUP -{return(SUBSYSTEMID);} +{yylval.number=DRQ; return(RESOURCE);} YY_BREAK case 31: YY_RULE_SETUP -{return(END);} +{yylval.number=IO; return(RESOURCE);} YY_BREAK case 32: YY_RULE_SETUP -{return(SLOT_DESC);} +{return(IOAPIC_IRQ);} YY_BREAK case 33: YY_RULE_SETUP -{return(EQUALS);} +{return(INHERIT);} YY_BREAK case 34: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(SUBSYSTEMID);} YY_BREAK case 35: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(END);} YY_BREAK case 36: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} +{return(SLOT_DESC);} YY_BREAK case 37: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} +{return(EQUALS);} YY_BREAK case 38: -/* rule 38 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 39: -/* rule 39 can match eol */ YY_RULE_SETUP -{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 40: YY_RULE_SETUP -{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(NUMBER);} YY_BREAK case 41: YY_RULE_SETUP +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(PCIINT);} + YY_BREAK +case 42: +/* rule 42 can match eol */ +YY_RULE_SETUP +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} + YY_BREAK +case 43: +/* rule 43 can match eol */ +YY_RULE_SETUP +{yylval.string = malloc(yyleng-1); strncpy(yylval.string, yytext+1, yyleng-2); yylval.string[yyleng-2]='\0'; return(STRING);} + YY_BREAK +case 44: +YY_RULE_SETUP +{yylval.string = malloc(yyleng+1); strncpy(yylval.string, yytext, yyleng); yylval.string[yyleng]='\0'; return(STRING);} + YY_BREAK +case 45: +YY_RULE_SETUP ECHO; YY_BREAK case YY_STATE_EOF(INITIAL): @@ -1304,7 +1326,7 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 173 ) + if ( yy_current_state >= 195 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; @@ -1332,11 +1354,11 @@ static int yy_get_next_buffer (void) while ( yy_chk[yy_base[yy_current_state] + yy_c] != yy_current_state ) { yy_current_state = (int) yy_def[yy_current_state]; - if ( yy_current_state >= 173 ) + if ( yy_current_state >= 195 ) yy_c = yy_meta[yy_c]; } yy_current_state = yy_nxt[yy_base[yy_current_state] + yy_c]; - yy_is_jam = (yy_current_state == 172); + yy_is_jam = (yy_current_state == 194); return yy_is_jam ? 0 : yy_current_state; } diff --git a/util/sconfig/main.c b/util/sconfig/main.c index 0d8f7f86af..6752b61cbb 100644 --- a/util/sconfig/main.c +++ b/util/sconfig/main.c @@ -5,6 +5,7 @@ /* stat.h needs to be included before commonlib/helpers.h to avoid errors.*/ #include #include +#include #include "sconfig.h" #include "sconfig.tab.h" @@ -323,6 +324,266 @@ struct chip_instance *new_chip_instance(char *path) return instance; } +/* List of fw_config fields added during parsing. */ +static struct fw_config_field *fw_config_fields; + +static struct fw_config_option *find_fw_config_option(struct fw_config_field *field, + const char *name) +{ + struct fw_config_option *option = field->options; + + while (option && option->name) { + if (!strcmp(option->name, name)) + return option; + option = option->next; + } + return NULL; +} + +static struct fw_config_field *find_fw_config_field(const char *name) +{ + struct fw_config_field *field = fw_config_fields; + + while (field && field->name) { + if (!strcmp(field->name, name)) + return field; + field = field->next; + } + return NULL; +} + +struct fw_config_field *get_fw_config_field(const char *name) +{ + struct fw_config_field *field = find_fw_config_field(name); + + /* Fail if the field does not exist, new fields must be added with a mask. */ + if (!field) { + printf("ERROR: fw_config field not found: %s\n", name); + exit(1); + } + return field; +} + +static void append_fw_config_field(struct fw_config_field *add) +{ + struct fw_config_field *field = fw_config_fields; + + if (!fw_config_fields) { + fw_config_fields = add; + } else { + while (field && field->next) + field = field->next; + field->next = add; + } +} + +struct fw_config_field *new_fw_config_field(const char *name, + unsigned int start_bit, unsigned int end_bit) +{ + struct fw_config_field *field = find_fw_config_field(name); + + /* Check that field is within 32bits. */ + if (start_bit > end_bit || end_bit > 31) { + printf("ERROR: fw_config field %s has invalid range %u-%u\n", name, + start_bit, end_bit); + exit(1); + } + + /* Don't allow re-defining a field, only adding new fields. */ + if (field) { + printf("ERROR: fw_config field %s[%u-%u] already exists with range %u-%u\n", + name, start_bit, end_bit, field->start_bit, field->end_bit); + exit(1); + } + + /* Check for overlap with an existing field. */ + field = fw_config_fields; + while (field) { + /* Check if the mask overlaps. */ + if (start_bit <= field->end_bit && end_bit >= field->start_bit) { + printf("ERROR: fw_config field %s[%u-%u] overlaps %s[%u-%u]\n", + name, start_bit, end_bit, + field->name, field->start_bit, field->end_bit); + exit(1); + } + field = field->next; + } + + field = S_ALLOC(sizeof(*field)); + field->name = name; + field->start_bit = start_bit; + field->end_bit = end_bit; + append_fw_config_field(field); + + return field; +} + +static void append_fw_config_option_to_field(struct fw_config_field *field, + struct fw_config_option *add) +{ + struct fw_config_option *option = field->options; + + if (!option) { + field->options = add; + } else { + while (option && option->next) + option = option->next; + option->next = add; + } +} + +void add_fw_config_option(struct fw_config_field *field, const char *name, unsigned int value) +{ + struct fw_config_option *option; + uint32_t field_max_value; + + /* Check that option value fits within field mask. */ + field_max_value = (1 << (1 + field->end_bit - field->start_bit)) - 1; + if (value > field_max_value) { + printf("ERROR: fw_config option %s:%s value %u larger than field max %u\n", + field->name, name, value, field_max_value); + exit(1); + } + + /* Check for existing option with this name or value. */ + option = field->options; + while (option) { + if (!strcmp(option->name, name)) { + printf("ERROR: fw_config option name %s:%s already exists\n", + field->name, name); + exit(1); + } + /* Compare values. */ + if (value == option->value) { + printf("ERROR: fw_config option %s:%s[%u] redefined as %s\n", + field->name, option->name, value, name); + exit(1); + } + option = option->next; + } + + option = S_ALLOC(sizeof(*option)); + option->name = name; + option->value = value; + + /* Add option to the current field. */ + append_fw_config_option_to_field(field, option); +} + +static void append_fw_config_probe_to_dev(struct device *dev, struct fw_config_probe *add) +{ + struct fw_config_probe *probe = dev->probe; + + if (!probe) { + dev->probe = add; + } else { + while (probe && probe->next) + probe = probe->next; + probe->next = add; + } +} + +void add_fw_config_probe(struct bus *bus, const char *field, const char *option) +{ + struct fw_config_probe *probe; + + probe = bus->dev->probe; + while (probe) { + if (!strcmp(probe->field, field) && !strcmp(probe->option, option)) { + printf("ERROR: fw_config probe %s:%s already exists\n", field, option); + exit(1); + } + probe = probe->next; + } + + probe = S_ALLOC(sizeof(*probe)); + probe->field = field; + probe->option = option; + + append_fw_config_probe_to_dev(bus->dev, probe); +} + +static void emit_fw_config(FILE *fil) +{ + struct fw_config_field *field = fw_config_fields; + + if (!field) + return; + + fprintf(fil, "\n/* firmware configuration */\n"); + fprintf(fil, "#include \n"); + + while (field) { + struct fw_config_option *option = field->options; + uint32_t mask; + + fprintf(fil, "#define FW_CONFIG_FIELD_%s_NAME \"%s\"\n", + field->name, field->name); + + /* Compute mask from start and end bit. */ + mask = ((1 << (1 + field->end_bit - field->start_bit)) - 1); + mask <<= field->start_bit; + + fprintf(fil, "#define FW_CONFIG_FIELD_%s_MASK 0x%08x\n", + field->name, mask); + + while (option) { + fprintf(fil, "#define FW_CONFIG_FIELD_%s_OPTION_%s_NAME \"%s\"\n", + field->name, option->name, option->name); + fprintf(fil, "#define FW_CONFIG_FIELD_%s_OPTION_%s_VALUE 0x%08x\n", + field->name, option->name, option->value << field->start_bit); + + option = option->next; + } + + field = field->next; + } + + fprintf(fil, "\n"); +} + +static int emit_fw_config_probe(FILE *fil, struct device *dev) +{ + struct fw_config_probe *probe = dev->probe; + + fprintf(fil, "STORAGE struct fw_config %s_probe_list[] = {\n", dev->name); + + while (probe) { + /* Find matching field. */ + struct fw_config_field *field; + struct fw_config_option *option; + uint32_t mask, value; + + field = find_fw_config_field(probe->field); + if (!field) { + printf("ERROR: fw_config_probe field %s not found\n", probe->field); + return -1; + } + option = find_fw_config_option(field, probe->option); + if (!option) { + printf("ERROR: fw_config_probe field %s option %s not found\n", + probe->field, probe->option); + return -1; + } + + /* Fill out the probe structure with values from emit_fw_config(). */ + fprintf(fil, "\t{\n"); + fprintf(fil, "\t\t.field_name = FW_CONFIG_FIELD_%s_NAME,\n", probe->field); + fprintf(fil, "\t\t.option_name = FW_CONFIG_FIELD_%s_OPTION_%s_NAME,\n", + probe->field, probe->option); + fprintf(fil, "\t\t.mask = FW_CONFIG_FIELD_%s_MASK,\n", probe->field); + fprintf(fil, "\t\t.value = FW_CONFIG_FIELD_%s_OPTION_%s_VALUE,\n", + probe->field, probe->option); + fprintf(fil, "\t},\n"); + + probe = probe->next; + } + + /* Add empty entry to mark end of list. */ + fprintf(fil, "\t{ }\n};\n"); + return 0; +} + /* * Allocate a new bus for the provided device. * - If this is the first bus being allocated under this device, then its id @@ -733,6 +994,13 @@ static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next if (chip_ins->base_chip_instance) chip_ins = chip_ins->base_chip_instance; + /* Emit probe structures. */ + if (ptr->probe && (emit_fw_config_probe(fil, ptr) < 0)) { + fclose(head); + fclose(fil); + exit(1); + } + if (ptr == &base_root_dev) fprintf(fil, "DEVTREE_CONST struct device %s = {\n", ptr->name); else @@ -780,6 +1048,8 @@ static void pass1(FILE *fil, FILE *head, struct device *ptr, struct device *next else fprintf(fil, "\t.sibling = NULL,\n"); fprintf(fil, "#if !DEVTREE_EARLY\n"); + if (ptr->probe) + fprintf(fil, "\t.probe_list = %s_probe_list,\n", ptr->name); for (pin = 0; pin < 4; pin++) { if (ptr->pci_irq_info[pin].ioapic_irq_pin > 0) fprintf(fil, @@ -1219,6 +1489,12 @@ static void update_device(struct device *base_dev, struct device *override_dev) reg = reg->next; } + /* + * Use probe list from override device in place of base device, in order + * to allow an override to remove a probe from the base device. + */ + base_dev->probe = override_dev->probe; + /* * Update base_chip_instance member in chip instance of override tree to forward it to * the chip instance in base tree. @@ -1343,9 +1619,11 @@ int main(int argc, char **argv) fprintf(autohead, "#ifndef __STATIC_DEVICE_TREE_H\n"); fprintf(autohead, "#define __STATIC_DEVICE_TREE_H\n\n"); fprintf(autohead, "#include \n\n"); + emit_fw_config(autohead); fprintf(autogen, "#include \n"); fprintf(autogen, "#include \n\n"); + fprintf(autogen, "#include \n"); emit_chips(autogen); diff --git a/util/sconfig/sconfig.h b/util/sconfig/sconfig.h index a960b7f055..1bbff4644c 100644 --- a/util/sconfig/sconfig.h +++ b/util/sconfig/sconfig.h @@ -28,6 +28,27 @@ struct pci_irq_info { int ioapic_dst_id; }; +struct fw_config_option; +struct fw_config_option { + const char *name; + unsigned int value; + struct fw_config_option *next; +}; +struct fw_config_field; +struct fw_config_field { + const char *name; + unsigned int start_bit; + unsigned int end_bit; + struct fw_config_field *next; + struct fw_config_option *options; +}; +struct fw_config_probe; +struct fw_config_probe { + const char *field; + const char *option; + struct fw_config_probe *next; +}; + struct chip; struct chip_instance { /* Monotonically increasing ID for each chip instance. */ @@ -141,6 +162,9 @@ struct device { /* SMBIOS slot length */ char *smbios_slot_length; + + /* List of field+option to probe. */ + struct fw_config_probe *probe; }; extern struct bus *root_parent; @@ -171,3 +195,13 @@ void *chip_dequeue_tail(void); struct chip_instance *new_chip_instance(char *path); void add_register(struct chip_instance *chip, char *name, char *val); + +struct fw_config_field *get_fw_config_field(const char *name); + +struct fw_config_field *new_fw_config_field(const char *name, + unsigned int start_bit, unsigned int end_bit); + +void add_fw_config_option(struct fw_config_field *field, const char *name, + unsigned int value); + +void add_fw_config_probe(struct bus *bus, const char *field, const char *option); diff --git a/util/sconfig/sconfig.l b/util/sconfig/sconfig.l index 5ac5057e23..10a86a2f2b 100755 --- a/util/sconfig/sconfig.l +++ b/util/sconfig/sconfig.l @@ -14,6 +14,10 @@ int linenum = 0; chip {return(CHIP);} device {return(DEVICE);} register {return(REGISTER);} +fw_config {return(FW_CONFIG_TABLE);} +field {return(FW_CONFIG_FIELD);} +option {return(FW_CONFIG_OPTION);} +probe {return(FW_CONFIG_PROBE);} on {yylval.number=1; return(BOOL);} off {yylval.number=0; return(BOOL);} hidden {yylval.number=3; return(STATUS);} diff --git a/util/sconfig/sconfig.tab.c_shipped b/util/sconfig/sconfig.tab.c_shipped index 2bae43bc29..c78f1ace25 100644 --- a/util/sconfig/sconfig.tab.c_shipped +++ b/util/sconfig/sconfig.tab.c_shipped @@ -1,4 +1,4 @@ -/* A Bison parser, made by GNU Bison 3.5.4. */ +/* A Bison parser, made by GNU Bison 3.5.1. */ /* Bison implementation for Yacc-like parsers in C @@ -48,7 +48,7 @@ #define YYBISON 1 /* Bison version. */ -#define YYBISON_VERSION "3.5.4" +#define YYBISON_VERSION "3.5.1" /* Skeleton name. */ #define YYSKELETON_NAME "yacc.c" @@ -77,6 +77,7 @@ void yyerror(const char *s); static struct bus *cur_parent; static struct chip_instance *cur_chip_instance; +static struct fw_config_field *cur_field; @@ -111,8 +112,8 @@ static struct chip_instance *cur_chip_instance; /* Use api.header.include to #include this header instead of duplicating it here. */ -#ifndef YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +#ifndef YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -160,7 +161,11 @@ extern int yydebug; USB = 289, MMIO = 290, LPC = 291, - ESPI = 292 + ESPI = 292, + FW_CONFIG_TABLE = 293, + FW_CONFIG_FIELD = 294, + FW_CONFIG_OPTION = 295, + FW_CONFIG_PROBE = 296 }; #endif @@ -186,7 +191,7 @@ extern YYSTYPE yylval; int yyparse (void); -#endif /* !YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ +#endif /* !YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ @@ -490,21 +495,21 @@ union yyalloc #endif /* !YYCOPY_NEEDED */ /* YYFINAL -- State number of the termination state. */ -#define YYFINAL 3 +#define YYFINAL 2 /* YYLAST -- Last index in YYTABLE. */ -#define YYLAST 45 +#define YYLAST 58 /* YYNTOKENS -- Number of terminals. */ -#define YYNTOKENS 38 +#define YYNTOKENS 42 /* YYNNTS -- Number of nonterminals. */ -#define YYNNTS 15 +#define YYNNTS 23 /* YYNRULES -- Number of rules. */ -#define YYNRULES 29 +#define YYNRULES 44 /* YYNSTATES -- Number of states. */ -#define YYNSTATES 50 +#define YYNSTATES 75 #define YYUNDEFTOK 2 -#define YYMAXUTOK 292 +#define YYMAXUTOK 296 /* YYTRANSLATE(TOKEN-NUM) -- Symbol number corresponding to TOKEN-NUM @@ -545,16 +550,18 @@ static const yytype_int8 yytranslate[] = 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, - 35, 36, 37 + 35, 36, 37, 38, 39, 40, 41 }; #if YYDEBUG /* YYRLINE[YYN] -- Source line where rule number YYN was defined. */ static const yytype_int8 yyrline[] = { - 0, 36, 36, 36, 38, 38, 38, 38, 40, 40, - 40, 40, 40, 40, 40, 40, 42, 42, 51, 51, - 59, 59, 61, 64, 67, 70, 73, 76, 79, 82 + 0, 24, 24, 24, 24, 26, 26, 26, 26, 28, + 28, 28, 28, 28, 28, 28, 28, 28, 30, 30, + 39, 39, 47, 47, 49, 52, 55, 58, 61, 64, + 67, 70, 74, 77, 77, 80, 80, 83, 83, 89, + 89, 95, 95, 101, 105 }; #endif @@ -568,9 +575,13 @@ static const char *const yytname[] = "STRING", "PCI", "PNP", "I2C", "APIC", "CPU_CLUSTER", "CPU", "DOMAIN", "IRQ", "DRQ", "SLOT_DESC", "IO", "NUMBER", "SUBSYSTEMID", "INHERIT", "IOAPIC_IRQ", "IOAPIC", "PCIINT", "GENERIC", "SPI", "USB", "MMIO", "LPC", - "ESPI", "$accept", "devtree", "$@1", "chipchildren", "devicechildren", - "chip", "@2", "device", "@3", "status", "resource", "registers", - "subsystemid", "ioapic_irq", "smbios_slot_desc", YY_NULLPTR + "ESPI", "FW_CONFIG_TABLE", "FW_CONFIG_FIELD", "FW_CONFIG_OPTION", + "FW_CONFIG_PROBE", "$accept", "devtree", "chipchildren", + "devicechildren", "chip", "@1", "device", "@2", "status", "resource", + "registers", "subsystemid", "ioapic_irq", "smbios_slot_desc", + "fw_config_table", "fw_config_table_children", + "fw_config_field_children", "fw_config_field", "$@3", "$@4", "$@5", + "fw_config_option", "fw_config_probe", YY_NULLPTR }; #endif @@ -582,11 +593,12 @@ static const yytype_int16 yytoknum[] = 0, 256, 257, 258, 259, 260, 261, 262, 263, 264, 265, 266, 267, 268, 269, 270, 271, 272, 273, 274, 275, 276, 277, 278, 279, 280, 281, 282, 283, 284, - 285, 286, 287, 288, 289, 290, 291, 292 + 285, 286, 287, 288, 289, 290, 291, 292, 293, 294, + 295, 296 }; # endif -#define YYPACT_NINF (-10) +#define YYPACT_NINF (-12) #define yypact_value_is_default(Yyn) \ ((Yyn) == YYPACT_NINF) @@ -600,11 +612,14 @@ static const yytype_int16 yytoknum[] = STATE-NUM. */ static const yytype_int8 yypact[] = { - -10, 11, 10, -10, 0, -10, -10, -10, 1, 6, - 2, -10, -10, -10, -10, -9, 8, 3, 4, -10, - -10, -10, -10, -10, -3, -4, -10, 9, -1, 5, - -10, -10, -10, -10, -10, -10, -10, 15, 14, 7, - -2, 12, 16, 13, 17, -10, 18, -10, -10, -10 + -12, 3, -12, 4, -12, -12, -12, -12, -2, -12, + -12, 8, -12, 9, 1, 14, 11, -12, -12, -12, + -12, 2, -12, 5, 17, -12, -12, -6, 10, 16, + -12, -1, -12, 18, -12, -12, -12, -12, -12, 0, + -12, 7, -12, -12, -12, -3, 19, -12, 21, 20, + 22, 28, -12, -12, -12, -12, -12, -12, -12, -12, + 31, 30, 23, 24, 33, 25, 36, 26, 27, -12, + -12, 38, -12, -12, -12 }; /* YYDEFACT[STATE-NUM] -- Default reduction number in state STATE-NUM. @@ -612,25 +627,30 @@ static const yytype_int8 yypact[] = means the default is an error. */ static const yytype_int8 yydefact[] = { - 2, 0, 0, 1, 0, 3, 16, 7, 0, 0, - 0, 17, 5, 4, 6, 0, 0, 0, 0, 20, - 21, 18, 23, 15, 0, 0, 19, 0, 0, 0, - 9, 8, 10, 14, 11, 12, 13, 0, 0, 0, - 0, 0, 29, 24, 0, 22, 28, 25, 26, 27 + 2, 0, 1, 0, 34, 3, 4, 18, 0, 8, + 32, 0, 33, 0, 41, 0, 0, 19, 6, 5, + 7, 39, 36, 0, 0, 37, 36, 0, 0, 0, + 36, 0, 42, 0, 35, 22, 23, 20, 25, 0, + 40, 0, 17, 38, 43, 0, 0, 21, 0, 0, + 0, 0, 10, 9, 11, 15, 12, 13, 14, 16, + 0, 0, 0, 0, 0, 0, 31, 26, 0, 44, + 24, 30, 27, 28, 29 }; /* YYPGOTO[NTERM-NUM]. */ static const yytype_int8 yypgoto[] = { - -10, -10, -10, -10, -10, -5, -10, 20, -10, -10, - -10, 21, -10, -10, -10 + -12, -12, -12, -12, -9, -12, 12, -12, -12, -12, + 13, -12, -12, -12, -12, -12, -11, -12, -12, -12, + -12, -12, -12 }; /* YYDEFGOTO[NTERM-NUM]. */ static const yytype_int8 yydefgoto[] = { - -1, 1, 2, 8, 24, 5, 7, 13, 23, 21, - 32, 14, 34, 35, 36 + -1, 1, 13, 45, 5, 9, 19, 42, 37, 54, + 20, 56, 57, 58, 6, 8, 27, 12, 30, 26, + 22, 34, 59 }; /* YYTABLE[YYPACT[STATE-NUM]] -- What to do in state STATE-NUM. If @@ -638,47 +658,56 @@ static const yytype_int8 yydefgoto[] = number is the opposite. If YYTABLE_NINF, syntax error. */ static const yytype_int8 yytable[] = { - 4, 9, 10, 12, 4, 9, 10, 25, 26, 19, - 20, 3, 11, 4, 6, 15, 16, 17, 22, 30, - 18, 27, 37, 38, 28, 39, 29, 41, 42, 44, - 46, 40, 49, 43, 0, 0, 0, 0, 45, 0, - 0, 47, 0, 48, 31, 33 + 3, 15, 16, 2, 18, 32, 3, 46, 47, 10, + 40, 43, 3, 15, 16, 31, 35, 36, 7, 39, + 17, 48, 14, 23, 49, 24, 50, 21, 25, 29, + 38, 28, 41, 44, 33, 61, 52, 11, 51, 33, + 33, 4, 64, 65, 66, 60, 62, 69, 63, 67, + 71, 70, 74, 73, 72, 68, 0, 53, 55 }; static const yytype_int8 yycheck[] = { - 3, 4, 5, 8, 3, 4, 5, 10, 11, 6, - 7, 0, 11, 3, 14, 9, 14, 26, 14, 24, - 12, 24, 26, 14, 27, 26, 29, 12, 14, 31, - 14, 26, 14, 26, -1, -1, -1, -1, 26, -1, - -1, 28, -1, 26, 24, 24 + 3, 4, 5, 0, 13, 11, 3, 10, 11, 11, + 11, 11, 3, 4, 5, 26, 6, 7, 14, 30, + 11, 24, 14, 9, 27, 14, 29, 26, 26, 12, + 14, 26, 14, 26, 40, 14, 45, 39, 41, 40, + 40, 38, 14, 12, 14, 26, 26, 14, 26, 26, + 14, 26, 14, 26, 28, 31, -1, 45, 45 }; /* YYSTOS[STATE-NUM] -- The (internal number of the) accessing symbol of state STATE-NUM. */ static const yytype_int8 yystos[] = { - 0, 39, 40, 0, 3, 43, 14, 44, 41, 4, - 5, 11, 43, 45, 49, 9, 14, 26, 12, 6, - 7, 47, 14, 46, 42, 10, 11, 24, 27, 29, - 43, 45, 48, 49, 50, 51, 52, 26, 14, 26, - 26, 12, 14, 26, 31, 26, 14, 28, 26, 14 + 0, 43, 0, 3, 38, 46, 56, 14, 57, 47, + 11, 39, 59, 44, 14, 4, 5, 11, 46, 48, + 52, 26, 62, 9, 14, 26, 61, 58, 26, 12, + 60, 58, 11, 40, 63, 6, 7, 50, 14, 58, + 11, 14, 49, 11, 26, 45, 10, 11, 24, 27, + 29, 41, 46, 48, 51, 52, 53, 54, 55, 64, + 26, 14, 26, 26, 14, 12, 14, 26, 31, 14, + 26, 14, 28, 26, 14 }; /* YYR1[YYN] -- Symbol number of symbol that rule YYN derives. */ static const yytype_int8 yyr1[] = { - 0, 38, 40, 39, 41, 41, 41, 41, 42, 42, - 42, 42, 42, 42, 42, 42, 44, 43, 46, 45, - 47, 47, 48, 49, 50, 50, 51, 52, 52, 52 + 0, 42, 43, 43, 43, 44, 44, 44, 44, 45, + 45, 45, 45, 45, 45, 45, 45, 45, 47, 46, + 49, 48, 50, 50, 51, 52, 53, 53, 54, 55, + 55, 55, 56, 57, 57, 58, 58, 60, 59, 61, + 59, 62, 59, 63, 64 }; /* YYR2[YYN] -- Number of symbols on the right hand side of rule YYN. */ static const yytype_int8 yyr2[] = { - 0, 2, 0, 2, 2, 2, 2, 0, 2, 2, - 2, 2, 2, 2, 2, 0, 0, 5, 0, 7, - 1, 1, 4, 4, 3, 4, 4, 5, 4, 3 + 0, 2, 0, 2, 2, 2, 2, 2, 0, 2, + 2, 2, 2, 2, 2, 2, 2, 0, 0, 5, + 0, 7, 1, 1, 4, 4, 3, 4, 4, 5, + 4, 3, 3, 2, 0, 2, 0, 0, 7, 0, + 6, 0, 5, 3, 3 }; @@ -1377,7 +1406,7 @@ yyreduce: { cur_parent = root_parent; } break; - case 16: + case 18: { (yyval.chip_instance) = new_chip_instance((yyvsp[0].string)); chip_enqueue_tail(cur_chip_instance); @@ -1385,57 +1414,99 @@ yyreduce: } break; - case 17: + case 19: { cur_chip_instance = chip_dequeue_tail(); } break; - case 18: + case 20: { (yyval.dev) = new_device(cur_parent, cur_chip_instance, (yyvsp[-2].number), (yyvsp[-1].string), (yyvsp[0].number)); cur_parent = (yyval.dev)->last_bus; } break; - case 19: + case 21: { cur_parent = (yyvsp[-2].dev)->parent; } break; - case 22: + case 24: { add_resource(cur_parent, (yyvsp[-3].number), strtol((yyvsp[-2].string), NULL, 0), strtol((yyvsp[0].string), NULL, 0)); } break; - case 23: + case 25: { add_register(cur_chip_instance, (yyvsp[-2].string), (yyvsp[0].string)); } break; - case 24: + case 26: { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-1].string), NULL, 16), strtol((yyvsp[0].string), NULL, 16), 0); } break; - case 25: + case 27: { add_pci_subsystem_ids(cur_parent, strtol((yyvsp[-2].string), NULL, 16), strtol((yyvsp[-1].string), NULL, 16), 1); } break; - case 26: + case 28: { add_ioapic_info(cur_parent, strtol((yyvsp[-2].string), NULL, 16), (yyvsp[-1].string), strtol((yyvsp[0].string), NULL, 16)); } break; - case 27: + case 29: { add_slot_desc(cur_parent, (yyvsp[-3].string), (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string)); } break; - case 28: + case 30: { add_slot_desc(cur_parent, (yyvsp[-2].string), (yyvsp[-1].string), (yyvsp[0].string), NULL); } break; - case 29: + case 31: { add_slot_desc(cur_parent, (yyvsp[-1].string), (yyvsp[0].string), NULL, NULL); } break; + case 32: + { } + break; + + case 37: + { + cur_field = new_fw_config_field((yyvsp[-2].string), strtoul((yyvsp[-1].string), NULL, 0), strtoul((yyvsp[0].string), NULL, 0)); +} + break; + + case 38: + { } + break; + + case 39: + { + cur_field = new_fw_config_field((yyvsp[-1].string), strtoul((yyvsp[0].string), NULL, 0), strtoul((yyvsp[0].string), NULL, 0)); +} + break; + + case 40: + { } + break; + + case 41: + { + cur_field = get_fw_config_field((yyvsp[0].string)); +} + break; + + case 42: + { } + break; + + case 43: + { add_fw_config_option(cur_field, (yyvsp[-1].string), strtoul((yyvsp[0].string), NULL, 0)); } + break; + + case 44: + { add_fw_config_probe(cur_parent, (yyvsp[-1].string), (yyvsp[0].string)); } + break; + default: break; diff --git a/util/sconfig/sconfig.tab.h_shipped b/util/sconfig/sconfig.tab.h_shipped index 5fa9d19362..cadd847fa4 100644 --- a/util/sconfig/sconfig.tab.h_shipped +++ b/util/sconfig/sconfig.tab.h_shipped @@ -1,4 +1,4 @@ -/* A Bison parser, made by GNU Bison 3.5.4. */ +/* A Bison parser, made by GNU Bison 3.5.1. */ /* Bison interface for Yacc-like parsers in C @@ -34,8 +34,8 @@ /* Undocumented macros, especially those whose name start with YY_, are private implementation details. Do not rely on them. */ -#ifndef YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED -# define YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +#ifndef YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED +# define YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED /* Debug traces. */ #ifndef YYDEBUG # define YYDEBUG 0 @@ -83,7 +83,11 @@ extern int yydebug; USB = 289, MMIO = 290, LPC = 291, - ESPI = 292 + ESPI = 292, + FW_CONFIG_TABLE = 293, + FW_CONFIG_FIELD = 294, + FW_CONFIG_OPTION = 295, + FW_CONFIG_PROBE = 296 }; #endif @@ -109,4 +113,4 @@ extern YYSTYPE yylval; int yyparse (void); -#endif /* !YY_YY_HOME_ME_REPOS_COREBOOTORG_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ +#endif /* !YY_YY_SRC_COREBOOT_UTIL_SCONFIG_SCONFIG_TAB_H_SHIPPED_INCLUDED */ diff --git a/util/sconfig/sconfig.y b/util/sconfig/sconfig.y index 161cf81551..57e939d9f0 100755 --- a/util/sconfig/sconfig.y +++ b/util/sconfig/sconfig.y @@ -9,6 +9,7 @@ void yyerror(const char *s); static struct bus *cur_parent; static struct chip_instance *cur_chip_instance; +static struct fw_config_field *cur_field; %} %union { @@ -18,13 +19,13 @@ static struct chip_instance *cur_chip_instance; int number; } -%token CHIP DEVICE REGISTER BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO LPC ESPI +%token CHIP DEVICE REGISTER BOOL STATUS MANDATORY BUS RESOURCE END EQUALS HEX STRING PCI PNP I2C APIC CPU_CLUSTER CPU DOMAIN IRQ DRQ SLOT_DESC IO NUMBER SUBSYSTEMID INHERIT IOAPIC_IRQ IOAPIC PCIINT GENERIC SPI USB MMIO LPC ESPI FW_CONFIG_TABLE FW_CONFIG_FIELD FW_CONFIG_OPTION FW_CONFIG_PROBE %% -devtree: { cur_parent = root_parent; } chip; +devtree: { cur_parent = root_parent; } | devtree chip | devtree fw_config_table; chipchildren: chipchildren device | chipchildren chip | chipchildren registers | /* empty */ ; -devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | devicechildren registers | /* empty */ ; +devicechildren: devicechildren device | devicechildren chip | devicechildren resource | devicechildren subsystemid | devicechildren ioapic_irq | devicechildren smbios_slot_desc | devicechildren registers | devicechildren fw_config_probe | /* empty */ ; chip: CHIP STRING /* == path */ { $$ = new_chip_instance($2); @@ -69,4 +70,38 @@ smbios_slot_desc: SLOT_DESC STRING STRING STRING smbios_slot_desc: SLOT_DESC STRING STRING { add_slot_desc(cur_parent, $2, $3, NULL, NULL); }; +/* fw_config: firmware configuration table */ +fw_config_table: FW_CONFIG_TABLE fw_config_table_children END { }; + +/* fw_config -> field */ +fw_config_table_children: fw_config_table_children fw_config_field | /* empty */ ; + +/* field -> option */ +fw_config_field_children: fw_config_field_children fw_config_option | /* empty */ ; + +/* field */ +fw_config_field: FW_CONFIG_FIELD STRING NUMBER /* == start bit */ NUMBER /* == end bit */ { + cur_field = new_fw_config_field($2, strtoul($3, NULL, 0), strtoul($4, NULL, 0)); +} + fw_config_field_children END { }; + +/* field (for single-bit fields) */ +fw_config_field: FW_CONFIG_FIELD STRING NUMBER /* == bit */ { + cur_field = new_fw_config_field($2, strtoul($3, NULL, 0), strtoul($3, NULL, 0)); +} + fw_config_field_children END { }; + +/* field (for adding options to an existing field) */ +fw_config_field: FW_CONFIG_FIELD STRING { + cur_field = get_fw_config_field($2); +} + fw_config_field_children END { }; + +/* option */ +fw_config_option: FW_CONFIG_OPTION STRING NUMBER /* == field value */ + { add_fw_config_option(cur_field, $2, strtoul($3, NULL, 0)); }; + +/* probe