From 9493c2ece2439a7a8253b18448a36dca2964fd69 Mon Sep 17 00:00:00 2001 From: Seunghwan Kim Date: Mon, 29 Apr 2024 11:20:50 +0900 Subject: [PATCH] mb/google/brya/var/xol: Add EC_IN_RW_OD config into early_gpio_table Add GPP_F18 configuration in early_gpio_table. Without this, DUT cannot get the proper state of this signal on early phase. It allowed DUT to attempt to enter into dev mode when EC is in RW currently, it causes the failure of autotest/firmware_DevMode. BUG=b:337365524 TEST=built and run autotest firmware_DevMode Change-Id: I2179bb10b431547bc35f332c74915a63495b779d Signed-off-by: Seunghwan Kim Reviewed-on: https://review.coreboot.org/c/coreboot/+/82099 Reviewed-by: Nick Vaccaro Tested-by: build bot (Jenkins) Reviewed-by: Eric Lai Reviewed-by: YH Lin --- src/mainboard/google/brya/variants/xol/gpio.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/mainboard/google/brya/variants/xol/gpio.c b/src/mainboard/google/brya/variants/xol/gpio.c index 168d9821d0..39478a1489 100644 --- a/src/mainboard/google/brya/variants/xol/gpio.c +++ b/src/mainboard/google/brya/variants/xol/gpio.c @@ -195,6 +195,8 @@ static const struct pad_config early_gpio_table[] = { PAD_CFG_GPI(GPP_E13, NONE, DEEP), /* E15 : RSVD_TP ==> PCH_WP_OD */ PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP), + /* F18 : EC_IN_RW_OD ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), /* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */ PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), /* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */