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soc/intel/apollolake: add ability to enable eSPI

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Add config option to enable eSPI

TEST=Boot to OS

Change-Id: Ib4634690fe4fdb902fc0bc074a3b66b91921ddd5
Signed-off-by: Bora Guvendik <bora.guvendik@intel.com>
Reviewed-on: https://review.coreboot.org/22320
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Hannah Williams <hannah.williams@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
This commit is contained in:
Bora Guvendik
2017-11-03 12:40:25 -07:00
committed by Subrata Banik
parent c73073c414
commit 94aed8d615
4 changed files with 10 additions and 0 deletions
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2
src/soc/intel/apollolake/lpc.c
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@ -45,6 +45,7 @@ const struct lpc_mmio_range *soc_get_fixed_mmio_ranges(void)
static const struct pad_config lpc_gpios[] = {
#if IS_ENABLED(CONFIG_SOC_INTEL_GLK)
#if !IS_ENABLED(CONFIG_SOC_ESPI)
PAD_CFG_NF(GPIO_147, UP_20K, DEEP, NF1), /* LPC_ILB_SERIRQ */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_148, UP_20K, DEEP, NF1, HIZCRx1,
DISPUPD), /* LPC_CLKOUT0 */
@ -62,6 +63,7 @@ static const struct pad_config lpc_gpios[] = {
DISPUPD), /* LPC_CLKRUNB */
PAD_CFG_NF_IOSSTATE_IOSTERM(GPIO_155, UP_20K, DEEP, NF1, HIZCRx1,
DISPUPD), /* LPC_FRAMEB*/
#endif /* !IS_ENABLED(CONFIG_SOC_ESPI) */
#else
PAD_CFG_NF(LPC_ILB_SERIRQ, UP_20K, DEEP, NF1),
PAD_CFG_NF(LPC_CLKRUNB, UP_20K, DEEP, NF1),