FSP 1.1: Move common FSP code
Move the FSP common code from the src/soc/intel/common directory into the src/drivers/intel/fsp1_1 directory. Rename the Kconfig values associated with this common code. BRANCH=none BUG=None TEST=Build and run on kunimitsu Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440 Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306350 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12156 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
This commit is contained in:
Lee Leahy
committed by
Patrick Georgi
Patrick Georgi
parent
597de2849d
commit
94b856ef9a
317
src/drivers/intel/fsp1_1/raminit.c
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317
src/drivers/intel/fsp1_1/raminit.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2014-2015 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <cbmem.h>
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#include <console/console.h>
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#include <fsp/memmap.h>
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#include <fsp/util.h>
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#include <lib.h> /* hexdump */
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#include <reset.h>
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#include <soc/pei_data.h>
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#include <soc/romstage.h>
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#include <string.h>
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#include <timestamp.h>
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void raminit(struct romstage_params *params)
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{
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const EFI_GUID bootldr_tolum_guid = FSP_BOOTLOADER_TOLUM_HOB_GUID;
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EFI_HOB_RESOURCE_DESCRIPTOR *cbmem_root;
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FSP_INFO_HEADER *fsp_header;
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EFI_HOB_RESOURCE_DESCRIPTOR *fsp_memory;
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FSP_MEMORY_INIT fsp_memory_init;
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FSP_MEMORY_INIT_PARAMS fsp_memory_init_params;
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const EFI_GUID fsp_reserved_guid =
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FSP_RESERVED_MEMORY_RESOURCE_HOB_GUID;
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void *fsp_reserved_memory_area;
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FSP_INIT_RT_COMMON_BUFFER fsp_rt_common_buffer;
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void *hob_list_ptr;
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FSP_SMBIOS_MEMORY_INFO *memory_info_hob;
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const EFI_GUID memory_info_hob_guid = FSP_SMBIOS_MEMORY_INFO_GUID;
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MEMORY_INIT_UPD memory_init_params;
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const EFI_GUID mrc_guid = FSP_NON_VOLATILE_STORAGE_HOB_GUID;
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u32 *mrc_hob;
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u32 fsp_reserved_bytes;
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MEMORY_INIT_UPD *original_params;
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struct pei_data *pei_ptr;
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EFI_STATUS status;
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VPD_DATA_REGION *vpd_ptr;
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UPD_DATA_REGION *upd_ptr;
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int fsp_verification_failure = 0;
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#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
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unsigned long int data;
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EFI_PEI_HOB_POINTERS hob_ptr;
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#endif
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/*
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* Find and copy the UPD region to the stack so the platform can modify
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* the settings if needed. Modifications to the UPD buffer are done in
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* the platform callback code. The platform callback code is also
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* responsible for assigning the UpdDataRngPtr to this buffer if any
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* updates are made. The default state is to leave the UpdDataRngPtr
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* set to NULL. This indicates that the FSP code will use the UPD
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* region in the FSP binary.
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*/
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post_code(0x34);
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fsp_header = params->chipset_context;
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vpd_ptr = (VPD_DATA_REGION *)(fsp_header->CfgRegionOffset +
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fsp_header->ImageBase);
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printk(BIOS_DEBUG, "VPD Data: 0x%p\n", vpd_ptr);
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upd_ptr = (UPD_DATA_REGION *)(vpd_ptr->PcdUpdRegionOffset +
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fsp_header->ImageBase);
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printk(BIOS_DEBUG, "UPD Data: 0x%p\n", upd_ptr);
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original_params = (void *)((u8 *)upd_ptr +
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upd_ptr->MemoryInitUpdOffset);
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memcpy(&memory_init_params, original_params,
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sizeof(memory_init_params));
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/* Zero fill RT Buffer data and start populating fields. */
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memset(&fsp_rt_common_buffer, 0, sizeof(fsp_rt_common_buffer));
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pei_ptr = params->pei_data;
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if (pei_ptr->boot_mode == SLEEP_STATE_S3) {
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fsp_rt_common_buffer.BootMode = BOOT_ON_S3_RESUME;
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} else if (pei_ptr->saved_data != NULL) {
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fsp_rt_common_buffer.BootMode =
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BOOT_ASSUMING_NO_CONFIGURATION_CHANGES;
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} else {
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fsp_rt_common_buffer.BootMode = BOOT_WITH_FULL_CONFIGURATION;
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}
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fsp_rt_common_buffer.UpdDataRgnPtr = &memory_init_params;
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fsp_rt_common_buffer.BootLoaderTolumSize = cbmem_overhead_size();
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/* Get any board specific changes */
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fsp_memory_init_params.NvsBufferPtr = (void *)pei_ptr->saved_data;
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fsp_memory_init_params.RtBufferPtr = &fsp_rt_common_buffer;
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fsp_memory_init_params.HobListPtr = &hob_list_ptr;
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/* Update the UPD data */
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soc_memory_init_params(params, &memory_init_params);
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mainboard_memory_init_params(params, &memory_init_params);
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post_code(0x36);
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/* Display the UPD data */
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if (IS_ENABLED(CONFIG_DISPLAY_UPD_DATA))
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soc_display_memory_init_params(original_params,
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&memory_init_params);
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/* Call FspMemoryInit to initialize RAM */
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fsp_memory_init = (FSP_MEMORY_INIT)(fsp_header->ImageBase
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+ fsp_header->FspMemoryInitEntryOffset);
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printk(BIOS_DEBUG, "Calling FspMemoryInit: 0x%p\n", fsp_memory_init);
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printk(BIOS_SPEW, " 0x%p: NvsBufferPtr\n",
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fsp_memory_init_params.NvsBufferPtr);
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printk(BIOS_SPEW, " 0x%p: RtBufferPtr\n",
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fsp_memory_init_params.RtBufferPtr);
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printk(BIOS_SPEW, " 0x%p: HobListPtr\n",
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fsp_memory_init_params.HobListPtr);
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timestamp_add_now(TS_FSP_MEMORY_INIT_START);
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status = fsp_memory_init(&fsp_memory_init_params);
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post_code(0x37);
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timestamp_add_now(TS_FSP_MEMORY_INIT_END);
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printk(BIOS_DEBUG, "FspMemoryInit returned 0x%08x\n", status);
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if (status != EFI_SUCCESS)
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die("ERROR - FspMemoryInit failed to initialize memory!\n");
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/* Locate the FSP reserved memory area */
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fsp_reserved_bytes = 0;
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fsp_memory = get_next_resource_hob(&fsp_reserved_guid, hob_list_ptr);
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if (fsp_memory == NULL) {
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fsp_verification_failure = 1;
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printk(BIOS_DEBUG,
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"7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB missing!\n");
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} else {
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fsp_reserved_bytes = fsp_memory->ResourceLength;
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printk(BIOS_DEBUG, "Reserving 0x%016lx bytes for FSP\n",
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(unsigned long int)fsp_reserved_bytes);
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}
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/* Display SMM area */
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#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
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char *smm_base;
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size_t smm_size;
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smm_region((void **)&smm_base, &smm_size);
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printk(BIOS_DEBUG, "0x%08x: smm_size\n", (unsigned int)smm_size);
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printk(BIOS_DEBUG, "0x%p: smm_base\n", smm_base);
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#endif
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/* Migrate CAR data */
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printk(BIOS_DEBUG, "0x%p: cbmem_top\n", cbmem_top());
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if (pei_ptr->boot_mode != SLEEP_STATE_S3) {
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cbmem_initialize_empty_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
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fsp_reserved_bytes);
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} else if (cbmem_initialize_id_size(CBMEM_ID_FSP_RESERVED_MEMORY,
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fsp_reserved_bytes)) {
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#if IS_ENABLED(CONFIG_HAVE_ACPI_RESUME)
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printk(BIOS_DEBUG, "Failed to recover CBMEM in S3 resume.\n");
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/* Failed S3 resume, reset to come up cleanly */
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hard_reset();
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#endif
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}
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/* Save the FSP runtime parameters. */
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fsp_set_runtime(fsp_header, hob_list_ptr);
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/* Lookup the FSP_BOOTLOADER_TOLUM_HOB */
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cbmem_root = get_next_resource_hob(&bootldr_tolum_guid, hob_list_ptr);
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if (cbmem_root == NULL) {
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fsp_verification_failure = 1;
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printk(BIOS_ERR, "7.4: FSP_BOOTLOADER_TOLUM_HOB missing!\n");
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printk(BIOS_ERR, "BootLoaderTolumSize: 0x%08x bytes\n",
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fsp_rt_common_buffer.BootLoaderTolumSize);
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}
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/* Locate the FSP_SMBIOS_MEMORY_INFO HOB */
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memory_info_hob = get_next_guid_hob(&memory_info_hob_guid,
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hob_list_ptr);
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if (NULL == memory_info_hob) {
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printk(BIOS_ERR, "FSP_SMBIOS_MEMORY_INFO HOB missing!\n");
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fsp_verification_failure = 1;
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} else {
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printk(BIOS_DEBUG,
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"FSP_SMBIOS_MEMORY_INFO HOB: 0x%p\n",
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memory_info_hob);
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}
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#if IS_ENABLED(CONFIG_DISPLAY_HOBS)
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if (hob_list_ptr == NULL)
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die("ERROR - HOB pointer is NULL!\n");
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/*
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* Verify that FSP is generating the required HOBs:
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* 7.1: FSP_BOOTLOADER_TEMP_MEMORY_HOB only produced for FSP 1.0
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* 7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB verified above
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* 7.3: FSP_NON_VOLATILE_STORAGE_HOB verified below
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* 7.4: FSP_BOOTLOADER_TOLUM_HOB verified above
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* 7.5: EFI_PEI_GRAPHICS_INFO_HOB produced by SiliconInit
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* FSP_SMBIOS_MEMORY_INFO HOB verified above
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*/
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if (NULL != cbmem_root) {
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printk(BIOS_DEBUG,
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"7.4: FSP_BOOTLOADER_TOLUM_HOB: 0x%p\n",
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cbmem_root);
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data = cbmem_root->PhysicalStart;
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printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
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data = cbmem_root->ResourceLength;
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printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
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}
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hob_ptr.Raw = get_next_guid_hob(&mrc_guid, hob_list_ptr);
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if (NULL == hob_ptr.Raw) {
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printk(BIOS_ERR, "7.3: FSP_NON_VOLATILE_STORAGE_HOB missing!\n");
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fsp_verification_failure =
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(params->pei_data->saved_data == NULL) ? 1 : 0;
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} else {
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printk(BIOS_DEBUG,
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"7.3: FSP_NON_VOLATILE_STORAGE_HOB: 0x%p\n",
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hob_ptr.Raw);
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}
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if (fsp_memory != NULL) {
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printk(BIOS_DEBUG,
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"7.2: FSP_RESERVED_MEMORY_RESOURCE_HOB: 0x%p\n",
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fsp_memory);
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data = fsp_memory->PhysicalStart;
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printk(BIOS_DEBUG, " 0x%016lx: PhysicalStart\n", data);
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data = fsp_memory->ResourceLength;
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printk(BIOS_DEBUG, " 0x%016lx: ResourceLength\n", data);
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}
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/* Verify all the HOBs are present */
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if (fsp_verification_failure)
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printk(BIOS_DEBUG,
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"ERROR - Missing one or more required FSP HOBs!\n");
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/* Display the HOBs */
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print_hob_type_structure(0, hob_list_ptr);
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#endif
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/* Get the address of the CBMEM region for the FSP reserved memory */
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fsp_reserved_memory_area = cbmem_find(CBMEM_ID_FSP_RESERVED_MEMORY);
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printk(BIOS_DEBUG, "0x%p: fsp_reserved_memory_area\n",
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fsp_reserved_memory_area);
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/* Verify the order of CBMEM root and FSP memory */
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if ((fsp_memory != NULL) && (cbmem_root != NULL) &&
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(cbmem_root->PhysicalStart <= fsp_memory->PhysicalStart)) {
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fsp_verification_failure = 1;
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printk(BIOS_DEBUG,
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"ERROR - FSP reserved memory above CBMEM root!\n");
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}
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/* Verify that the FSP memory was properly reserved */
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if ((fsp_memory != NULL) && ((fsp_reserved_memory_area == NULL) ||
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(fsp_memory->PhysicalStart !=
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(unsigned int)fsp_reserved_memory_area))) {
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fsp_verification_failure = 1;
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printk(BIOS_DEBUG, "ERROR - Reserving FSP memory area!\n");
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#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
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if (cbmem_root != NULL) {
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size_t delta_bytes = (unsigned int)smm_base
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- cbmem_root->PhysicalStart
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- cbmem_root->ResourceLength;
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printk(BIOS_DEBUG,
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"0x%08x: Chipset reserved bytes reported by FSP\n",
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(unsigned int)delta_bytes);
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die("Please verify the chipset reserved size\n");
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}
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#endif
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}
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/* Verify the FSP 1.1 HOB interface */
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if (fsp_verification_failure)
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die("ERROR - Coreboot's requirements not met by FSP binary!\n");
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/* Display the memory configuration */
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report_memory_config();
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/* Locate the memory configuration data to speed up the next reboot */
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mrc_hob = get_next_guid_hob(&mrc_guid, hob_list_ptr);
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if (mrc_hob == NULL)
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printk(BIOS_DEBUG,
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"Memory Configuration Data Hob not present\n");
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else {
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pei_ptr->data_to_save = GET_GUID_HOB_DATA(mrc_hob);
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pei_ptr->data_to_save_size = ALIGN(
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((u32)GET_HOB_LENGTH(mrc_hob)), 16);
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}
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}
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/* Initialize the UPD parameters for MemoryInit */
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__attribute__((weak)) void mainboard_memory_init_params(
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struct romstage_params *params,
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MEMORY_INIT_UPD *upd_ptr)
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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}
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/* Display the UPD parameters for MemoryInit */
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__attribute__((weak)) void soc_display_memory_init_params(
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const MEMORY_INIT_UPD *old, MEMORY_INIT_UPD *new)
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{
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printk(BIOS_SPEW, "UPD values for MemoryInit:\n");
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hexdump32(BIOS_SPEW, new, sizeof(*new));
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}
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/* Initialize the UPD parameters for MemoryInit */
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__attribute__((weak)) void soc_memory_init_params(
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struct romstage_params *params,
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MEMORY_INIT_UPD *upd)
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{
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printk(BIOS_DEBUG, "WEAK: %s/%s called\n", __FILE__, __func__);
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}
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