FSP 1.1: Move common FSP code
Move the FSP common code from the src/soc/intel/common directory into the src/drivers/intel/fsp1_1 directory. Rename the Kconfig values associated with this common code. BRANCH=none BUG=None TEST=Build and run on kunimitsu Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a Signed-off-by: Patrick Georgi <pgeorgi@chromium.org> Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440 Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293 Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com> Original-Reviewed-on: https://chromium-review.googlesource.com/306350 Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com> Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/12156 Tested-by: build bot (Jenkins) Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
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Lee Leahy
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Patrick Georgi
Patrick Georgi
parent
597de2849d
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183
src/drivers/intel/fsp1_1/stack.c
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183
src/drivers/intel/fsp1_1/stack.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Google Inc.
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* Copyright (C) 2015 Intel Corp.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <cbmem.h>
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#include <console/console.h>
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#include <cpu/x86/mtrr.h>
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#include <fsp/memmap.h>
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#include <fsp/romstage.h>
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#include <fsp/stack.h>
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#include <soc/intel/common/util.h>
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#include <stdlib.h>
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const unsigned long romstage_ram_stack_size = CONFIG_ROMSTAGE_RAM_STACK_SIZE;
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/*
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* Romstage needs quite a bit of stack for decompressing images since the lzma
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* lib keeps its state on the stack during romstage.
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*/
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static unsigned long choose_top_of_stack(void)
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{
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unsigned long stack_top;
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/* cbmem_add() does a find() before add(). */
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stack_top = (unsigned long)cbmem_add(CBMEM_ID_ROMSTAGE_RAM_STACK,
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romstage_ram_stack_size);
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stack_top += romstage_ram_stack_size;
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return stack_top;
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}
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/*
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* setup_stack_and_mtrrs() determines the stack to use after
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* cache-as-ram is torn down as well as the MTRR settings to use.
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*/
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void *setup_stack_and_mtrrs(void)
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{
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size_t alignment;
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uint32_t aligned_ram;
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uint32_t mtrr_mask_upper;
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uint32_t max_mtrrs;
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uint32_t num_mtrrs;
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uint32_t *slot;
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unsigned long top_of_stack;
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/* Display the MTTRs */
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soc_display_mtrrs();
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/* Top of stack needs to be aligned to a 8-byte boundary. */
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top_of_stack = choose_top_of_stack();
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slot = (void *)top_of_stack;
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num_mtrrs = 0;
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max_mtrrs = soc_get_variable_mtrr_count(NULL);
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/*
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* The upper bits of the MTRR mask need to set according to the number
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* of physical address bits.
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*/
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mtrr_mask_upper = (1 << ((cpuid_eax(0x80000008) & 0xff) - 32)) - 1;
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alignment = mmap_region_granluarity();
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aligned_ram = ALIGN_DOWN(top_of_stack - romstage_ram_stack_size,
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alignment);
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/*
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* The order for each MTRR is value then base with upper 32-bits of
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* each value coming before the lower 32-bits. The reasoning for
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* this ordering is to create a stack layout like the following:
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*
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* +36: MTRR mask 1 63:32
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* +32: MTRR mask 1 31:0
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* +28: MTRR base 1 63:32
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* +24: MTRR base 1 31:0
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* +20: MTRR mask 0 63:32
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* +16: MTRR mask 0 31:0
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* +12: MTRR base 0 63:32
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* +8: MTRR base 0 31:0
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* +4: Number of MTRRs to setup (described above)
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* +0: Number of variable MTRRs to clear
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*/
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/* Cache RAM as WB from 0 -> CONFIG_RAMTOP. */
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slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push32(slot, ~(CONFIG_RAMTOP - 1) | MTRR_PHYS_MASK_VALID);
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slot = stack_push32(slot, 0); /* upper base */
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slot = stack_push32(slot, 0 | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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/*
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* +-------------------------+ Top of RAM (aligned)
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* | System Management Mode |
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* | code and data | Length: CONFIG_TSEG_SIZE
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* | (TSEG) |
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* +-------------------------+ SMM base (aligned)
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* | |
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* | Chipset Reserved Memory | Length: Multiple of CONFIG_TSEG_SIZE
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* | |
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* +-------------------------+ top_of_ram (aligned)
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* | |
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* | CBMEM Root |
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* | |
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* +-------------------------+
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* | |
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* | FSP Reserved Memory |
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* | |
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* +-------------------------+
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* | |
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* | Various CBMEM Entries |
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* | |
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* +-------------------------+ top_of_stack (8 byte aligned)
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* | |
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* | stack (CBMEM Entry) |
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* | |
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* +-------------------------+
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*/
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/*
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* Cache the stack and the other CBMEM entries as well as part or all
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* of the FSP reserved memory region.
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*/
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slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
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slot = stack_push32(slot, 0); /* upper base */
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slot = stack_push32(slot, aligned_ram | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
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void *smm_base;
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size_t smm_size;
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uint32_t tseg_base;
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/*
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* Cache the TSEG region at the top of ram. This region is not
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* restricted to SMM mode until SMM has been relocated. By setting
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* the region to cacheable it provides faster access when relocating
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* the SMM handler as well as using the TSEG region for other purposes.
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*/
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smm_region(&smm_base, &smm_size);
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tseg_base = (uint32_t)smm_base;
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slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push32(slot, ~(alignment - 1) | MTRR_PHYS_MASK_VALID);
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slot = stack_push32(slot, 0); /* upper base */
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slot = stack_push32(slot, tseg_base | MTRR_TYPE_WRBACK);
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num_mtrrs++;
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#endif
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/* Cache the ROM as WP just below 4GiB. */
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slot = stack_push32(slot, mtrr_mask_upper); /* upper mask */
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slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_PHYS_MASK_VALID);
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slot = stack_push32(slot, 0); /* upper base */
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slot = stack_push32(slot, ~(CONFIG_ROM_SIZE - 1) | MTRR_TYPE_WRPROT);
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num_mtrrs++;
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/* Validate the MTRR usage */
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if (num_mtrrs > max_mtrrs) {
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printk(BIOS_ERR, "MTRRs: max = %d, used = %d, available=%d",
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max_mtrrs, num_mtrrs, max_mtrrs - num_mtrrs);
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die("ERROR - MTRR use count incorrect!\n");
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}
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/*
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* Save the number of MTRRs to setup and clear. Return the stack
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* location pointing to the number of MTRRs.
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*/
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slot = stack_push32(slot, num_mtrrs);
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slot = stack_push32(slot, max_mtrrs);
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return slot;
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}
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