FSP 1.1: Move common FSP code

Move the FSP common code from the src/soc/intel/common directory into
the src/drivers/intel/fsp1_1 directory.  Rename the Kconfig values
associated with this common code.

BRANCH=none
BUG=None
TEST=Build and run on kunimitsu

Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440
Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306350
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12156
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>

src/soc/intel/skylake/Kconfig

@@ -19,6 +19,10 @@ config CPU_SPECIFIC_OPTIONS
 	select COLLECT_TIMESTAMPS
 	select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
 	select CPU_MICROCODE_IN_CBFS
+	select FSP_RAM_INIT
+	select FSP_ROMSTAGE
+	select FSP_STACK
+	select FSP_STAGE_CACHE
 	select GENERIC_GPIO_LIB
 	select HAS_PRECBMEM_TIMESTAMP_REGION
 	select HAVE_HARD_RESET
@@ -39,11 +43,7 @@ config CPU_SPECIFIC_OPTIONS
 	select RELOCATABLE_RAMSTAGE
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
-	select SOC_INTEL_COMMON_FSP_RAM_INIT
-	select SOC_INTEL_COMMON_FSP_ROMSTAGE
 	select SOC_INTEL_COMMON_RESET
-	select SOC_INTEL_COMMON_STACK
-	select SOC_INTEL_COMMON_STAGE_CACHE
 	select SMM_MODULES
 	select SMM_TSEG
 	select SMP

src/soc/intel/skylake/include/soc/ramstage.h

@@ -23,7 +23,7 @@
 
 #include <chip.h>
 #include <device/device.h>
-#include <soc/intel/common/ramstage.h>
+#include <fsp/ramstage.h>
 
 void pch_enable_dev(device_t dev);
 void soc_init_pre_device(void *chip_info);

src/soc/intel/skylake/include/soc/romstage.h

@@ -21,7 +21,7 @@
 #ifndef _SOC_ROMSTAGE_H_
 #define _SOC_ROMSTAGE_H_
 
-#include <soc/intel/common/romstage.h>
+#include <fsp/romstage.h>
 
 struct chipset_power_state;
 struct chipset_power_state *fill_power_state(void);

src/soc/intel/skylake/include/soc/smm.h

@@ -23,8 +23,8 @@
 
 #include <stdint.h>
 #include <cpu/x86/msr.h>
-#include <soc/intel/common/romstage.h>
-#include <soc/intel/common/memmap.h>
+#include <fsp/memmap.h>
+#include <fsp/romstage.h>
 #include <soc/gpio.h>
 
 struct ied_header {

src/soc/intel/skylake/ramstage.c

@@ -19,7 +19,6 @@
  */
 
 #include <soc/ramstage.h>
-#include <soc/intel/common/ramstage.h>
 
 void soc_init_pre_device(void *chip_info)
 {