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FSP 1.1: Move common FSP code

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Move the FSP common code from the src/soc/intel/common directory into
the src/drivers/intel/fsp1_1 directory.  Rename the Kconfig values
associated with this common code.

BRANCH=none
BUG=None
TEST=Build and run on kunimitsu

Change-Id: If1ca613b5010424c797e047c2258760ac3724a5a
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: e8228cb2a12df1cc06646071fafe10e50bf01440
Original-Change-Id: I4ea84ea4e3e96ae0cfdbbaeb1316caee83359293
Original-Signed-off-by: Lee Leahy <Leroy.P.Leahy@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/306350
Original-Commit-Ready: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Tested-by: Leroy P Leahy <leroy.p.leahy@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/12156
Tested-by: build bot (Jenkins)
Reviewed-by: Leroy P Leahy <leroy.p.leahy@intel.com>
This commit is contained in:
Lee Leahy
2015-10-15 12:07:03 -07:00
committed by Patrick Georgi
parent 597de2849d
commit 94b856ef9a
33 changed files with 106 additions and 115 deletions
Download Patch File Download Diff File Expand all files Collapse all files

8
src/soc/intel/skylake/Kconfig
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@@ -19,6 +19,10 @@ config CPU_SPECIFIC_OPTIONS
select COLLECT_TIMESTAMPS
select CPU_INTEL_FIRMWARE_INTERFACE_TABLE
select CPU_MICROCODE_IN_CBFS
select FSP_RAM_INIT
select FSP_ROMSTAGE
select FSP_STACK
select FSP_STAGE_CACHE
select GENERIC_GPIO_LIB
select HAS_PRECBMEM_TIMESTAMP_REGION
select HAVE_HARD_RESET
@@ -39,11 +43,7 @@ config CPU_SPECIFIC_OPTIONS
select RELOCATABLE_RAMSTAGE
select SOC_INTEL_COMMON
select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
select SOC_INTEL_COMMON_FSP_RAM_INIT
select SOC_INTEL_COMMON_FSP_ROMSTAGE
select SOC_INTEL_COMMON_RESET
select SOC_INTEL_COMMON_STACK
select SOC_INTEL_COMMON_STAGE_CACHE
select SMM_MODULES
select SMM_TSEG
select SMP