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soc/intel/quark: Fix errors detected by checkpatch

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Fix the errors detected by checkpatch and update the copyright dates.

TEST=Build and run on Galileo Gen2

Change-Id: Idad062eaeca20519394c2cd24d803c546d8e0ae0
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/18591
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Lee Leahy
2017-03-06 08:59:23 -08:00
parent a24c81cd30
commit 94b971a909
10 changed files with 292 additions and 250 deletions
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6
src/soc/intel/quark/chip.h
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@@ -3,7 +3,7 @@
*
* Copyright (C) 2007-2008 coresystems GmbH
* Copyright (C) 2014 Google Inc.
* Copyright (C) 2015 Intel Corporation.
* Copyright (C) 2015-2017 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -41,7 +41,7 @@ struct soc_intel_quark_config {
* MemoryInit:
*
* The following fields come from FspUpdVpd.h and are defined as PCDs
* for the FSP binary. Data for these fields comes from the board's
* for the FSP binary. Data for these fields comes from the board's
* devicetree.cb file which gets processed into static.c and then
* built into the coreboot image. The fields below contain retain
* the FSP PCD field name.
@@ -90,7 +90,7 @@ struct soc_intel_quark_config {
* impedance control.
*/
uint8_t DramRonVal;
uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RESERVED */
uint8_t DramRttNomVal; /* 0=40ohm, 1=60ohm, 2=120ohm, others=RSVD */
uint8_t DramRttWrVal; /* 0=off others=RESERVED */
/* 0=off, 1=60ohm, 2=120ohm, 3=180ohm, others=RESERVED */