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glados: move to native gpio configuration

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Instead of relying on FSP to do gpio configuration in one
place use the native support in coreboot. This also removes
the open coded configuration of the memory configuration
ids.

BUG=chrome-os-partner:42982
BRANCH=None
TEST=Built and booted glados.

Original-Change-Id: I4655221d821d91a2270d774305a02d6bd5c3959c
Original-Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-on: https://chromium-review.googlesource.com/289800
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

Change-Id: I2e66242d050c3825f6bc65d3d2c7f51d2cdfbd73
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: http://review.coreboot.org/11175
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Aaron Durbin
2015-07-24 13:06:12 -05:00
parent ffdf901c76
commit 9506aea351
4 changed files with 177 additions and 320 deletions
Download Patch File Download Diff File Expand all files Collapse all files

448
src/mainboard/google/glados/gpio.h
View File

@@ -2,7 +2,6 @@
* This file is part of the coreboot project. * This file is part of the coreboot project.
* *
* Copyright (C) 2015 Google Inc. * Copyright (C) 2015 Google Inc.
* Copyright (C) 2015 Intel Corporation
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by * it under the terms of the GNU General Public License as published by
@@ -23,293 +22,176 @@
#include <soc/gpio.h> #include <soc/gpio.h>
const GPIO_INIT_CONFIG mainboard_gpio_table[] = { static const struct pad_config gpio_table[] = {
/* RCIN# */ /* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
{GPIO_LP_GPP_A0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, /* LAD0 */ PAD_CFG_NF(GPP_A1, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* LAD1 */ PAD_CFG_NF(GPP_A2, NONE, DEEP, NF1),
/* LAD0 */ /* LAD2 */ PAD_CFG_NF(GPP_A3, NONE, DEEP, NF1),
{GPIO_LP_GPP_A1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, /* LAD3 */ PAD_CFG_NF(GPP_A4, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
/* LAD1 */ /* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
{GPIO_LP_GPP_A2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, /* PIRQA# */ /* GPP_A7 */
GpioOutDefault, GpioIntDis, GpioTermNone}}, /* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
/* LAD2 */ /* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
{GPIO_LP_GPP_A3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, /* CLKOUT_LPC1 */ /* GPP_A10 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* PME# */ /* GPP_A11 */
/* LAD3 */ /* BM_BUSY# */ /* GPP_A12 */
{GPIO_LP_GPP_A4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, /* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* SUS_STAT# */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* LFRAME# */ /* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
{GPIO_LP_GPP_A5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* SD_PWR_EN# */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
/* SERIRQ */ /* ISH_GP0 */ /* GPP_A18 */
{GPIO_LP_GPP_A6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, /* ISH_GP1 */ /* GPP_A19 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* ISH_GP2 */ /* GPP_A20 */
/* CLKRUN# */ /* ISH_GP3 */ /* GPP_A21 */
{GPIO_LP_GPP_A8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, /* ISH_GP4 */ /* GPP_A22 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* ISH_GP5 */ /* GPP_A23 */
/* CLKOUT_LPC0 */ /* CORE_VID0 */ /* GPP_B0 */
{GPIO_LP_GPP_A9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* CORE_VID1 */ /* GPP_B1 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* VRALERT# */ /* GPP_B2 */
/* SUSWARN# tied to SUSACK# */ /* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP), /* TRACKPAD */
{GPIO_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, /* CPU_GP3 */ /* GPP_B4 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* SRCCLKREQ0# */ /* GPP_B5 */
/* SUS_STAT# TP27 */ /* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN */
{GPIO_LP_GPP_A13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* SRCCLKREQ3# */ /* GPP_B8 */
/* SUSACK# tied to SUSWARN# */ /* SRCCLKREQ4# */ /* GPP_B9 */
{GPIO_LP_GPP_A15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, /* SRCCLKREQ5# */ /* GPP_B10 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* EXT_PWR_GATE# */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
/* SD_1P8_SEL */ /* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
{GPIO_LP_GPP_A16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, /* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* SPKR */ /* GPP_B14 */
/* SD_PWR_EN# */ /* GSPI0_CS# */ /* GPP_B15 */
{GPIO_LP_GPP_A17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirNone, /* GSPI0_CLK */ PAD_CFG_GPI_APIC(GPP_B16, NONE, DEEP), /* WLAN WAKE */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* GSPI0_MISO */ /* GPP_B17 */
/* TRACKPAD_INT_L */ /* GSPI0_MOSI */ /* GPP_B18 */
{GPIO_LP_GPP_B3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, /* GSPI1_CS# */ /* GPP_B19 */
GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep, /* GSPI1_CLK */ /* GPP_B20 */
GpioTermNone}}, /* GSPI1_MISO */ /* GPP_B21 */
/* SRCCLKREQ1# / WLAN_PCIE_CLKREQ_L */ /* GSPI1_MOSI */ /* GPP_B22 */
{GPIO_LP_GPP_B6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, /* SM1ALERT# */ /* GPP_B23 */
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, /* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
/* SRCCLKREQ2# / KEPLER_PCIE_CLKREQ_L */ /* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
{GPIO_LP_GPP_B7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, /* SMBALERT# */ /* GPP_C2 */
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, /* SML0CLK */ /* GPP_C3 */
/* EXT_PWR_GATE# */ /* SML0DATA */ /* GPP_C4 */
{GPIO_LP_GPP_B11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* SML0ALERT# */ /* GPP_C5 */
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}}, /* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
/* SLP_S0# */ /* SM1DATA */ /* GPP_C7 */
{GPIO_LP_GPP_B12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* UART0_RXD */ /* GPP_C8 */
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* UART0_TXD */ /* GPP_C9 */
/* PLTRST# */ /* UART0_RTS# */ /* GPP_C10 */
{GPIO_LP_GPP_B13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 1, DEEP), /* EN_PP3300_KEPLER */
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
/* WLAN_PCIE_WAKE_L */ /* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
{GPIO_LP_GPP_B16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, /* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}}, /* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
/* SMBCLK (XDP) */ /* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
{GPIO_LP_GPP_C0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */
/* SMBDATA (XDP) */ /* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TRACKPAD */
{GPIO_LP_GPP_C1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
/* EC_IN_RW */ /* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */
{GPIO_LP_GPP_C6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, /* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermWpu20K}}, /* GPP_D0 */
/* EN_PP3300_KEPLER */ /* GPP_D1 */
{GPIO_LP_GPP_C11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, /* GPP_D2 */
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, /* GPP_D3 */
/* PCH_MEM_CONFIG[0] */ /* FASHTRIG */ /* GPP_D4 */
{GPIO_LP_GPP_C12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, /* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */
/* PCH_MEM_CONFIG[1] */ /* ISH_I2C1_SDA */ /* GPP_D7 */
{GPIO_LP_GPP_C13, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, /* ISH_I2C1_SCL */ /* GPP_D8 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* GPP_D9 */
/* PCH_MEM_CONFIG[2] */ PAD_CFG_GPO(GPP_D10, 1, DEEP), /* USBA_1_ILIM_SEL_L */
{GPIO_LP_GPP_C14, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, PAD_CFG_GPO(GPP_D11, 1, DEEP), /* USBA_2_ILIM_SEL_L */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */
/* PCH_MEM_CONFIG[3] */ /* ISH_UART0_RXD */ /* GPP_D13 */
{GPIO_LP_GPP_C15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, /* ISH_UART0_TXD */ /* GPP_D14 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* ISH_UART0_RTS# */ /* GPP_D15 */
/* I2C0_SDA */ /* ISH_UART0_CTS# */ /* GPP_D16 */
{GPIO_LP_GPP_C16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, /* DMIC_CLK1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* DMIC_DATA1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
/* I2C0_SCL */ /* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
{GPIO_LP_GPP_C17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* GPP_D21 */
/* I2C1 SDA */ /* GPP_D22 */
{GPIO_LP_GPP_C18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, /* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP), /* TPM_PIRQ_L */
/* I2C1 SDA */ /* SATAXPCIE1 */ /* GPP_E1 */
{GPIO_LP_GPP_C19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* SATAXPCIE2 */ /* GPP_E2 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* CPU_GP0 */ /* GPP_E3 */
/* UART2_RXD */ /* SATA_DEVSLP0 */ /* GPP_E4 */
{GPIO_LP_GPP_C20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn, /* SATA_DEVSLP1 */ /* GPP_E5 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* SATA_DEVSLP2 */ /* GPP_E6 */
/* UART2_TXD */ /* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP), /* TOUCHSCREEN */
{GPIO_LP_GPP_C21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* SATALED# */ /* GPP_E8 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* EN_PP3300_DX_TOUCHSCREEN */ /* USB2_OC1# */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
{GPIO_LP_GPP_C22, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, /* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermWpd20K}}, /* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
/* PCH_WP */ /* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
{GPIO_LP_GPP_C23, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, /* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermWpu20K}}, /* DDPD_HPD2 */ PAD_CFG_NF(GPP_E15, NONE, DEEP, NF1),
/* EN_PP3300_DX_EMMC */ /* DDPE_HPD3 */ PAD_CFG_NF(GPP_E16, NONE, DEEP, NF1),
{GPIO_LP_GPP_D5, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, /* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* DDPB_CTRLCLK */ /* GPP_E18 */
/* EN_PP1800_DX_EMMC */ /* DDPB_CTRLDATA */ /* GPP_E19 */
{GPIO_LP_GPP_D6, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, /* DDPC_CTRLCLK */ /* GPP_E20 */
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* DDPC_CTRLDATA */ /* GPP_E21 */
/* USBA_1_ILIM_SEL_L */ /* GPP_E22 */
{GPIO_LP_GPP_D10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut, /* GPP_E23 */
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* USBA_2_ILIM_SEL_L */
{GPIO_LP_GPP_D11, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* EN_PP3300_DX_CAM */
{GPIO_LP_GPP_D12, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirOut,
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* DMIC_CLK1 */
{GPIO_LP_GPP_D17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* DMIC_DATA1 */
{GPIO_LP_GPP_D18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* DMIC_CLK0 */
{GPIO_LP_GPP_D19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* DMIC_DATA0 */
{GPIO_LP_GPP_D20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* I2S_MCLK */
{GPIO_LP_GPP_D23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* TPM_PIRQ_L */
{GPIO_LP_GPP_E0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
/* TOUCHSCREEN_INT_L */
{GPIO_LP_GPP_E7, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, (GpioIntApic | GpioIntLevel), GpioResetDeep,
GpioTermNone}},
/* USB2_OC0# */
{GPIO_LP_GPP_E9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
/* USB2_OC1# */
{GPIO_LP_GPP_E10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
/* USB2_OC2# */
{GPIO_LP_GPP_E11, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
/* USB2_OC3# */
{GPIO_LP_GPP_E12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
/* DDPB_HPD0 */
{GPIO_LP_GPP_E13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
/* DDPC_HPD1 */
{GPIO_LP_GPP_E14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
/* EC_SMI_L */
{GPIO_LP_GPP_E15, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
/* EC_SCI_L */
{GPIO_LP_GPP_E16, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
/* EDP_HPD */
{GPIO_LP_GPP_E17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
/* /*
* The next 4 pads are for bit banging the amplifiers. They are connected * The next 4 pads are for bit banging the amplifiers. They are connected
* together with i2s0 signals. For default behavior of i2s make these * together with i2s0 signals. For default behavior of i2s make these
* gpio inupts. * gpio inupts.
*/ */
/* I2S2_SCLK */ /* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
{GPIO_LP_GPP_F0, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, /* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
/* I2S2_SFRM */ /* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
{GPIO_LP_GPP_F1, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, /* I2C2_SDA */ /* GPP_F4 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* I2C2_SCL */ /* GPP_F5 */
/* I2S2_TXD */ /* I2C3_SDA */ /* GPP_F6 */
{GPIO_LP_GPP_F2, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, /* I2C3_SCL */ /* GPP_F7 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1), /* Amplifiers */
/* I2S2_RXD */ /* I2C4_SCL */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1), /* Amplifiers */
{GPIO_LP_GPP_F3, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirIn, /* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP), /* MIC_INT_L */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* I2C5_SCL */ /* GPP_F11 */
/* I2C4_SDA */ /* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
{GPIO_LP_GPP_F8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, /* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
/* I2C4_SCL */ /* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
{GPIO_LP_GPP_F9, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut, /* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
/* MIC_INT_L */ /* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
{GPIO_LP_GPP_F10, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirInInv, /* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
GpioOutDefault, (GpioIntApic | GpioIntEdge), GpioResetDeep, /* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
GpioTermNone}}, /* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* EMMC_CMD */ /* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
{GPIO_LP_GPP_F12, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* GPP_F23 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* SD_CMD */ PAD_CFG_NF(GPP_G0, NONE, DEEP, NF1),
/* EMMC_DATA0 */ /* SD_DATA0 */ PAD_CFG_NF(GPP_G1, NONE, DEEP, NF1),
{GPIO_LP_GPP_F13, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* SD_DATA1 */ PAD_CFG_NF(GPP_G2, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* SD_DATA2 */ PAD_CFG_NF(GPP_G3, NONE, DEEP, NF1),
/* EMMC_DATA1 */ /* SD_DATA3 */ PAD_CFG_NF(GPP_G4, NONE, DEEP, NF1),
{GPIO_LP_GPP_F14, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* SD_CD# */ PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* SD_CLK */ PAD_CFG_NF(GPP_G6, NONE, DEEP, NF1),
/* EMMC_DATA2 */ /* SD_WP */ PAD_CFG_NF(GPP_G7, NONE, DEEP, NF1),
{GPIO_LP_GPP_F15, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* BATLOW# */ /* GPD0 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
/* EMMC_DATA3 */ /* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
{GPIO_LP_GPP_F16, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
/* EMMC_DATA4 */ /* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
{GPIO_LP_GPP_F17, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* SLP_A# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* GPD7 */
/* EMMC_DATA5 */ /* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
{GPIO_LP_GPP_F18, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut, /* SLP_WLAN# */ /* GPD9 */
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}}, /* SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
/* EMMC_DATA6 */ /* LANPHYC */ /* GPD11 */
{GPIO_LP_GPP_F19, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* EMMC_DATA7 */
{GPIO_LP_GPP_F20, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* EMMC_RCLK */
{GPIO_LP_GPP_F21, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* EMMC_CLK */
{GPIO_LP_GPP_F22, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* EMMC_CMD */
{GPIO_LP_GPP_F23, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* SD_CMD */
{GPIO_LP_GPP_G0, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* SD_DATA0 */
{GPIO_LP_GPP_G1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* SD_DATA1 */
{GPIO_LP_GPP_G2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* SD_DATA2 */
{GPIO_LP_GPP_G3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* SD_DATA3 */
{GPIO_LP_GPP_G4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirInOut,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* SD_CD# */
{GPIO_LP_GPP_G5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* SD_CLK# */
{GPIO_LP_GPP_G6, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
/* SD_WP# */
{GPIO_LP_GPP_G7, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
/* ACPRESENT# */
{GPIO_LP_GPD1, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
/* EC_PCH_WAKE_L */
{GPIO_LP_GPD2, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntEdge, GpioResetDeep, GpioTermNone}},
/* PWRBTN# */
{GPIO_LP_GPD3, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirIn,
GpioOutDefault, GpioIntLevel, GpioResetDeep, GpioTermNone}},
/* SLP_S3# */
{GPIO_LP_GPD4, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* SLP_S4# */
{GPIO_LP_GPD5, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutHigh, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* SUSCLK */
{GPIO_LP_GPD8, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}},
/* SLP_S5# */
{GPIO_LP_GPD10, {GpioPadModeNative1, GpioHostOwnGpio, GpioDirOut,
GpioOutLow, GpioIntDis, GpioResetDeep, GpioTermNone}},
{END_OF_GPIO_TABLE, {GpioPadModeGpio, GpioHostOwnGpio, GpioDirNone,
GpioOutDefault, GpioIntDis, GpioResetPwrGood, GpioTermNone}},
}; };
#endif #endif

4
src/mainboard/google/glados/mainboard.c
View File

@@ -20,10 +20,14 @@
*/ */
#include <device/device.h> #include <device/device.h>
#include <stdlib.h>
#include "ec.h" #include "ec.h"
#include "gpio.h"
static void mainboard_init(device_t dev) static void mainboard_init(device_t dev)
{ {
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
if (IS_ENABLED(CONFIG_GOOGLE_CHROME_EC)) if (IS_ENABLED(CONFIG_GOOGLE_CHROME_EC))
mainboard_ec_init(); mainboard_ec_init();
} }

2
src/mainboard/google/glados/ramstage.c
View File

@@ -19,9 +19,7 @@
*/ */
#include <soc/ramstage.h> #include <soc/ramstage.h>
#include "gpio.h"
void mainboard_silicon_init_params(SILICON_INIT_UPD *params) void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
{ {
params->GpioTablePtr = (UINT32 *)mainboard_gpio_table;
} }

43
src/mainboard/google/glados/spd/spd.c
View File

@@ -21,10 +21,9 @@
#include <arch/byteorder.h> #include <arch/byteorder.h>
#include <cbfs.h> #include <cbfs.h>
#include <console/console.h> #include <console/console.h>
#include <gpio.h>
#include <string.h> #include <string.h>
#include <soc/gpio.h>
#include <soc/pei_data.h> #include <soc/pei_data.h>
#include <soc/pcr.h>
#include <soc/romstage.h> #include <soc/romstage.h>
#include "spd.h" #include "spd.h"
@@ -85,42 +84,16 @@ void mainboard_fill_spd_data(struct pei_data *pei_data)
char *spd_file; char *spd_file;
size_t spd_file_len; size_t spd_file_len;
int spd_index; int spd_index;
int spd_gpio[4];
/************************************************************* gpio_t spd_gpios[] = {
* FIXME: Remove when real GPIO support is ready. GPP_C12, /* PCH_MEM_CONFIG[0] */
*/ GPP_C13, /* PCH_MEM_CONFIG[1] */
GPIO_PAD gpio_set[4] = { GPP_C14, /* PCH_MEM_CONFIG[2] */
GPIO_LP_GPP_C12, /* PCH_MEM_CONFIG[0] */ GPP_C15, /* PCH_MEM_CONFIG[3] */
GPIO_LP_GPP_C13, /* PCH_MEM_CONFIG[1] */
GPIO_LP_GPP_C14, /* PCH_MEM_CONFIG[2] */
GPIO_LP_GPP_C15, /* PCH_MEM_CONFIG[3] */
}; };
int index;
for (index = 0; index < ARRAY_SIZE(gpio_set); index++) { spd_index = gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios));
u32 number = GPIO_GET_PAD_NUMBER(gpio_set[index]); printk(BIOS_ERR, "SPD index %d\n", spd_index);
u32 cfgreg = 8 * number + R_PCH_PCR_GPIO_GPP_C_PADCFG_OFFSET;
/*
* Set GPIO mode and enable input
* Clear PMODE0 | PMODE1 | GPIORXDIS
*/
u32 dw0mask = (1 << 10) | (1 << 11) | (1 << 9);
u32 dw0reg = 0;
pcr_andthenor32(PID_GPIOCOM1, cfgreg, ~dw0mask, dw0reg);
/* Read current input value */
pcr_read32(PID_GPIOCOM1, cfgreg, &dw0reg);
spd_gpio[index] = !!(dw0reg & (1 << 1));
}
/*************************************************************/
spd_index = (spd_gpio[3] << 3) | (spd_gpio[2] << 2) |
(spd_gpio[1] << 1) | spd_gpio[0];
printk(BIOS_DEBUG,
"SPD: index %d (GPP_C15=%d GPP_C14=%d GPP_C13=%d GPP_C12=%d)\n",
spd_index, spd_gpio[3], spd_gpio[2], spd_gpio[1], spd_gpio[0]);
/* Load SPD data from CBFS */ /* Load SPD data from CBFS */
spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD,