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src/mainboard/emulation/qemu-power9: require hb-mode=on

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"hb-mode" is a -machine flag for QEMU. "hb" stands for Hostboot, which
is OpenPower firmware created by IBM.

QEMU for PPC64 can run initial program in two different modes:
 * hb-mode=off with load address 0x00000000
 * hb-mode=on with load address 0x08000000

Real hardware always loads firmware at 0x08000000 and coreboot shouldn't
require a special build to be run on QEMU.

Memory layout is updated to reflect change of load address.

Change-Id: I1bdc97a095bd46fccc862985b3bd24f4fa5bc054
Signed-off-by: Yaroslav Kurlaev <yaroslav.kurlaev@3mdeb.com>
Signed-off-by: Sergii Dmytruk <sergii.dmytruk@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57082
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Yaroslav Kurlaev
2021-07-06 22:38:37 +07:00
committed by Felix Held
parent bcbcdf7394
commit 956a8b69d2
4 changed files with 36 additions and 11 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/arch/ppc64/include/arch/io.h
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@@ -8,7 +8,9 @@
/* Set MSB to 1 to ignore HRMOR */ /* Set MSB to 1 to ignore HRMOR */
#define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000 #define MMIO_GROUP0_CHIP0_LPC_BASE_ADDR 0x8006030000000000
#define LPCHC_IO_SPACE 0xD0010000 #define LPCHC_IO_SPACE 0xD0010000
#define FLASH_IO_SPACE 0xFC000000
#define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE) #define LPC_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + LPCHC_IO_SPACE)
#define FLASH_BASE_ADDR (MMIO_GROUP0_CHIP0_LPC_BASE_ADDR + FLASH_IO_SPACE)
#define MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR 0x800603FC00000000 #define MMIO_GROUP0_CHIP0_SCOM_BASE_ADDR 0x800603FC00000000
/* Enforce In-order Execution of I/O */ /* Enforce In-order Execution of I/O */

5
src/arch/ppc64/rom_media.c
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@@ -1,11 +1,10 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/io.h>
#include <boot_device.h> #include <boot_device.h>
/* This assumes that the CBFS resides at 0x0, which is true for the default
* configuration. */
static const struct mem_region_device boot_dev = static const struct mem_region_device boot_dev =
MEM_REGION_DEV_RO_INIT(NULL, CONFIG_ROM_SIZE); MEM_REGION_DEV_RO_INIT(FLASH_BASE_ADDR, CONFIG_ROM_SIZE);
const struct region_device *boot_device_ro(void) const struct region_device *boot_device_ro(void)
{ {

13
src/arch/ppc64/stages.c
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@@ -13,10 +13,23 @@
#include <cbmem.h> #include <cbmem.h>
#include <arch/stages.h> #include <arch/stages.h>
#include <cpu/power/spr.h>
void stage_entry(uintptr_t stage_arg) void stage_entry(uintptr_t stage_arg)
{ {
#if ENV_RAMSTAGE
uint64_t hrmor;
#endif
if (!ENV_ROMSTAGE_OR_BEFORE) if (!ENV_ROMSTAGE_OR_BEFORE)
_cbmem_top_ptr = stage_arg; _cbmem_top_ptr = stage_arg;
#if ENV_RAMSTAGE
hrmor = read_spr(SPR_HRMOR);
asm volatile("sync; isync" ::: "memory");
write_spr(SPR_HRMOR, 0);
asm volatile("or 1,1,%0; slbia 7; sync; isync" :: "r"(hrmor) : "memory");
#endif
main(); main();
} }

27
src/mainboard/emulation/qemu-power9/memlayout.ld
View File

@@ -10,14 +10,25 @@ SECTIONS
BOOTBLOCK(0, 32K) BOOTBLOCK(0, 32K)
ROMSTAGE(0xf00000, 1M) ROMSTAGE(0x1f00000, 1M)
STACK(0x1000000, 32K)
RAMSTAGE(0x1008000, 1M)
FMAP_CACHE(0x1108000, 4K) #if !ENV_RAMSTAGE
CBFS_MCACHE(0x1109000, 8K) STACK(0x2000000, 32K)
TIMESTAMP(0x110b000, 4K) #endif
CBFS_CACHE(0x110c000, 512K)
PRERAM_CBMEM_CONSOLE(0x118c000, 128K)
FMAP_CACHE(0x2108000, 4K)
CBFS_MCACHE(0x2109000, 8K)
TIMESTAMP(0x210b000, 4K)
CBFS_CACHE(0x210c000, 512K)
PRERAM_CBMEM_CONSOLE(0x218c000, 128K)
/* By default all memory addresses are affected by the value of HRMOR
* (Hypervisor Real Mode Offset Register) which is ORed to them. HRMOR
* has initial value of 0x8000000 in QEMU and is changed to 0 in
* ramstage. This means that before ramstage 0 actually points to
* 0x8000000. */
#if ENV_RAMSTAGE
STACK(0xa000000, 32K)
#endif
RAMSTAGE(0xa008000, 1M)
} }