Merge branch 'master' into system76_cleanup

Change-Id: Ida07401fa877243cc64fae9ac96a65b5a58d01ab

.clang-format

@@ -7,7 +7,7 @@ AllowShortIfStatementsOnASingleLine:		false
 IndentCaseLabels:				false
 SortIncludes:					false
 ContinuationIndentWidth:			8
-ColumnLimit:					0
+ColumnLimit:					96
 AlwaysBreakBeforeMultilineStrings:		true
 AllowShortLoopsOnASingleLine:			false
 AllowShortFunctionsOnASingleLine:		false

.gitmodules

@@ -29,3 +29,8 @@
 [submodule "opensbi"]
 	path = 3rdparty/opensbi
 	url = https://github.com/coreboot/opensbi.git
+[submodule "intel-microcode"]
+	path = 3rdparty/intel-microcode
+	url = https://github.com/coreboot/intel-microcode.git
+	update = none
+	ignore = dirty

Documentation/arch/riscv/index.md

@@ -15,7 +15,7 @@ Payloads run from the ramstage are started in S mode, and trap delegation
 will have been done. These payloads rely on the SBI and can not replace it.
 
 ## Stage handoff protocol
-On entry to a stage or payload,
+On entry to a stage or payload (including SELF payloads),
 * all harts are running.
 * A0 is the hart ID.
 * A1 is the pointer to the Flattened Device Tree (FDT).

Documentation/drivers/index.md

@@ -0,0 +1,7 @@
+# Platform indenpendend drivers documentation
+
+The drivers can be found in `src/drivers`. They are intended for onboard
+and plugin devices, significantly reducing integration complexity and
+they allow to easily reuse existing code accross platforms.
+
+* [IPMI KCS](ipmi_kcs.md)

Documentation/drivers/ipmi_kcs.md

@@ -0,0 +1,47 @@
+# IPMI KCS driver
+
+The driver can be found in `src/drivers/ipmi/`. It works with BMC that provide
+a KCS I/O interface as specified in the [IPMI] standard.
+
+The driver detects the IPMI version, reserves the I/O space in coreboot's
+resource allocator and writes the required ACPI and SMBIOS tables.
+
+## For developers
+
+To use the driver, select the `IPMI_KCS` Kconfig and add the following PNP
+device under the LPC bridge device (in example for the KCS at 0xca2):
+
+```
+ chip drivers/ipmi
+   device pnp ca2.0 on end         # IPMI KCS
+ end
+```
+
+**Note:** The I/O base address needs to be aligned to 2.
+
+The following registers can be set:
+
+* `have_nv_storage`
+  * Boolean
+  * If true `nv_storage_device_address` will be added to SMBIOS type 38.
+* `nv_storage_device_address`
+  * Integer
+  * The NV storage address as defined in SMBIOS spec for type 38.
+* `bmc_i2c_address`
+  * Integer
+  * The i2c address of the BMC. zero if not applicable.
+* `have_apic`
+  * Boolean
+  * If true the `apic_interrupt` will be added to SPMI table.
+* `apic_interrupt`
+  * Integer
+  * The APIC interrupt used to notify about a change on the KCS.
+* `have_gpe`
+  * Boolean
+  * If true the `gpe_interrupt` will be added to SPMI table.
+* `gpe_interrupt`
+  * Integer
+  * The bit in GPE (SCI) used to notify about a change on the KCS.
+
+
+[IPMI]: https://www.intel.com/content/dam/www/public/us/en/documents/product-briefs/ipmi-second-gen-interface-spec-v2-rev1-1.pdf

Documentation/index.md

@@ -175,6 +175,7 @@ Contents:
 * [Native Graphics Initialization with libgfxinit](gfx/libgfxinit.md)
 * [Display panel-specific documentation](gfx/display-panel.md)
 * [Architecture-specific documentation](arch/index.md)
+* [Platform independend drivers documentation](drivers/index.md)
 * [Northbridge-specific documentation](northbridge/index.md)
 * [System on Chip-specific documentation](soc/index.md)
 * [Mainboard-specific documentation](mainboard/index.md)

Documentation/mainboard/asus/p8z77-m_pro.md

@@ -0,0 +1,168 @@
+# ASUS P8Z77-M Pro
+
+This page describes how to run coreboot on the [ASUS P8Z77-M Pro]
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+----------------+
+| Type                | Value          |
++=====================+================+
+| Socketed flash      | yes            |
++---------------------+----------------+
+| Model               | W25Q64FVA1Q    |
++---------------------+----------------+
+| Size                | 8 MiB          |
++---------------------+----------------+
+| Package             | DIP-8          |
++---------------------+----------------+
+| Write protection    | yes            |
++---------------------+----------------+
+| Dual BIOS feature   | no             |
++---------------------+----------------+
+| Internal flashing   | yes            |
++---------------------+----------------+
+```
+
+The flash IC is located right next to one of the SATA ports:
+![](p8z77-m_pro.jpg)
+
+### Internal programming
+
+The main SPI flash cannot be written because Asus disables BIOSWE and
+enables BLE/SMM_BWP flags in BIOS_CNTL for their latest bioses.
+An external programmer is required. You must flash standalone,
+flashing in-circuit doesn't work. The flash chip is socketed, so it's
+easy to remove and reflash.
+
+## Working
+
+- PS/2 keyboard with SeaBIOS & Tianocore (in Mint 18.3/19.1)
+
+- Rear/front headphones connector audio & mic
+
+- S3 Suspend to RAM (tested with OS installed in a HDD/SSD and also with a
+  Mint 18.3/19.1 LiveUSB pendrive connected to USB3/USB2), but please
+  see [Known issues]
+
+- USB2 on rear (tested mouse/keyboard plugged there. Also, booting with
+  a Mint 18./19.1 LiveUSB works ok)
+
+- USB3 (Z77's and Asmedia's works, but please see [Known issues])
+
+- Gigabit Ethernet (RTL8111F)
+
+- SATA3, SATA2 and eSATA (tested on all ports, hot-swap and TCG OPAL working)
+    (Blue SATA2)  (Blue SATA2)  (White SATA3)  (Red eSATA SATA3 rear)
+       port 3        port 5         port 1             port 8
+       port 4        port 6         port 2             port 7
+
+- NVME SSD boot on PCIe-x16/x8/4x slot using Tianocore
+  (tested with M.2-to-PCIe adapter and a M.2 Samsung EVO 970 SSD)
+
+- CPU Temp sensors (tested PSensor on linux + HWINFO64 on Win10)
+
+- TPM on TPM-header (tested tpm-tools with Asus TPM 1.2 Infineon SLB9635TT12)
+
+- Native raminit and also MRC.bin(systemagent-r6.bin) memory initialization
+  (please see [Native raminit compatibility] and [MRC memory compatibility])
+
+- Integrated graphics with both libgfxinit and the Intel Video BIOS OpROM
+  (VGA/DVI-D/HDMI tested and working)
+
+- 1x PCIe GPU in PCIe-16x/8x/4x slots (tested using Zotac GeForce GTX
+  750Ti and FirePro W5100 under Mint 18.3/19.1)
+
+## Known issues
+
+- The rear's USB3s on bottom (closest to the PCB) have problems booting or
+  being used before the OS loads. For better compatibility, please use
+  the Z77's ones above the Ethernet connector or the Asmedia's top one
+
+- After S3 suspend, some USB3 connectors on rear seem not to work
+
+- At the moment, the power led does not blink when entering S3 state
+
+- Currently, we have not setup the SuperIO's Hardware Monitor (HWM),
+  so only the CPU sensors are reported
+
+- If you use the MRC.bin, the NVRAM variable gfx_uma_size may be ignored
+  as IGP's UMA could be reconfigured by the blob
+
+- Using TianoCore + a PCIe GPU under Windows crashes with an
+  ACPI_BIOS_ERROR fatal code, not sure why. Using just the IGP
+  works perfectly
+
+- Under Windows 10, if you experiment problems with PS/2 devices, change
+  HKLM\SYSTEM\CurrentControlSet\Services\i8042prt->Start from '3' to '1'
+
+## Untested
+
+- EHCI debugging
+- S/PDIF audio
+- Wake-on-LAN
+- Serial port
+
+## Not working
+
+- PS/2 keyboard in Win10 using Tianocore (please see [Known issues])
+- PS/2 mouse using Tianocore
+- PCIe graphics card on Windows and Tianocore (throws critical ACPI_BIOS_ERROR)
+
+## Native raminit compatibility
+
+- GSkill F3-2133C10D-16GAB(XMP,1.60v) 2x8GB kit works at 1333Mhz instead
+  of XMP 2133Mhz
+
+- Team Xtreem TXD38G2133HC9NDC01(XMP,1.50v) 2x4GB kit works at 1600Mhz
+  instead of XMP 2133Mhz
+
+- Kingston KVR1066D3N7K2/4G(JEDEC,1.50v) 2x4GB kit works at 1066Mhz
+  but the board only detects half its RAM, because those DIMMs have
+  Double Sided(DS) chips and seems only Single Sided(SS) ones are
+  fully detected
+
+- GSkill F3-10666CL9T2-24GBRL(JEDEC,1.50v) 6x4GB kit (4 DIMMs used)
+  works perfectly at full speed (1333Mhz)
+
+## MRC memory compatibility
+
+- GSkill F3-2133C10D-16GAB(XMP,1.60v) 2x8GB kit works at 1333Mhz
+  instead of XMP 2133Mhz
+
+- Team Xtreem TXD38G2133HC9NDC01(XMP,1.50v) 2x4GB kit works at
+  1600Mhz instead of XMP 2133Mhz
+
+- Kingston KVR1066D3N7K2/4G(JEDEC,1.50v) 2x4GB kit works at 1066Mhz
+  but the board only detects half its RAM, as those DIMMs have
+  Double Sided(DS) chips and seems only Single Sided(SS) ones are
+  fully detected
+
+- GSkill F3-10666CL9T2-24GBRL(JEDEC,1.50v) 6x4GB kit (4 DIMMs used)
+  works perfectly at full speed (1333Mhz)
+
+## Technology
+
+```eval_rst
++------------------+--------------------------------------------------+
+| Northbridge      | :doc:`../../northbridge/intel/sandybridge/index` |
++------------------+--------------------------------------------------+
+| Southbridge      | bd82x6x                                          |
++------------------+--------------------------------------------------+
+| CPU              | model_206ax                                      |
++------------------+--------------------------------------------------+
+| Super I/O        | Nuvoton NCT6779D                                 |
++------------------+--------------------------------------------------+
+| EC               | None                                             |
++------------------+--------------------------------------------------+
+| Coprocessor      | Intel Management Engine                          |
++------------------+--------------------------------------------------+
+```
+
+## Extra resources
+
+- [Flash chip datasheet][W25Q64FVA1Q]
+
+[ASUS P8Z88-M Pro]: https://www.asus.com/Motherboards/P8Z77M_PRO/
+[W25Q64FVA1Q]: https://www.winbond.com/resource-files/w25q64fv%20revs%2007182017.pdf
+[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/index.md

@@ -7,6 +7,7 @@ This section contains documentation about coreboot on specific mainboards.
 - [F2A85-M](asus/f2a85-m.md)
 - [P8H61-M LX](asus/p8h61-m_lx.md)
 - [P8H61-M Pro](asus/p8h61-m_pro.md)
+- [P8Z77-M Pro](asus/p8z77-m_pro.md)
 
 ## ASRock
 
@@ -86,10 +87,18 @@ The boards in this section are not real mainboards, but emulators.
 
 - [MS-7707](msi/ms7707/ms7707.md)
 
+## PC Engines
+
+- [APU2](pcengines/apu2.md)
+
 ## Roda
 
 - [RK9 Flash Header](roda/rk9/flash_header.md)
 
+## PC Engines
+
+- [APU1](pcengines/apu1.md)
+
 ## SiFive
 
 - [SiFive HiFive Unleashed](sifive/hifive-unleashed.md)

Documentation/mainboard/pcengines/apu1.md

@@ -0,0 +1,97 @@
+# PC Engines APU1
+
+This page describes how to run coreboot on PC Engines APU1 platform.
+
+## Technology
+
+```eval_rst
++------------+--------------------------------------------------------+
+| CPU        | AMD G series T40E APU                                  |
++------------+--------------------------------------------------------+
+| CPU core   | 1 GHz dual core (Bobcat core) with 64 bit support      |
+|            | 32K data + 32K instruction + 512KB L2 cache per core   |
++------------+--------------------------------------------------------+
+| DRAM       | 2 or 4 GB DDR3-1066 DRAM                               |
++------------+--------------------------------------------------------+
+| Boot       | From SD card, USB, mSATA, SATA                         |
++------------+--------------------------------------------------------+
+| Power      | 6 to 12W of 12V power                                  |
++------------+--------------------------------------------------------+
+| Firmware   | coreboot with support for iPXE and USB boot            |
++------------+--------------------------------------------------------+
+```
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+--------------------------+
+| Type                | Value                    |
++=====================+==========================+
+| Socketed flash      | no                       |
++---------------------+--------------------------+
+| Model               | MX25L1606E               |
++---------------------+--------------------------+
+| Size                | 2 MiB                    |
++---------------------+--------------------------+
+| Package             | SOP-8                    |
++---------------------+--------------------------+
+| Write protection    | jumper on WP# pin        |
++---------------------+--------------------------+
+| Dual BIOS feature   | no                       |
++---------------------+--------------------------+
+| Internal flashing   | yes                      |
++---------------------+--------------------------+
+```
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom]. It is important to execute
+command with a `-c <chipname>` argument:
+
+    flashrom -p internal -c "MX25L1606E" -w coreboot.rom
+
+### External programming
+
+**IMPORTANT**: When programming SPI flash, first you need to enter apu1 in S5
+(Soft-off) power state. S5 state can be forced by shorting power button pin on
+J2 header.
+
+The external access to flash chip is available through standard SOP-8 clip or
+SOP-8 header next to the flash chip on the board. Notice that not all boards
+have a header soldered down originally. Hence, there could be an empty slot with
+8 eyelets, so you can solder down a header on your own. The SPI flash chip and
+SPI header are marked in the picture below. Also there is SPI header pin layout
+included. Notice, that signatures at the schematic can be ambiguous:
+- J12 SPIDI = U35 SO = MISO
+- J12 SPIDO = U35 SI = MOSI
+
+There is no restrictions as to the programmer device. It is only recommended to
+flash firmware without supplying power. External programming can be performed,
+for example using OrangePi and Armbian. You can exploit linux_spi driver which
+provide communication with SPI devices. Example command to program SPI flash
+with OrangePi using linux_spi:
+
+    flashrom -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000 -c
+    "MX25L1606E"
+
+
+**apu1 platform with marked in SPI header and SPI flash chip**
+
+![][apu1c1_flash]
+
+**SPI header pin layout**
+
+![][spi_header]
+
+
+### Schematics
+
+PC Engines APU platform schematics are available for free on PC Engines official
+site. Depending on the configuration:
+[apu1c](https://www.pcengines.ch/schema/apu1c.pdf) and
+[apu1d](https://www.pcengines.ch/schema/apu1d.pdf).
+
+
+[apu1c1_flash]: apu1c1.jpg
+[spi_header]: apu1_spi.jpg
+[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/pcengines/apu2.md

@@ -0,0 +1,116 @@
+# PC Engines APU2
+
+This page describes how to run coreboot on PC Engines APU2 platform.
+
+## Technology
+
+```eval_rst
++------------+---------------------------------------------------------------+
+| CPU        | AMD G series GX-412TC                                         |
++------------+---------------------------------------------------------------+
+| CPU core   | 1 GHz quad Puma core with 64 bit support                      |
+|            | 32K data + 32K instruction cache per core, shared 2MB L2 cache|
++------------+---------------------------------------------------------------+
+| DRAM       | 2 or 4 GB DDR3-1333 DRAM                                      |
++------------+---------------------------------------------------------------+
+| Boot       | From SD card, USB, mSATA SSD, SATA                            |
++------------+---------------------------------------------------------------+
+| Power      | 6 to 12W of 12V power                                         |
++------------+---------------------------------------------------------------+
+| Firmware   | coreboot with support for iPXE and USB boot                   |
++------------+---------------------------------------------------------------+
+```
+
+## Required proprietary blobs
+
+To build working coreboot image some blobs are needed.
+
+```eval_rst
++-----------------+---------------------------------+---------------------+
+| Binary file     | Apply                           | Required / Optional |
++=================+=================================+=====================+
+| amdfw.rom*      | AMD Platform Security Processor | Required            |
++-----------------+---------------------------------+---------------------+
+| AGESA.bin       | AGESA Platform Initialization   | Required            |
++-----------------+---------------------------------+---------------------+
+| xhci.bin        | AMD XHCI controller             | Optional            |
++-----------------+---------------------------------+---------------------+
+```
+(\*) - package containing all required blobs for PSP. Directory, in which all
+blobs are listed and available is: *3rdparty/southbridge/amd/avalon/PSP*
+
+## Flashing coreboot
+
+```eval_rst
++---------------------+--------------------------+
+| Type                | Value                    |
++=====================+==========================+
+| Socketed flash      | no                       |
++---------------------+--------------------------+
+| Model               | W25Q64                   |
++---------------------+--------------------------+
+| Size                | 8 MiB                    |
++---------------------+--------------------------+
+| Package             | SOIC-8                   |
++---------------------+--------------------------+
+| Write protection    | jumper on WP# pin*       |
++---------------------+--------------------------+
+| Dual BIOS feature   | no                       |
++---------------------+--------------------------+
+| Internal flashing   | yes                      |
++---------------------+--------------------------+
+```
+(\*) - It is used in normal SPI mode, but can be dangerous when using Quad SPI
+Flash. Then, pull-down resistors should be considered rather than jumper.
+
+### Internal programming
+
+The SPI flash can be accessed using [flashrom].
+
+    flashrom -p internal -w coreboot.rom
+
+### External programming
+
+**IMPORTANT**: When programming SPI flash, first you need to enter apu2 in S5
+(Soft-off) power state. S5 state can be forced by shorting power button pin on
+J2 header.
+
+The external access to flash chip is available through standard SOP-8 clip or
+SOP-8 header next to the flash chip on the board. Notice that not all boards
+have a header soldered down originally. Hence, there could be an empty slot with
+8 eyelets, so you can solder down a header on your own. The SPI flash chip and
+SPI header are marked in the picture below. Also there is SPI header and SPI
+flash pin layout included. Depend on using header or clip there are important
+rules:
+- using header J6 - don't connect 1,7,8 pins
+- using clip U23 - don't connect 3,7,8 pins
+
+Also signatures at the schematic can be ambiguous:
+- J6 SPIDI = U23 SO = MISO
+- J6 SPIDO = U23 SI = MOSI
+
+There is no restrictions as to the programmer device. It is only recommended to
+flash firmware without supplying power. External programming can be performed,
+for example using OrangePi and Armbian. You can exploit linux_spi driver which
+provides communication with SPI devices. Example command to program SPI flash
+with OrangePi using linux_spi:
+
+    flashrom -f -w coreboot.rom -p linux_spi:dev=/dev/spidev1.0,spispeed=16000
+
+**apu2 platform with marked in SPI header and SPI flash chip**
+
+![][apu2_flash]
+
+**SPI header pin layout**
+
+![][spi_header]
+
+## Schematics
+
+PC Engines APU2 [platform schematics](https://pcengines.ch/schema/apu2d.pdf)
+are available for free on PC Engines official site. Both configurations
+(2GB/4GB) have the same PCB and schematic.
+
+[apu2_flash]: apu2.jpg
+[spi_header]: apu2_spi.jpg
+[flashrom]: https://flashrom.org/Flashrom

Documentation/mainboard/up/squared/header_40pin_gpio_uart1.svg

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Documentation/mainboard/up/squared/header_cn16_10pin_uart0.svg

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+    <tspan x="480" y="252.425">RX</tspan>
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+    <tspan x="440" y="272.425">TX</tspan>
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Documentation/mainboard/up/squared/header_cn22_12pin_spi.svg

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+    <tspan x="530" y="34.425">1</tspan>
+  </text>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="490" y="74.425">
+    <tspan x="490" y="74.425">4</tspan>
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+    <tspan x="490" y="34.425">3</tspan>
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+    <tspan x="530" y="74.425">2</tspan>
+  </text>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="450" y="74.425">
+    <tspan x="450" y="74.425">6</tspan>
+  </text>
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+    <tspan x="330" y="34.425">11</tspan>
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+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="330" y="74.425">
+    <tspan x="330" y="74.425">12</tspan>
+  </text>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:normal" x="370" y="74.425">
+    <tspan x="370" y="74.425">10</tspan>
+  </text>
+  <text font-size="12.8" style="fill: #000000;text-anchor:start;font-family:sans-serif;font-style:normal;font-weight:700" x="420" y="-20">
+    <tspan x="420" y="-20">SPI header (CN22)</tspan>
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+    <tspan x="360" y="164.425">GND</tspan>
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+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="520" y="164.425">
+    <tspan x="520" y="164.425">GND</tspan>
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+    <tspan x="400" y="144.425">MISO</tspan>
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+    <tspan x="480" y="136.425">VCC</tspan>
+    <tspan x="480" y="152.425">1.8V</tspan>
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+    <tspan x="320" y="144.425">#HOLD</tspan>
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+    <tspan x="400" y="-55.575">CLK</tspan>
+  </text>
+  <g>
+    <polyline style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="320,-20 320,9 "/>
+    <polygon style="fill: #000000" points="315,9 320,19 325,9 "/>
+    <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="315,9 320,19 325,9 "/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="320" y="-35.575">
+    <tspan x="320" y="-35.575">MOSI</tspan>
+  </text>
+  <g>
+    <line style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" x1="440" y1="140" x2="440" y2="91"/>
+    <polygon style="fill: #000000" points="445,91 440,81 435,91 "/>
+    <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="445,91 440,81 435,91 "/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="440" y="164.238">
+    <tspan x="440" y="164.238">#CS</tspan>
+  </text>
+</svg>

Documentation/mainboard/up/squared/index.md

@@ -7,6 +7,12 @@
 ### Bottom
 ![][overview_bottom]
 
+* **Legend**
+	* [BLUE][header_cn16_link]: UART0 / USB connector
+	* [GREEN][header_gpio_link]: UART1 / GPIO header
+	* [RED][header_cn22_link]: SPI header
+	* YELLOW: Indicates pin 1
+
 ## Mainboard components
 ### Platform
 ```eval_rst
@@ -46,6 +52,79 @@
 +---------------------+------------+
 ```
 
+### Debugging
+#### UART0 (CN16)
+This connector is located on the **bottom** side (see [here][overview_bottom_link]).
+![][header_cn16]
+
+
+#### UART1 (GPIO header)
+The GPIO header is located on the **bottom** side (see [here][overview_bottom_link]).
+![][header_gpio]
+
+## Building and flashing coreboot
+### Using the SPI header
+The SPI header is located on the **bottom** side (see [here][overview_bottom_link]).
+![][header_cn22]
+
+### Preperations
+In order to build coreboot, it's neccessary to extract some files from the vendor firmware. Make sure that you have a fully working dump.
+```bash
+[upsquared]$ ls
+firmware_vendor.rom
+```
+
+```bash
+[upsquared]$ mkdir extracted && cd extracted
+[extracted]$ ifdtool -x ../firmware_vendor.rom 
+File ../firmware_vendor.rom is 16777216 bytes
+Peculiar firmware descriptor, assuming Ibex Peak compatibility.
+  Flash Region 0 (Flash Descriptor): 00000000 - 00000fff 
+  Flash Region 1 (BIOS): 00001000 - 00efefff 
+  Flash Region 2 (Intel ME): 07fff000 - 00000fff (unused)
+  Flash Region 3 (GbE): 07fff000 - 00000fff (unused)
+  Flash Region 4 (Platform Data): 07fff000 - 00000fff (unused)
+  Flash Region 5 (Reserved): 00eff000 - 00ffefff 
+  Flash Region 6 (Reserved): 07fff000 - 00000fff (unused)
+  Flash Region 7 (Reserved): 07fff000 - 00000fff (unused)
+  Flash Region 8 (EC): 07fff000 - 00000fff (unused)
+```
+
+```bash
+flashregion_0_flashdescriptor.bin
+flashregion_1_bios.bin
+flashregion_5_reserved.bin
+```
+
+### Clean up
+```bash
+[coreboot]$ make distclean
+```
+
+### Configuring
+```bash
+[coreboot]$ touch .config
+[coreboot]$ ./util/scripts/config --enable VENDOR_UP
+[coreboot]$ ./util/scripts/config --enable BOARD_UP_SQUARED
+[coreboot]$ ./util/scripts/config --enable NEED_IFWI
+[coreboot]$ ./util/scripts/config --enable HAVE_IFD_BIN
+[coreboot]$ ./util/scripts/config --set-str IFWI_FILE_NAME "<flashregion_1_bios.bin>"
+[coreboot]$ ./util/scripts/config --set-str IFD_BIN_PATH "<flashregion_0_flashdescriptor.bin>"
+[coreboot]$ make olddefconfig
+```
+
+### Building
+```bash
+[coreboot]$ make
+```
+
+Now you should have a working and ready to use coreboot build at `build/coreboot.rom`.
+
+### Flashing
+```bash
+[coreboot]$ flashrom -p <your_programmer> -w build/coreboot.rom
+```
+
 ## Board status
 ### Working
 - bootblock, romstage, ramstage
@@ -78,22 +157,13 @@
 - mini PCIe
 - flashing with flashrom internally using Linux
 
-## Building and flashing coreboot
-### Building
-
-```bash
-make distclean
-touch .config
-./util/scripts/config --enable VENDOR_UP
-./util/scripts/config --enable BOARD_UP_SQUARED
-./util/scripts/config --enable NEED_IFWI
-./util/scripts/config --enable HAVE_IFD_BIN
-./util/scripts/config --set-str IFWI_FILE_NAME "<path_to_your_bios_region>"
-./util/scripts/config --set-str IFD_BIN_PATH "<path_to_your_ifd_region>"
-make olddefconfig
-```
-
-### Flashing
 
+[header_cn16]: header_cn16_10pin_uart0.svg
+[header_cn16_link]: #uart0-cn16
+[header_cn22]: header_cn22_12pin_spi.svg
+[header_cn22_link]: #using-the-spi-header
+[header_gpio]: header_40pin_gpio_uart1.svg
+[header_gpio_link]: #uart1-gpio-header
 [overview_top]: top.jpg
 [overview_bottom]: bottom.jpg
+[overview_bottom_link]: #bottom

Documentation/security/index.md

@@ -6,3 +6,4 @@ This section describes documentation about the security architecture of coreboot
 
 - [Verified Boot](vboot/index.md)
 - [Measured Boot](vboot/measured_boot.md)
+- [Memory clearing](memory_clearing.md)

Documentation/security/memory_clearing.md

@@ -0,0 +1,44 @@
+# Memory clearing
+
+The main memory on computer platforms in high security environments contains
+sensible data. On unexpected reboot the data might persist and could be
+read by a malicious application in the bootflow or userspace.
+
+In order to prevent leaking information from pre-reset, the boot firmware can
+clear the main system memory on boot, wiping all information.
+
+A common API indicates if the main memory has to be cleared. That could be
+on user request or by a Trusted Execution Environment indicating that secrets
+are in memory.
+
+As every platform has different bring-up mechanisms and memory-layouts, every
+The device must indicate support for memory clearing as part of the boot
+process.
+
+## Requirements
+
+1. The platform must clear all platform memory (DRAM) if requested
+2. Code that is placed in DRAM might be skipped (as workaround)
+3. Stack that is placed in DRAM might be skipped (as workaround)
+4. All DRAM is cleared with zeros
+
+## Implementation
+
+A platform that supports memory clearing selects Kconfig
+``PLATFORM_HAS_DRAM_CLEAR`` and calls
+
+```C
+bool security_clear_dram_request(void);
+```
+
+to detect if memory should be cleared.
+
+The memory is cleared in ramstage as part of `DEV_INIT` stage. It's possible to
+clear it earlier on some platforms, but on x86 MTRRs needs to be programmed
+first, which happens in `DEV_INIT`.
+
+Without MTRRs (and caches enabled) clearing memory takes multiple seconds.
+## Exceptions
+
+As some platforms place code and stack in DRAM (FSP1.0), the regions can be
+skipped.

Documentation/soc/intel/apollolake/flash_layout.svg

@@ -0,0 +1,122 @@
+<?xml version="1.0" encoding="UTF-8" standalone="no"?>
+<!DOCTYPE svg PUBLIC "-//W3C//DTD SVG 1.0//EN" "http://www.w3.org/TR/2001/PR-SVG-20010719/DTD/svg10.dtd">
+<svg width="38cm" height="18cm" viewBox="118 98 744 344" xmlns="http://www.w3.org/2000/svg" xmlns:xlink="http://www.w3.org/1999/xlink">
+  <g>
+    <rect style="fill: #ffffff" x="620" y="100" width="180" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="620" y="100" width="180" height="60"/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="710" y="134.425">
+    <tspan x="710" y="134.425">DEVICE_EXTENSION</tspan>
+  </text>
+  <g>
+    <rect style="fill: #ffffff" x="300" y="100" width="320" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="300" y="100" width="320" height="60"/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="460" y="134.425">
+    <tspan x="460" y="134.425">BIOS</tspan>
+  </text>
+  <g>
+    <rect style="fill: #ffffff" x="240" y="100" width="60" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="240" y="100" width="60" height="60"/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="270" y="134.425">
+    <tspan x="270" y="134.425">IFD</tspan>
+  </text>
+  <g>
+    <rect style="fill: #ffffff" x="200" y="240" width="80" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="200" y="240" width="80" height="60"/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="240" y="274.425">
+    <tspan x="240" y="274.425">IFWI</tspan>
+  </text>
+  <g>
+    <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 200 240 C 200,160 460,220 460,169.736"/>
+    <polygon style="fill: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/>
+    <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/>
+  </g>
+  <g>
+    <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 700 240 C 700,160 460,220 460,169.736"/>
+    <polygon style="fill: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/>
+    <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="460,162.236 465,172.236 460,169.736 455,172.236 "/>
+  </g>
+  <g>
+    <rect style="fill: #ffffff" x="800" y="100" width="60" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="800" y="100" width="60" height="60"/>
+  </g>
+  <g>
+    <rect style="fill: #ffffff" x="320" y="380" width="60" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="320" y="380" width="60" height="60"/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="350" y="414.425">
+    <tspan x="350" y="414.425">FMAP</tspan>
+  </text>
+  <g>
+    <rect style="fill: #ffffff" x="440" y="380" width="100" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="440" y="380" width="100" height="60"/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="490" y="414.425">
+    <tspan x="490" y="414.425">CONSOLE</tspan>
+  </text>
+  <g>
+    <rect style="fill: #ffffff" x="540" y="380" width="160" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="540" y="380" width="160" height="60"/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="620" y="414.425">
+    <tspan x="620" y="414.425">COREBOOT(CBFS)</tspan>
+  </text>
+  <g>
+    <rect style="fill: #ffffff" x="700" y="380" width="140" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="700" y="380" width="140" height="60"/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="770" y="414.425">
+    <tspan x="770" y="414.425">BIOS_UNUSABLE</tspan>
+  </text>
+  <g>
+    <rect style="fill: #ffffff" x="380" y="380" width="60" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="380" y="380" width="60" height="60"/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="410" y="414.425">
+    <tspan x="410" y="414.425">MRC</tspan>
+  </text>
+  <g>
+    <rect style="fill: #ffffff" x="280" y="240" width="420" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="280" y="240" width="420" height="60"/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="490" y="274.425">
+    <tspan x="490" y="274.425">OBB</tspan>
+  </text>
+  <g>
+    <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 320 380 C 320,300 490,360 490,311"/>
+    <polygon style="fill: #000000" points="495,311 490,301 485,311 "/>
+    <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495,311 490,301 485,311 "/>
+  </g>
+  <g>
+    <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 840 380 C 840,300 490,360 490,311"/>
+    <polygon style="fill: #000000" points="495,311 490,301 485,311 "/>
+    <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="495,311 490,301 485,311 "/>
+  </g>
+  <g>
+    <rect style="fill: #ffffff" x="120" y="380" width="60" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="120" y="380" width="60" height="60"/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="150" y="414.425">
+    <tspan x="150" y="414.425">TXE</tspan>
+  </text>
+  <g>
+    <rect style="fill: #ffffff" x="180" y="380" width="120" height="60"/>
+    <rect style="fill: none; fill-opacity:0; stroke-width: 3; stroke: #000000" x="180" y="380" width="120" height="60"/>
+  </g>
+  <text font-size="12.8" style="fill: #000000;text-anchor:middle;font-family:sans-serif;font-style:normal;font-weight:700" x="240" y="414.425">
+    <tspan x="240" y="414.425">BOOTBLOCK</tspan>
+  </text>
+  <g>
+    <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 300 380 C 300,320 240,360 240,311"/>
+    <polygon style="fill: #000000" points="245,311 240,301 235,311 "/>
+    <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="245,311 240,301 235,311 "/>
+  </g>
+  <g>
+    <path style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" d="M 120 380 C 120,320 240,360 240,311"/>
+    <polygon style="fill: #000000" points="245,311 240,301 235,311 "/>
+    <polygon style="fill: none; fill-opacity:0; stroke-width: 2; stroke: #000000" points="245,311 240,301 235,311 "/>
+  </g>
+</svg>

Documentation/soc/intel/apollolake/index.md

@@ -0,0 +1,17 @@
+# Apollolake
+## SPI flash layout
+
+![][apl_flash_layout]
+
+With Apollolake Intel invented another flash layout for x86 firmware called IFWI (Intel FirmWare Image).
+
+Usually on x86 platforms the bootblock is stored at the end of the bios region
+and the Intel ME / TXE has its own IFD region. On Apollolake both have been
+moved into the IFWI region, which is a subregion of "BIOS", since it allows to
+store multiple firmware components.
+
+The IFWI region can be manipulated by `ifwitool`.
+
+[apl_flash_layout]: flash_layout.svg
+
+

Documentation/soc/intel/index.md

@@ -9,3 +9,4 @@ This section contains documentation about coreboot on specific Intel SOCs.
 - [Ice Lake/9th Gen Core-i series](icelake/index.md)
 - [MP Initialization](mp_init/mp_init.md)
 - [Firmware Interface Table](fit.md)
+- [Apollolake](apollolake/index.md)

MAINTAINERS

@@ -164,6 +164,11 @@ M:	Patrick Rudolph <siro@das-labor.org>
 S:	Maintained
 F:	src/mainboard/lenovo/
 
+APPLE MAINBOARDS
+M:	Evgeny Zinoviev <me@ch1p.io>
+S:	Maintained
+F:	src/mainboard/apple/
+
 GETAC P470 MAINBOARD
 M:	Patrick Georgi <patrick@georgi.software>
 S:	Maintained
@@ -364,6 +369,11 @@ M:	Angel Pons <th3fanbus@gmail.com>
 S:	Maintained
 F:	src/mainboard/asus/p8h61-m_pro/
 
+ASUS P8Z77-M PRO MAINBOARD
+M:	Vlado Cibic <vladocb@protonmail.com>
+S:	Maintained
+F:	src/mainboard/asus/p8z77-m_pro/
+
 PC ENGINES ALL MAINBOARDS
 M:	Piotr Król <piotr.krol@3mdeb.com>
 M:	Michał Żygowski <michal.zygowski@3mdeb.com>
@@ -624,6 +634,12 @@ S:	Supported
 F:	*/memlayout.h
 F:	*.ld
 
+ELTAN VENDORCODE
+M:	Frans Hendriks <fhendriks@eltan.com>
+M:	Wim Vervoorn <wvervoorn@eltan.com>
+S:	Maintained
+F:	src/vendorcode/eltan
+
 MISSING: TIMERS / DELAYS
 
 MISSING: TIMESTAMPS

Makefile.inc

@@ -193,9 +193,10 @@ ifneq ($(UPDATED_SUBMODULES),1)
 # try to fetch non-optional submodules if the source is under git
 forgetthis:=$(if $(GIT),$(shell git submodule update --init))
 ifeq ($(CONFIG_USE_BLOBS),y)
-# this is necessary because 3rdparty/blobs is update=none, and so is ignored
+# this is necessary because 3rdparty/{blobs,intel-microcode} is update=none, and so is ignored
 # unless explicitly requested and enabled through --checkout
 forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/blobs))
+forgetthis:=$(if $(GIT),$(shell git submodule update --init --checkout 3rdparty/intel-microcode))
 ifeq ($(CONFIG_PLATFORM_USES_FSP1_0)$(CONFIG_PLATFORM_USES_FSP1_1)$(CONFIG_PLATFORM_USES_FSP2_0),y)
 # this is necessary because 3rdparty/fsp is update=none, and so is ignored
 # unless explicitly requested and enabled through --checkout
@@ -512,6 +513,7 @@ CBFSTOOL:=$(objutil)/cbfstool/cbfstool
 FMAPTOOL:=$(objutil)/cbfstool/fmaptool
 RMODTOOL:=$(objutil)/cbfstool/rmodtool
 IFWITOOL:=$(objutil)/cbfstool/ifwitool
+IFITTOOL:=$(objutil)/cbfstool/ifittool
 
 $(obj)/cbfstool: $(CBFSTOOL)
 	cp $< $@
@@ -525,6 +527,9 @@ $(obj)/rmodtool: $(RMODTOOL)
 $(obj)/ifwitool: $(IFWITOOL)
 	cp $< $@
 
+$(obj)/ifittool: $(IFITTOOL)
+	cp $< $@
+
 _WINCHECK=$(shell uname -o 2> /dev/null)
 STACK=
 ifeq ($(_WINCHECK),Msys)
@@ -637,7 +642,7 @@ install-git-commit-clangfmt:
 include util/crossgcc/Makefile.inc
 
 .PHONY: tools
-tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) $(BINCFG)
+tools: $(objutil)/kconfig/conf $(CBFSTOOL) $(objutil)/cbfstool/cbfs-compression-tool $(FMAPTOOL) $(RMODTOOL) $(IFWITOOL) $(objutil)/nvramtool/nvramtool $(ROMCC_BIN) $(objutil)/sconfig/sconfig $(IFDTOOL) $(CBOOTIMAGE) $(AMDFWTOOL) $(FUTILITY) $(BINCFG) $(IFITTOOL)
 
 ###########################################################################
 # Common recipes for all stages
@@ -1007,10 +1012,9 @@ $(obj)/fmap.fmap: $(obj)/fmap.fmd $(FMAPTOOL)
 
 ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
 TS_OPTIONS := -j $(CONFIG_INTEL_TOP_SWAP_BOOTBLOCK_SIZE)
-FIT_OPTIONS := $(TS_OPTIONS)
 endif
 ifneq ($(CONFIG_UPDATE_IMAGE),y)
-$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc
+$(obj)/coreboot.pre: $(objcbfs)/bootblock.bin $$(prebuilt-files) $(CBFSTOOL) $(IFITTOOL) $$(cpu_ucode_cbfs_file) $(obj)/fmap.fmap $(obj)/fmap.desc
 	$(CBFSTOOL) $@.tmp create -M $(obj)/fmap.fmap -r $(shell cat $(obj)/fmap.desc)
 ifeq ($(CONFIG_ARCH_X86),y)
 	$(CBFSTOOL) $@.tmp add \
@@ -1054,9 +1058,6 @@ $(REFCODE_BLOB): $(RMODTOOL)
 endif
 
 FIT_ENTRY=$(call strip_quotes, $(CONFIG_INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG))
-ifneq ($(FIT_ENTRY),)
-FIT_OPTIONS += -q $(FIT_ENTRY)
-endif
 
 ifeq ($(CONFIG_HAVE_RAMSTAGE),y)
 RAMSTAGE=$(objcbfs)/ramstage.elf
@@ -1086,15 +1087,38 @@ endif
 ifeq ($(CONFIG_CPU_INTEL_FIRMWARE_INTERFACE_TABLE),y)
 ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
 	@printf "    UPDATE-FIT\n"
-	$(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
+	$(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
-	$(FIT_OPTIONS)
+	-r COREBOOT
 endif
-
 ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y)
 	@printf "    UPDATE-FIT\n"
-	$(CBFSTOOL) $@.tmp update-fit -n cpu_microcode_blob.bin -x $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
+	$(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
-	$(FIT_OPTIONS)
+	-r COREBOOT
 endif
+	$(IFITTOOL) -f $@.tmp -D -r COREBOOT
+
+# Second FIT in TOP_SWAP bootblock
+ifeq ($(CONFIG_INTEL_ADD_TOP_SWAP_BOOTBLOCK),y)
+# INTEL_TOP_SWAP_FIT_ENTRY_FMAP_REG adds a region as first ucode into the seconds bootblock
+ifneq ($(FIT_ENTRY),)
+	@printf "    UPDATE-FIT2\n"
+	$(IFITTOOL) -f $@.tmp -A -n $(FIT_ENTRY) -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
+	$(TS_OPTIONS) -r COREBOOT
+endif
+ifeq ($(CONFIG_CPU_MICROCODE_CBFS_EXTERNAL_HEADER),y)
+	@printf "    UPDATE-FIT2\n"
+	$(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
+	$(TS_OPTIONS) -r COREBOOT
+endif
+ifeq ($(CONFIG_USE_CPU_MICROCODE_CBFS_BINS),y)
+	@printf "    UPDATE-FIT2\n"
+	$(IFITTOOL) -f $@.tmp -a -n cpu_microcode_blob.bin -t 1 -s $(CONFIG_CPU_INTEL_NUM_FIT_ENTRIES) \
+	$(TS_OPTIONS) -r COREBOOT
+endif
+	$(IFITTOOL) -f $@.tmp -D $(TS_OPTIONS) -r COREBOOT
+
+endif
+
 endif
 	mv $@.tmp $@
 	@printf "    CBFSLAYOUT  $(subst $(obj)/,,$(@))\n\n"

payloads/external/LinuxBoot/x86_64/defconfig

@@ -4,6 +4,7 @@ CONFIG_KERNEL_XZ=y
 CONFIG_SYSVIPC=y
 CONFIG_NO_HZ_IDLE=y
 CONFIG_HIGH_RES_TIMERS=y
+CONFIG_PREEMPT=y
 CONFIG_VIRT_CPU_ACCOUNTING_GEN=y
 CONFIG_CGROUPS=y
 CONFIG_MEMCG=y
@@ -36,36 +37,20 @@ CONFIG_EMBEDDED=y
 # CONFIG_COMPAT_BRK is not set
 CONFIG_SLOB=y
 # CONFIG_SLAB_MERGE_DEFAULT is not set
-CONFIG_GCC_PLUGINS=y
-CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
-CONFIG_GCC_PLUGIN_STRUCTLEAK=y
-CONFIG_GCC_PLUGIN_STRUCTLEAK_BYREF_ALL=y
-CONFIG_GCC_PLUGIN_RANDSTRUCT=y
-# CONFIG_VMAP_STACK is not set
-CONFIG_REFCOUNT_FULL=y
-# CONFIG_BLK_DEV_BSG is not set
-CONFIG_PARTITION_ADVANCED=y
-# CONFIG_IOSCHED_DEADLINE is not set
-# CONFIG_IOSCHED_CFQ is not set
-# CONFIG_MQ_IOSCHED_DEADLINE is not set
-# CONFIG_MQ_IOSCHED_KYBER is not set
 # CONFIG_ZONE_DMA is not set
 # CONFIG_X86_MPPARSE is not set
 # CONFIG_X86_EXTENDED_PLATFORM is not set
-CONFIG_IOSF_MBI=y
 # CONFIG_SCHED_OMIT_FRAME_POINTER is not set
 # CONFIG_DMI is not set
-CONFIG_PREEMPT=y
 # CONFIG_X86_MCE is not set
 # CONFIG_MICROCODE is not set
 CONFIG_X86_MSR=y
 CONFIG_X86_CPUID=y
-# CONFIG_SPARSEMEM_VMEMMAP is not set
-# CONFIG_COMPACTION is not set
 # CONFIG_MTRR is not set
 # CONFIG_X86_INTEL_UMIP is not set
 # CONFIG_X86_INTEL_MEMORY_PROTECTION_KEYS is not set
 CONFIG_KEXEC=y
+CONFIG_KEXEC_FILE=y
 # CONFIG_RELOCATABLE is not set
 # CONFIG_MODIFY_LDT_SYSCALL is not set
 # CONFIG_SUSPEND is not set
@@ -78,12 +63,30 @@ CONFIG_ACPI_VIDEO=y
 # CONFIG_ACPI_TABLE_UPGRADE is not set
 # CONFIG_X86_PM_TIMER is not set
 # CONFIG_CPU_IDLE is not set
-CONFIG_PCIEPORTBUS=y
-CONFIG_PCIEASPM_POWER_SUPERSAVE=y
-CONFIG_PCI_MSI=y
 # CONFIG_ISA_DMA_API is not set
+CONFIG_GOOGLE_FIRMWARE=y
+CONFIG_GOOGLE_COREBOOT_TABLE=y
+CONFIG_GOOGLE_FRAMEBUFFER_COREBOOT=y
+CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y
+CONFIG_GOOGLE_VPD=y
+# CONFIG_VIRTUALIZATION is not set
+# CONFIG_VMAP_STACK is not set
+CONFIG_REFCOUNT_FULL=y
+CONFIG_GCC_PLUGINS=y
+CONFIG_GCC_PLUGIN_LATENT_ENTROPY=y
+CONFIG_GCC_PLUGIN_STRUCTLEAK=y
+CONFIG_GCC_PLUGIN_RANDSTRUCT=y
+# CONFIG_BLK_DEV_BSG is not set
+CONFIG_PARTITION_ADVANCED=y
+# CONFIG_MQ_IOSCHED_DEADLINE is not set
+# CONFIG_MQ_IOSCHED_KYBER is not set
 # CONFIG_BINFMT_SCRIPT is not set
 # CONFIG_COREDUMP is not set
+# CONFIG_SPARSEMEM_VMEMMAP is not set
+# CONFIG_COMPACTION is not set
+CONFIG_PCI=y
+CONFIG_PCIEPORTBUS=y
+CONFIG_PCI_MSI=y
 # CONFIG_UEVENT_HELPER is not set
 CONFIG_DEVTMPFS=y
 CONFIG_DEVTMPFS_MOUNT=y
@@ -92,35 +95,38 @@ CONFIG_DEVTMPFS_MOUNT=y
 # CONFIG_ALLOW_DEV_COREDUMP is not set
 # CONFIG_PNP_DEBUG_MESSAGES is not set
 CONFIG_BLK_DEV_LOOP=y
+CONFIG_BLK_DEV_NVME=y
+CONFIG_NVME_MULTIPATH=y
 CONFIG_BLK_DEV_SD=y
 # CONFIG_SCSI_LOWLEVEL is not set
 CONFIG_ATA=y
-CONFIG_SATA_AHCI=y
 CONFIG_MD=y
 CONFIG_BLK_DEV_DM=y
 CONFIG_DM_CRYPT=y
-CONFIG_SERIAL_8250_CONSOLE=y
-# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
-# CONFIG_SERIAL_8250_EXAR is not set
-# CONFIG_SERIAL_8250_LPSS is not set
-# CONFIG_SERIAL_8250_MID is not set
-# CONFIG_SERIAL_8250_PNP is not set
 CONFIG_SERIAL_8250=y
+# CONFIG_SERIAL_8250_DEPRECATED_OPTIONS is not set
+# CONFIG_SERIAL_8250_PNP is not set
+CONFIG_SERIAL_8250_CONSOLE=y
+CONFIG_SERIAL_8250_NR_UARTS=32
+CONFIG_SERIAL_8250_RUNTIME_UARTS=32
+CONFIG_SERIAL_8250_EXTENDED=y
+CONFIG_SERIAL_8250_MANY_PORTS=y
+CONFIG_SERIAL_8250_DW=y
+CONFIG_SERIAL_DEV_BUS=y
 CONFIG_HW_RANDOM_TIMERIOMEM=y
-# CONFIG_HW_RANDOM_AMD is not set
 # CONFIG_HW_RANDOM_VIA is not set
 CONFIG_TCG_TPM=y
 CONFIG_TCG_TIS=y
-# CONFIG_DEVPORT is not set
 CONFIG_I2C=y
 CONFIG_POWER_SUPPLY=y
 # CONFIG_HWMON is not set
-# CONFIG_VGA_ARB is not set
+CONFIG_MFD_INTEL_LPSS_PCI=y
 CONFIG_FB=y
 CONFIG_FIRMWARE_EDID=y
 CONFIG_FB_FOREIGN_ENDIAN=y
 CONFIG_FB_MODE_HELPERS=y
 CONFIG_FB_TILEBLITTING=y
+CONFIG_FB_SIMPLE=y
 CONFIG_BACKLIGHT_LCD_SUPPORT=y
 CONFIG_VGACON_SOFT_SCROLLBACK=y
 CONFIG_VGACON_SOFT_SCROLLBACK_PERSISTENT_ENABLE_BY_DEFAULT=y
@@ -128,14 +134,14 @@ CONFIG_FRAMEBUFFER_CONSOLE=y
 CONFIG_FRAMEBUFFER_CONSOLE_DETECT_PRIMARY=y
 CONFIG_FRAMEBUFFER_CONSOLE_ROTATION=y
 # CONFIG_USB_SUPPORT is not set
+CONFIG_MMC=y
+CONFIG_MMC_SDHCI=y
+CONFIG_MMC_SDHCI_PCI=y
+CONFIG_MMC_SDHCI_ACPI=y
+CONFIG_MMC_SDHCI_PLTFM=y
 CONFIG_SYNC_FILE=y
 # CONFIG_VIRTIO_MENU is not set
 # CONFIG_X86_PLATFORM_DEVICES is not set
-# CONFIG_FIRMWARE_MEMMAP is not set
-CONFIG_GOOGLE_FIRMWARE=y
-CONFIG_GOOGLE_COREBOOT_TABLE_ACPI=y
-CONFIG_GOOGLE_MEMCONSOLE_COREBOOT=y
-CONFIG_GOOGLE_VPD=y
 CONFIG_EXT4_FS=y
 # CONFIG_FILE_LOCKING is not set
 # CONFIG_DNOTIFY is not set
@@ -149,7 +155,13 @@ CONFIG_VFAT_FS=y
 CONFIG_FAT_DEFAULT_UTF8=y
 CONFIG_TMPFS=y
 # CONFIG_MISC_FILESYSTEMS is not set
-# CONFIG_ENABLE_WARN_DEPRECATED is not set
+CONFIG_SECURITY_DMESG_RESTRICT=y
+CONFIG_FORTIFY_SOURCE=y
+# CONFIG_CRYPTO_ECHAINIV is not set
+CONFIG_CRYPTO_SHA256_SSSE3=y
+CONFIG_CRYPTO_ANSI_CPRNG=y
+CONFIG_CRYPTO_JITTERENTROPY=y
+# CONFIG_CRYPTO_HW is not set
 # CONFIG_ENABLE_MUST_CHECK is not set
 CONFIG_FRAME_WARN=1024
 # CONFIG_UNUSED_SYMBOLS is not set
@@ -163,11 +175,3 @@ CONFIG_FRAME_WARN=1024
 CONFIG_OPTIMIZE_INLINING=y
 # CONFIG_X86_DEBUG_FPU is not set
 CONFIG_UNWINDER_GUESS=y
-CONFIG_SECURITY_DMESG_RESTRICT=y
-CONFIG_FORTIFY_SOURCE=y
-# CONFIG_CRYPTO_ECHAINIV is not set
-CONFIG_CRYPTO_SHA256_SSSE3=y
-CONFIG_CRYPTO_ANSI_CPRNG=y
-CONFIG_CRYPTO_JITTERENTROPY=y
-# CONFIG_CRYPTO_HW is not set
-# CONFIG_VIRTUALIZATION is not set

payloads/libpayload/README

@@ -22,12 +22,18 @@ Installation
 
  $ make
 
- $ sudo make install (optional, will install into /opt per default)
+ $ make install (optional, will install into ./install per default)
 
-As libpayload is for 32bit x86 systems only, you might have to install the
+On x86 systems, libpayload will always be 32-bit even if your host OS runs
-32bit libgcc version, otherwise your payloads will fail to compile.
+in 64-bit, so you might have to install the 32-bit libgcc version.
 On Debian systems you'd do 'apt-get install gcc-multilib' for example.
 
+Run 'make distclean' before switching boards. This command will remove
+your current .config file, so you need 'make menuconfig' again or
+'make defconfig' in order to set up configuration. Default configuration
+is based on 'configs/defconfig'. See the configs/ directory for examples
+of configuration.
+
 
 Usage
 -----

payloads/libpayload/configs/config.emulation-qemu-arm

@@ -0,0 +1,6 @@
+CONFIG_LP_ARCH_ARM=y
+CONFIG_LP_STACK_SIZE=64000
+CONFIG_LP_BASE_ADDRESS=0x62030000
+CONFIG_LP_TINYCURSES=y
+CONFIG_LP_8250_SERIAL_CONSOLE=y
+CONFIG_LP_TIMER_GENERIC_HZ=1000000

payloads/libpayload/drivers/i8042/keyboard.c

@@ -319,25 +319,33 @@ void keyboard_init(void)
 
 	/* Set scancode set 1 */
 	ret = keyboard_cmd(I8042_KBCMD_SET_SCANCODE);
-	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
+	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) {
+		printf("ERROR: Keyboard set scancode failed!\n");
 		return;
+	}
 
 	ret = keyboard_cmd(I8042_SCANCODE_SET_1);
-	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
+	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) {
+		printf("ERROR: Keyboard scancode set#1 failed!\n");
 		return;
+	}
 
 	/*
 	 * Set default parameters.
 	 * Fix for broken QEMU ps/2 make scancodes.
 	 */
 	ret = keyboard_cmd(0xf6);
-	if (!ret)
+	if (!ret) {
+		printf("ERROR: Keyboard set default params failed!\n");
 		return;
+	}
 
 	/* Enable scanning */
 	ret = keyboard_cmd(I8042_KBCMD_EN);
-	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE))
+	if (!ret && !CONFIG(LP_PC_KEYBOARD_IGNORE_INIT_FAILURE)) {
+		printf("ERROR: Keyboard enable scanning failed!\n");
 		return;
+	}
 
 	console_add_input_driver(&cons);
 }

payloads/libpayload/drivers/serial/qcs405.c

@@ -547,8 +547,10 @@ void serial_console_init(void)
 
 	uart_board_param.uart_dm_base = (void *)(uintptr_t)sc_ptr->baseaddr;
 
-	/* TODO: We should rely on coreboot init. */
+	/* We should re-initialise uart rx as it gets reset in coreboot. */
-	msm_boot_uart_dm_init(uart_board_param.uart_dm_base);
+	write32(MSM_BOOT_UART_DM_IMR(uart_board_param.uart_dm_base),
+		MSM_BOOT_UART_DM_IMR_ENABLED);
+	msm_boot_uart_dm_init_rx_transfer(uart_board_param.uart_dm_base);
 
 	console_add_output_driver(&consout);
 	console_add_input_driver(&consin);

payloads/libpayload/drivers/video/graphics.c

@@ -183,6 +183,10 @@ int draw_box(const struct rect *box, const struct rgb_color *rgb)
 	struct vector top_left;
 	struct vector size;
 	struct vector p, t;
+
+	if (cbgfx_init())
+		return CBGFX_ERROR_INIT;
+
 	const uint32_t color = calculate_color(rgb, 0);
 	const struct scale top_left_s = {
 		.x = { .n = box->offset.x, .d = CANVAS_SCALE, },
@@ -193,9 +197,6 @@ int draw_box(const struct rect *box, const struct rgb_color *rgb)
 		.y = { .n = box->size.y, .d = CANVAS_SCALE, }
 	};
 
-	if (cbgfx_init())
-		return CBGFX_ERROR_INIT;
-
 	transform_vector(&top_left, &canvas.size, &top_left_s, &canvas.offset);
 	transform_vector(&size, &canvas.size, &size_s, &vzero);
 	add_vectors(&t, &top_left, &size);

payloads/libpayload/include/coreboot_tables.h

@@ -33,6 +33,58 @@
 #include <arch/types.h>
 #include <ipchksum.h>
 
+enum {
+	CB_TAG_UNUSED			= 0x0000,
+	CB_TAG_MEMORY			= 0x0001,
+	CB_TAG_HWRPB			= 0x0002,
+	CB_TAG_MAINBOARD		= 0x0003,
+	CB_TAG_VERSION			= 0x0004,
+	CB_TAG_EXTRA_VERSION		= 0x0005,
+	CB_TAG_BUILD			= 0x0006,
+	CB_TAG_COMPILE_TIME		= 0x0007,
+	CB_TAG_COMPILE_BY		= 0x0008,
+	CB_TAG_COMPILE_HOST		= 0x0009,
+	CB_TAG_COMPILE_DOMAIN		= 0x000a,
+	CB_TAG_COMPILER			= 0x000b,
+	CB_TAG_LINKER			= 0x000c,
+	CB_TAG_ASSEMBLER		= 0x000d,
+	CB_TAG_SERIAL			= 0x000f,
+	CB_TAG_CONSOLE			= 0x0010,
+	CB_TAG_FORWARD			= 0x0011,
+	CB_TAG_FRAMEBUFFER		= 0x0012,
+	CB_TAG_GPIO			= 0x0013,
+	CB_TAG_TIMESTAMPS		= 0x0016,
+	CB_TAG_CBMEM_CONSOLE		= 0x0017,
+	CB_TAG_MRC_CACHE		= 0x0018,
+	CB_TAG_VBNV			= 0x0019,
+	CB_TAG_VBOOT_HANDOFF		= 0x0020,
+	CB_TAG_X86_ROM_MTRR		= 0x0021,
+	CB_TAG_DMA			= 0x0022,
+	CB_TAG_RAM_OOPS			= 0x0023,
+	CB_TAG_ACPI_GNVS		= 0x0024,
+	CB_TAG_BOARD_ID			= 0x0025,
+	CB_TAG_VERSION_TIMESTAMP	= 0x0026,
+	CB_TAG_WIFI_CALIBRATION		= 0x0027,
+	CB_TAG_RAM_CODE			= 0x0028,
+	CB_TAG_SPI_FLASH		= 0x0029,
+	CB_TAG_SERIALNO			= 0x002a,
+	CB_TAG_MTC			= 0x002b,
+	CB_TAG_VPD			= 0x002c,
+	CB_TAG_SKU_ID			= 0x002d,
+	CB_TAG_BOOT_MEDIA_PARAMS	= 0x0030,
+	CB_TAG_CBMEM_ENTRY		= 0x0031,
+	CB_TAG_TSC_INFO			= 0x0032,
+	CB_TAG_MAC_ADDRS		= 0x0033,
+	CB_TAG_VBOOT_WORKBUF		= 0x0034,
+	CB_TAG_MMC_INFO			= 0x0035,
+	CB_TAG_TCPA_LOG			= 0x0036,
+	CB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
+	CB_TAG_OPTION			= 0x00c9,
+	CB_TAG_OPTION_ENUM		= 0x00ca,
+	CB_TAG_OPTION_DEFAULTS		= 0x00cb,
+	CB_TAG_OPTION_CHECKSUM		= 0x00cc,
+};
+
 struct cbuint64 {
 	u32 lo;
 	u32 hi;
@@ -52,9 +104,6 @@ struct cb_record {
 	u32 size;
 };
 
-#define CB_TAG_UNUSED     0x0000
-#define CB_TAG_MEMORY     0x0001
-
 struct cb_memory_range {
 	struct cbuint64 start;
 	struct cbuint64 size;
@@ -75,16 +124,12 @@ struct cb_memory {
 	struct cb_memory_range map[0];
 };
 
-#define CB_TAG_HWRPB      0x0002
-
 struct cb_hwrpb {
 	u32 tag;
 	u32 size;
 	u64 hwrpb;
 };
 
-#define CB_TAG_MAINBOARD  0x0003
-
 struct cb_mainboard {
 	u32 tag;
 	u32 size;
@@ -93,25 +138,12 @@ struct cb_mainboard {
 	u8 strings[0];
 };
 
-#define CB_TAG_VERSION        0x0004
-#define CB_TAG_EXTRA_VERSION  0x0005
-#define CB_TAG_BUILD          0x0006
-#define CB_TAG_COMPILE_TIME   0x0007
-#define CB_TAG_COMPILE_BY     0x0008
-#define CB_TAG_COMPILE_HOST   0x0009
-#define CB_TAG_COMPILE_DOMAIN 0x000a
-#define CB_TAG_COMPILER       0x000b
-#define CB_TAG_LINKER         0x000c
-#define CB_TAG_ASSEMBLER      0x000d
-
 struct cb_string {
 	u32 tag;
 	u32 size;
 	u8 string[0];
 };
 
-#define CB_TAG_SERIAL         0x000f
-
 struct cb_serial {
 	u32 tag;
 	u32 size;
@@ -138,8 +170,6 @@ struct cb_serial {
 	u32 uart_pci_addr;
 };
 
-#define CB_TAG_CONSOLE       0x00010
-
 struct cb_console {
 	u32 tag;
 	u32 size;
@@ -153,15 +183,12 @@ struct cb_console {
 #define CB_TAG_CONSOLE_SROM       4 // OBSOLETE
 #define CB_TAG_CONSOLE_EHCI       5
 
-#define CB_TAG_FORWARD       0x00011
-
 struct cb_forward {
 	u32 tag;
 	u32 size;
 	u64 forward;
 };
 
-#define CB_TAG_FRAMEBUFFER      0x0012
 struct cb_framebuffer {
 	u32 tag;
 	u32 size;
@@ -181,7 +208,6 @@ struct cb_framebuffer {
 	u8 reserved_mask_size;
 };
 
-#define CB_TAG_GPIO 0x0013
 #define CB_GPIO_ACTIVE_LOW 0
 #define CB_GPIO_ACTIVE_HIGH 1
 #define CB_GPIO_MAX_NAME_LENGTH 16
@@ -200,13 +226,6 @@ struct cb_gpios {
 	struct cb_gpio gpios[0];
 };
 
-#define CB_TAG_VBNV		0x0019
-#define CB_TAG_VBOOT_HANDOFF	0x0020
-#define CB_TAG_VBOOT_WORKBUF	0x0034
-#define CB_TAG_DMA		0x0022
-#define CB_TAG_RAM_OOPS		0x0023
-#define CB_TAG_MTC		0x002b
-#define CB_TAG_VPD		0x002c
 struct lb_range {
 	uint32_t tag;
 	uint32_t size;
@@ -214,18 +233,12 @@ struct lb_range {
 	uint32_t range_size;
 };
 
-#define CB_TAG_TIMESTAMPS	0x0016
-#define CB_TAG_CBMEM_CONSOLE	0x0017
-#define CB_TAG_MRC_CACHE	0x0018
-#define CB_TAG_ACPI_GNVS	0x0024
-#define CB_TAG_WIFI_CALIBRATION	0x0027
 struct cb_cbmem_tab {
 	uint32_t tag;
 	uint32_t size;
 	uint64_t cbmem_tab;
 };
 
-#define CB_TAG_X86_ROM_MTRR	0x0021
 struct cb_x86_rom_mtrr {
 	uint32_t tag;
 	uint32_t size;
@@ -236,17 +249,12 @@ struct cb_x86_rom_mtrr {
 	uint32_t index;
 };
 
-
-#define CB_TAG_BOARD_ID		0x0025
-#define CB_TAG_RAM_CODE		0x0028
-#define CB_TAG_SKU_ID		0x002d
 struct cb_strapping_id {
 	uint32_t tag;
 	uint32_t size;
 	uint32_t id_code;
 };
 
-#define CB_TAG_SPI_FLASH	0x0029
 struct cb_spi_flash {
 	uint32_t tag;
 	uint32_t size;
@@ -255,7 +263,6 @@ struct cb_spi_flash {
 	uint32_t erase_cmd;
 };
 
-#define CB_TAG_BOOT_MEDIA_PARAMS 0x0030
 struct cb_boot_media_params {
 	uint32_t tag;
 	uint32_t size;
@@ -266,7 +273,6 @@ struct cb_boot_media_params {
 	uint64_t boot_media_size;
 };
 
-#define CB_TAG_TSC_INFO 0x0032
 struct cb_tsc_info {
 	uint32_t tag;
 	uint32_t size;
@@ -274,7 +280,6 @@ struct cb_tsc_info {
 	uint32_t freq_khz;
 };
 
-#define CB_TAG_MAC_ADDRS       0x0033
 struct mac_address {
 	uint8_t mac_addr[6];
 	uint8_t pad[2];         /* Pad it to 8 bytes to keep it simple. */
@@ -287,7 +292,6 @@ struct cb_macs {
 	struct mac_address mac_addrs[0];
 };
 
-#define CB_TAG_MMC_INFO		0x0035
 struct cb_mmc_info {
 	uint32_t tag;
 	uint32_t size;
@@ -302,17 +306,14 @@ struct cb_mmc_info {
 	int32_t early_cmd1_status;
 };
 
-#define CB_TAG_SERIALNO		0x002a
 #define CB_MAX_SERIALNO_LENGTH	32
 
-#define CB_TAG_CMOS_OPTION_TABLE 0x00c8
 struct cb_cmos_option_table {
 	u32 tag;
 	u32 size;
 	u32 header_length;
 };
 
-#define CB_TAG_OPTION         0x00c9
 #define CB_CMOS_MAX_NAME_LENGTH    32
 struct cb_cmos_entries {
 	u32 tag;
@@ -324,8 +325,6 @@ struct cb_cmos_entries {
 	u8 name[CB_CMOS_MAX_NAME_LENGTH];
 };
 
-
-#define CB_TAG_OPTION_ENUM    0x00ca
 #define CB_CMOS_MAX_TEXT_LENGTH 32
 struct cb_cmos_enums {
 	u32 tag;
@@ -335,7 +334,6 @@ struct cb_cmos_enums {
 	u8 text[CB_CMOS_MAX_TEXT_LENGTH];
 };
 
-#define CB_TAG_OPTION_DEFAULTS 0x00cb
 #define CB_CMOS_IMAGE_BUFFER_SIZE 128
 struct cb_cmos_defaults {
 	u32 tag;
@@ -345,7 +343,6 @@ struct cb_cmos_defaults {
 	u8 default_set[CB_CMOS_IMAGE_BUFFER_SIZE];
 };
 
-#define CB_TAG_OPTION_CHECKSUM 0x00cc
 #define CB_CHECKSUM_NONE	0
 #define CB_CHECKSUM_PCBIOS	1
 struct	cb_cmos_checksum {

payloads/libpayload/sample/Makefile

@@ -28,19 +28,20 @@
 ##
 
 # Sample libpayload Makefile.
-include ../.xcompile
 include ../.config
+include ../.xcompile
 
-ARCH-$(CONFIG_LP_ARCH_ARMV)    := arm
+ARCH-$(CONFIG_LP_ARCH_ARM)   := arm
-ARCH-$(CONFIG_LP_ARCH_POWERPC) := powerpc
+ARCH-$(CONFIG_LP_ARCH_X86)   := x86_32
-ARCH-$(CONFIG_LP_ARCH_X86)     := i386
+ARCH-$(CONFIG_LP_ARCH_ARM64) := arm64
+ARCH-$(CONFIG_LP_ARCH_MIPS)  := mips
 
 CC := $(CC_$(ARCH-y))
 AS := $(AS_$(ARCH-y))
 LIBPAYLOAD_DIR := ../install/libpayload
 XCC := CC="$(CC)" $(LIBPAYLOAD_DIR)/bin/lpgcc
 XAS := AS="$(AS)" $(LIBPAYLOAD_DIR)/bin/lpas
-CFLAGS := -Wall -Werror -Os
+CFLAGS := -fno-builtin -Wall -Werror -Os
 TARGET := hello
 OBJS := $(TARGET).o
 

src/Kconfig

@@ -32,8 +32,13 @@ config LOCALVERSION
 	  the coreboot version number, so that you can easily distinguish
 	  boot logs of different boards from each other.
 
+config CONFIGURABLE_CBFS_PREFIX
+	bool
+	help
+	  Select this to prompt to use to configure the prefix for cbfs files.
+
 config CBFS_PREFIX
-	string "CBFS prefix to use"
+	string "CBFS prefix to use" if CONFIGURABLE_CBFS_PREFIX
 	default "fallback"
 	help
 	  Select the prefix to all files put into the image. It's "fallback"
@@ -285,7 +290,7 @@ config HAVE_RAMPAYLOAD
 
 config RAMPAYLOAD
 	bool "Enable coreboot flow without executing ramstage"
-	default n
+	default y if ARCH_X86
 	depends on HAVE_RAMPAYLOAD
 	help
 	  If this option is enabled, coreboot flow will skip ramstage

src/arch/arm/armv7/mmu.c

@@ -29,6 +29,7 @@
  */
 
 #include <assert.h>
+#include <commonlib/helpers.h>
 #include <stdlib.h>
 #include <stdint.h>
 #include <symbols.h>

src/arch/arm/cpu.c

@@ -29,6 +29,7 @@
  */
 #include <stdlib.h>
 #include <arch/cpu.h>
+#include <commonlib/helpers.h>
 
 /* Return the CPU struct which is at the high memory address of the stack.
  */
@@ -39,7 +40,7 @@ struct cpu_info *cpu_info(void)
 	"feature, make sure you add the proper assertions " \
 	"(and maybe consider revising the whole thing to work closer to what " \
 	"arm64 is doing now)."
-	uintptr_t addr = ALIGN((uintptr_t)__builtin_frame_address(0),
+	uintptr_t addr = ALIGN_UP((uintptr_t)__builtin_frame_address(0),
 		CONFIG_STACK_SIZE);
 	addr -= sizeof(struct cpu_info);
 	return (void *)addr;

src/arch/arm64/armv8/bootblock.S

@@ -19,7 +19,7 @@
 /* NOTE: When making changes to general ARM64 initialization, keep in mind that
  * there are other CPU entry points, using BOOTBLOCK_CUSTOM or entering the CPU
  * in a later stage (like Tegra). Changes should generally be put into
- * arm64_cpu_init so they can be shared between those instances. */
+ * arm64_init_cpu so they can be shared between those instances. */
 
 ENTRY(_start)
 	/* Initialize PSTATE, SCTLR and caches to clean state, set up stack. */

src/arch/arm64/fit_payload.c

@@ -20,6 +20,7 @@
 #include <string.h>
 #include <commonlib/compression.h>
 #include <commonlib/cbfs_serialized.h>
+#include <commonlib/helpers.h>
 #include <lib.h>
 #include <fit.h>
 #include <endian.h>
@@ -184,20 +185,14 @@ bool fit_payload_arch(struct prog *payload, struct fit_config_node *config,
 	bool place_anywhere;
 	void *arg = NULL;
 
-	if (!config->fdt || !fdt) {
+	if (!decompress_kernel_header(config->kernel)) {
-		printk(BIOS_CRIT, "CRIT: Providing a valid FDT is mandatory to "
-		       "boot an ARM64 kernel!\n");
-		return false;
-	}
-
-	if (!decompress_kernel_header(config->kernel_node)) {
 		printk(BIOS_CRIT, "CRIT: Payload doesn't look like an ARM64"
 		       " kernel Image.\n");
 		return false;
 	}
 
 	/* Update kernel size from image header, if possible */
-	kernel->size = get_kernel_size(config->kernel_node);
+	kernel->size = get_kernel_size(config->kernel);
 	printk(BIOS_DEBUG, "FIT: Using kernel size of 0x%zx bytes\n",
 	       kernel->size);
 

src/arch/riscv/boot.c

@@ -19,6 +19,7 @@
 #include <arch/encoding.h>
 #include <arch/smp/smp.h>
 #include <mcall.h>
+#include <commonlib/cbfs_serialized.h>
 
 /*
  * A pointer to the Flattened Device Tree passed to coreboot by the boot ROM.
@@ -33,6 +34,12 @@ static void do_arch_prog_run(struct prog *prog)
 	int hart_id;
 	void *fdt = prog_entry_arg(prog);
 
+	/*
+	 * Workaround selfboot putting the coreboot table into prog_entry_arg
+	 */
+	if (prog_cbfs_type(prog) == CBFS_TYPE_SELF)
+		fdt = HLS()->fdt;
+
 	/*
 	 * If prog_entry_arg is not set (e.g. by fit_payload), use fdt from HLS
 	 * instead.

src/arch/riscv/include/mcall.h

@@ -27,7 +27,7 @@
 #endif
 
 /* We save 37 registers, currently. */
-#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * 8)
+#define MENTRY_FRAME_SIZE (HLS_SIZE + 37 * __SIZEOF_POINTER__)
 
 #ifndef __ASSEMBLER__
 

src/arch/riscv/mcall.c

@@ -25,24 +25,15 @@
  * MAINTENANCE, SUPPORT, UPDATES, ENHANCEMENTS, OR MODIFICATIONS.
  */
 
-#include <arch/barrier.h>
-#include <arch/errno.h>
-#include <console/console.h>
 #include <mcall.h>
 #include <string.h>
 #include <vm.h>
 
-int mcalldebug; // set this interactively for copious debug.
-
 void hls_init(uint32_t hart_id, void *fdt)
 {
-	printk(BIOS_SPEW, "hart %d: HLS is %p\n", hart_id, HLS());
 	memset(HLS(), 0, sizeof(*HLS()));
 	HLS()->fdt = fdt;
 	HLS()->hart_id = hart_id;
 
 	mtime_init();
-
-	printk(BIOS_SPEW, "Time is %p and timecmp is %p\n",
-	       HLS()->time, HLS()->timecmp);
 }

src/arch/riscv/payload.c

@@ -19,23 +19,38 @@
 #include <arch/boot.h>
 #include <arch/encoding.h>
 #include <console/console.h>
+#include <vm.h>
 
 void run_payload(struct prog *prog, void *fdt, int payload_mode)
 {
 	void (*doit)(int hart_id, void *fdt) = prog_entry(prog);
 	int hart_id = read_csr(mhartid);
 	uintptr_t status = read_csr(mstatus);
-	status &= ~MSTATUS_MPIE;
+	status = INSERT_FIELD(status, MSTATUS_MPIE, 0);
-	status &= ~MSTATUS_MPP;
 	switch (payload_mode) {
 	case RISCV_PAYLOAD_MODE_U:
+		status = INSERT_FIELD(status, MSTATUS_MPP, PRV_U);
+		/* Trap vector base address point to the payload */
+		write_csr(utvec, doit);
+		/* disable U-Mode interrupt */
+		write_csr(uie, 0);
 		break;
 	case RISCV_PAYLOAD_MODE_S:
-		status |= MSTATUS_SPP;
+		status = INSERT_FIELD(status, MSTATUS_MPP, PRV_S);
+		/* Trap vector base address point to the payload */
+		write_csr(stvec, doit);
+		/* disable S-Mode interrupt */
+		write_csr(sie, 0);
+		/* disable MMU */
+		write_csr(satp, 0);
 		break;
 	case RISCV_PAYLOAD_MODE_M:
-		doit(hart_id, fdt);
+		status = INSERT_FIELD(status, MSTATUS_MPP, PRV_M);
-		return;
+		/* Trap vector base address point to the payload */
+		write_csr(mtvec, doit);
+		/* disable M-Mode interrupt */
+		write_csr(mie, 0);
+		break;
 	default:
 		die("wrong privilege level for payload");
 		break;

src/arch/x86/Kconfig

@@ -239,14 +239,17 @@ config ROMSTAGE_DEBUG_SPINLOOP
 	  Add a spin (JMP .) in assembly_entry.S during early romstage to wait
 	  for a JTAG debugger to break into the execution sequence.
 
+# Selecting a cbfs prefix from the bootblock is only implemented with romcc
 choice
 	prompt "Bootblock behaviour"
 	default BOOTBLOCK_SIMPLE
+	depends on !C_ENVIRONMENT_BOOTBLOCK
 
 config BOOTBLOCK_SIMPLE
 	bool "Always load fallback"
 
 config BOOTBLOCK_NORMAL
+	select CONFIGURABLE_CBFS_PREFIX
 	bool "Switch to normal if CMOS says so"
 
 endchoice

src/arch/x86/acpi.c

@@ -44,6 +44,7 @@
 #include <arch/acpigen.h>
 #include <device/pci.h>
 #include <cbmem.h>
+#include <commonlib/helpers.h>
 #include <cpu/x86/lapic_def.h>
 #include <cpu/cpu.h>
 #include <cbfs.h>
@@ -772,6 +773,57 @@ void acpi_create_vfct(struct device *device,
 	header->checksum = acpi_checksum((void *)vfct, header->length);
 }
 
+void acpi_create_ipmi(struct device *device,
+		      struct acpi_spmi *spmi,
+		      const u16 ipmi_revision,
+		      const acpi_addr_t *addr,
+		      const enum acpi_ipmi_interface_type type,
+		      const s8 gpe_interrupt,
+		      const u32 apic_interrupt,
+		      const u32 uid)
+{
+	acpi_header_t *header = &(spmi->header);
+	memset((void *)spmi, 0, sizeof(struct acpi_spmi));
+
+	/* Fill out header fields. */
+	memcpy(header->signature, "SPMI", 4);
+	memcpy(header->oem_id, OEM_ID, 6);
+	memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8);
+	memcpy(header->asl_compiler_id, ASLC, 4);
+
+	header->asl_compiler_revision = asl_revision;
+	header->length = sizeof(struct acpi_spmi);
+	header->revision = get_acpi_table_revision(SPMI);
+
+	spmi->reserved = 1;
+
+	if (device->path.type == DEVICE_PATH_PCI) {
+		spmi->pci_device_flag = ACPI_IPMI_PCI_DEVICE_FLAG;
+		spmi->pci_bus = device->bus->secondary;
+		spmi->pci_device = device->path.pci.devfn >> 3;
+		spmi->pci_function = device->path.pci.devfn & 0x7;
+	} else if (type != IPMI_INTERFACE_SSIF) {
+		memcpy(spmi->uid, &uid, sizeof(spmi->uid));
+	}
+
+	spmi->base_address = *addr;
+	spmi->specification_revision = ipmi_revision;
+
+	spmi->interface_type = type;
+
+	if (gpe_interrupt >= 0 && gpe_interrupt < 32) {
+		spmi->gpe = gpe_interrupt;
+		spmi->interrupt_type |= ACPI_IPMI_INT_TYPE_SCI;
+	}
+	if (apic_interrupt > 0) {
+		spmi->global_system_interrupt = apic_interrupt;
+		spmi->interrupt_type |= ACPI_IPMI_INT_TYPE_APIC;
+	}
+
+	/* Calculate checksum. */
+	header->checksum = acpi_checksum((void *)spmi, header->length);
+}
+
 void acpi_create_ivrs(acpi_ivrs_t *ivrs,
 		      unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct,
 		      unsigned long current))
@@ -813,7 +865,7 @@ unsigned long acpi_write_hpet(struct device *device, unsigned long current,
 
 	hpet = (acpi_hpet_t *) current;
 	current += sizeof(acpi_hpet_t);
-	current = ALIGN(current, 16);
+	current = ALIGN_UP(current, 16);
 	acpi_create_hpet(hpet);
 	acpi_add_table(rsdp, hpet);
 
@@ -1271,7 +1323,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	acpi_write_xsdt(xsdt, oem_id, oem_table_id);
 
 	printk(BIOS_DEBUG, "ACPI:    * FACS\n");
-	current = (ALIGN(current, 64));
+	current = ALIGN_UP(current, 64);
 	facs = (acpi_facs_t *) current;
 	current += sizeof(acpi_facs_t);
 	current = acpi_align_current(current);
@@ -1490,6 +1542,8 @@ int get_acpi_table_revision(enum acpi_tables table)
 		return 1;
 	case SLIT: /* ACPI 2.0 upto 6.3: 1 */
 		return 1;
+	case SPMI: /* IMPI 2.0 */
+		return 5;
 	case HPET: /* Currently 1. Table added in ACPI 2.0. */
 		return 1;
 	case VFCT: /* ACPI 2.0/3.0/4.0: 1 */

src/arch/x86/acpi_s3.c

@@ -18,6 +18,7 @@
 #include <arch/acpi.h>
 #include <arch/cpu.h>
 #include <cbmem.h>
+#include <commonlib/helpers.h>
 #include <fallback.h>
 #include <timestamp.h>
 #include <program_loading.h>

src/arch/x86/car.ld

@@ -91,13 +91,6 @@
 	_car_global_end = .;
 	_car_relocatable_data_end = .;
 
-#if CONFIG(NORTHBRIDGE_INTEL_SANDYBRIDGE) && !CONFIG(USE_NATIVE_RAMINIT)
-	. = ABSOLUTE(0xff7e1000);
-	_mrc_pool = .;
-	. += 0x5000;
-	_emrc_pool = .;
-#endif
-
 #if !CONFIG(C_ENVIRONMENT_BOOTBLOCK)
 	_car_stack_start = .;
 	_car_stack_end = _car_region_end;

src/arch/x86/cpu.c

@@ -113,6 +113,7 @@ static struct {
 	{ X86_VENDOR_TRANSMETA, "TransmetaCPU", },
 	{ X86_VENDOR_NSC,       "Geode by NSC", },
 	{ X86_VENDOR_SIS,       "SiS SiS SiS ", },
+	{ X86_VENDOR_HYGON,     "HygonGenuine", },
 };
 
 static const char *const x86_vendor_name[] = {
@@ -126,6 +127,7 @@ static const char *const x86_vendor_name[] = {
 	[X86_VENDOR_TRANSMETA] = "Transmeta",
 	[X86_VENDOR_NSC]       = "NSC",
 	[X86_VENDOR_SIS]       = "SiS",
+	[X86_VENDOR_HYGON]     = "Hygon",
 };
 
 static const char *cpu_vendor_name(int vendor)

src/arch/x86/gdt.c

@@ -16,6 +16,7 @@
 #include <types.h>
 #include <string.h>
 #include <cbmem.h>
+#include <commonlib/helpers.h>
 #include <console/console.h>
 #include <cpu/x86/gdt.h>
 
@@ -46,7 +47,7 @@ static void move_gdt(int is_recovery)
 	newgdt = cbmem_find(CBMEM_ID_GDT);
 	num_gdt_bytes = (uintptr_t)&gdt_end - (uintptr_t)&gdt;
 	if (!newgdt) {
-		newgdt = cbmem_add(CBMEM_ID_GDT, ALIGN(num_gdt_bytes, 512));
+		newgdt = cbmem_add(CBMEM_ID_GDT, ALIGN_UP(num_gdt_bytes, 512));
 		if (!newgdt) {
 			printk(BIOS_ERR, "Error: Could not relocate GDT.\n");
 			return;

src/arch/x86/include/arch/acpi.h

@@ -82,7 +82,7 @@ enum acpi_tables {
 	BERT, DBG2, DMAR, DSDT, FACS, FADT, HEST, HPET, IVRS, MADT, MCFG,
 	RSDP, RSDT, SLIT, SRAT, SSDT, TCPA, TPM2, XSDT, ECDT,
 	/* Additional proprietary tables used by coreboot */
-	VFCT, NHLT
+	VFCT, NHLT, SPMI
 };
 
 /* RSDP (Root System Description Pointer) */
@@ -782,6 +782,43 @@ enum acpi_upc_type {
 	UPC_TYPE_HUB
 };
 
+enum acpi_ipmi_interface_type {
+	IPMI_INTERFACE_RESERVED = 0,
+	IPMI_INTERFACE_KCS,
+	IPMI_INTERFACE_SMIC,
+	IPMI_INTERFACE_BT,
+	IPMI_INTERFACE_SSIF,
+};
+
+#define ACPI_IPMI_PCI_DEVICE_FLAG	(1 << 0)
+#define ACPI_IPMI_INT_TYPE_SCI		(1 << 0)
+#define ACPI_IPMI_INT_TYPE_APIC		(1 << 1)
+
+/* ACPI IPMI 2.0 */
+struct acpi_spmi {
+	struct acpi_table_header header;
+	u8 interface_type;
+	u8 reserved;
+	u16 specification_revision;
+	u8 interrupt_type;
+	u8 gpe;
+	u8 reserved2;
+	u8 pci_device_flag;
+
+	u32 global_system_interrupt;
+	acpi_addr_t base_address;
+	union {
+		struct {
+			u8 pci_segment_group;
+			u8 pci_bus;
+			u8 pci_device;
+			u8 pci_function;
+		};
+		u8 uid[4];
+	};
+	u8 reserved3;
+} __packed;
+
 unsigned long fw_cfg_acpi_tables(unsigned long start);
 
 /* These are implemented by the target port or north/southbridge. */
@@ -834,6 +871,15 @@ void acpi_create_vfct(struct device *device,
 				struct acpi_vfct *vfct_struct,
 				unsigned long current));
 
+void acpi_create_ipmi(struct device *device,
+		      struct acpi_spmi *spmi,
+		      const u16 ipmi_revision,
+		      const acpi_addr_t *addr,
+		      const enum acpi_ipmi_interface_type type,
+		      const s8 gpe_interrupt,
+		      const u32 apic_interrupt,
+		      const u32 uid);
+
 void acpi_create_ivrs(acpi_ivrs_t *ivrs,
 		      unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct,
 		      unsigned long current));
@@ -958,7 +1004,7 @@ static inline int acpi_is_wakeup_s4(void) { return 0; }
 
 static inline uintptr_t acpi_align_current(uintptr_t current)
 {
-	return ALIGN(current, 16);
+	return ALIGN_UP(current, 16);
 }
 
 /* ACPI table revisions should match the revision of the ACPI spec

src/arch/x86/include/arch/cpu.h

@@ -152,6 +152,7 @@ static inline unsigned int cpuid_edx(unsigned int op)
 #define X86_VENDOR_TRANSMETA  8
 #define X86_VENDOR_NSC        9
 #define X86_VENDOR_SIS       10
+#define X86_VENDOR_HYGON     11
 #define X86_VENDOR_ANY     0xfe
 #define X86_VENDOR_UNKNOWN 0xff
 

src/arch/x86/include/arch/early_variables.h

@@ -17,6 +17,7 @@
 #define ARCH_EARLY_VARIABLES_H
 
 #include <arch/symbols.h>
+#include <commonlib/helpers.h>
 #include <stdlib.h>
 
 #if ENV_CACHE_AS_RAM && !CONFIG(NO_CAR_GLOBAL_MIGRATION)
@@ -69,7 +70,7 @@ int car_active(void);
 static inline size_t car_data_size(void)
 {
 	size_t car_size = _car_relocatable_data_size;
-	return ALIGN(car_size, 64);
+	return ALIGN_UP(car_size, 64);
 }
 
 static inline size_t car_object_offset(void *ptr)

src/arch/x86/pirq_routing.c

@@ -16,6 +16,7 @@
  */
 #include <console/console.h>
 #include <arch/pirq_routing.h>
+#include <commonlib/helpers.h>
 #include <string.h>
 #include <device/pci.h>
 
@@ -191,7 +192,7 @@ unsigned long copy_pirq_routing_table(unsigned long addr,
 	const struct irq_routing_table *routing_table)
 {
 	/* Align the table to be 16 byte aligned. */
-	addr = ALIGN(addr, 16);
+	addr = ALIGN_UP(addr, 16);
 
 	/* This table must be between 0xf0000 & 0x100000 */
 	printk(BIOS_INFO, "Copying Interrupt Routing Table to 0x%08lx... ",

src/arch/x86/rdrand.c

@@ -75,7 +75,6 @@ int get_random_number_64(uint64_t *rand)
 #if ENV_X86_64
 		if (rdrand_64(rand))
 			return 0;
-		else
 #endif
 		if (rdrand_32(&rand_high) && rdrand_32(&rand_low)) {
 			*rand = ((uint64_t)rand_high << 32) |

src/arch/x86/smbios.c

@@ -30,6 +30,7 @@
 #include <memory_info.h>
 #include <spd.h>
 #include <cbmem.h>
+#include <commonlib/helpers.h>
 #include <device/pci_ids.h>
 #include <device/pci_def.h>
 #include <device/pci.h>
@@ -1150,12 +1151,12 @@ unsigned long smbios_write_tables(unsigned long current)
 	int max_struct_size = 0;
 	int handle = 0;
 
-	current = ALIGN(current, 16);
+	current = ALIGN_UP(current, 16);
 	printk(BIOS_DEBUG, "%s: %08lx\n", __func__, current);
 
 	se = (struct smbios_entry *)current;
 	current += sizeof(struct smbios_entry);
-	current = ALIGN(current, 16);
+	current = ALIGN_UP(current, 16);
 
 	tables = current;
 	update_max(len, max_struct_size, smbios_write_type0(&current,
@@ -1193,7 +1194,7 @@ unsigned long smbios_write_tables(unsigned long current)
 	memcpy(se->anchor, "_SM_", 4);
 	se->length = sizeof(struct smbios_entry);
 	se->major_version = 2;
-	se->minor_version = 7;
+	se->minor_version = 8;
 	se->max_struct_size = max_struct_size;
 	se->struct_count = handle;
 	memcpy(se->intermediate_anchor_string, "_DMI_", 5);

src/arch/x86/tables.c

@@ -23,6 +23,7 @@
 #include <arch/pirq_routing.h>
 #include <arch/smp/mpspec.h>
 #include <arch/acpi.h>
+#include <commonlib/helpers.h>
 #include <string.h>
 #include <cbmem.h>
 #include <smbios.h>
@@ -36,7 +37,7 @@ static unsigned long write_pirq_table(unsigned long rom_table_end)
 
 	/* This table must be between 0x0f0000 and 0x100000 */
 	rom_table_end = write_pirq_routing_table(rom_table_end);
-	rom_table_end = ALIGN(rom_table_end, 1024);
+	rom_table_end = ALIGN_UP(rom_table_end, 1024);
 
 	/* And add a high table version for those payloads that
 	 * want to live in the F segment
@@ -68,7 +69,7 @@ static unsigned long write_mptable(unsigned long rom_table_end)
 
 	/* The smp table must be in 0-1K, 639K-640K, or 960K-1M */
 	rom_table_end = write_smp_table(rom_table_end);
-	rom_table_end = ALIGN(rom_table_end, 1024);
+	rom_table_end = ALIGN_UP(rom_table_end, 1024);
 
 	high_table_pointer = (unsigned long)cbmem_add(CBMEM_ID_MPTABLE,
 		MAX_MP_TABLE_SIZE);
@@ -114,7 +115,7 @@ static unsigned long write_acpi_table(unsigned long rom_table_end)
 		unsigned long acpi_start = high_table_pointer;
 		unsigned long new_high_table_pointer;
 
-		rom_table_end = ALIGN(rom_table_end, 16);
+		rom_table_end = ALIGN_UP(rom_table_end, 16);
 		new_high_table_pointer = write_acpi_tables(high_table_pointer);
 		if (new_high_table_pointer > (high_table_pointer
 			+ MAX_ACPI_SIZE))
@@ -146,10 +147,10 @@ static unsigned long write_acpi_table(unsigned long rom_table_end)
 			printk(BIOS_ERR,
 				"ERROR: Didn't find RSDP in high table.\n");
 		}
-		rom_table_end = ALIGN(rom_table_end + sizeof(acpi_rsdp_t), 16);
+		rom_table_end = ALIGN_UP(rom_table_end + sizeof(acpi_rsdp_t), 16);
 	} else {
 		rom_table_end = write_acpi_tables(rom_table_end);
-		rom_table_end = ALIGN(rom_table_end, 1024);
+		rom_table_end = ALIGN_UP(rom_table_end, 1024);
 	}
 
 	return rom_table_end;
@@ -168,7 +169,7 @@ static unsigned long write_smbios_table(unsigned long rom_table_end)
 
 		new_high_table_pointer =
 			smbios_write_tables(high_table_pointer);
-		rom_table_end = ALIGN(rom_table_end, 16);
+		rom_table_end = ALIGN_UP(rom_table_end, 16);
 		memcpy((void *)rom_table_end, (void *)high_table_pointer,
 			sizeof(struct smbios_entry));
 		rom_table_end += sizeof(struct smbios_entry);
@@ -184,7 +185,7 @@ static unsigned long write_smbios_table(unsigned long rom_table_end)
 		new_rom_table_end = smbios_write_tables(rom_table_end);
 		printk(BIOS_DEBUG, "SMBIOS size %ld bytes\n", new_rom_table_end
 			- rom_table_end);
-		rom_table_end = ALIGN(new_rom_table_end, 16);
+		rom_table_end = ALIGN_UP(new_rom_table_end, 16);
 	}
 
 	return rom_table_end;

src/commonlib/include/commonlib/coreboot_tables.h

@@ -44,6 +44,58 @@
  * table entries and be backwards compatible, but it is not required.
  */
 
+enum {
+	LB_TAG_UNUSED			= 0x0000,
+	LB_TAG_MEMORY			= 0x0001,
+	LB_TAG_HWRPB			= 0x0002,
+	LB_TAG_MAINBOARD		= 0x0003,
+	LB_TAG_VERSION			= 0x0004,
+	LB_TAG_EXTRA_VERSION		= 0x0005,
+	LB_TAG_BUILD			= 0x0006,
+	LB_TAG_COMPILE_TIME		= 0x0007,
+	LB_TAG_COMPILE_BY		= 0x0008,
+	LB_TAG_COMPILE_HOST		= 0x0009,
+	LB_TAG_COMPILE_DOMAIN		= 0x000a,
+	LB_TAG_COMPILER			= 0x000b,
+	LB_TAG_LINKER			= 0x000c,
+	LB_TAG_ASSEMBLER		= 0x000d,
+	LB_TAG_SERIAL			= 0x000f,
+	LB_TAG_CONSOLE			= 0x0010,
+	LB_TAG_FORWARD			= 0x0011,
+	LB_TAG_FRAMEBUFFER		= 0x0012,
+	LB_TAG_GPIO			= 0x0013,
+	LB_TAG_TIMESTAMPS		= 0x0016,
+	LB_TAG_CBMEM_CONSOLE		= 0x0017,
+	LB_TAG_MRC_CACHE		= 0x0018,
+	LB_TAG_VBNV			= 0x0019,
+	LB_TAG_VBOOT_HANDOFF		= 0x0020,
+	LB_TAG_X86_ROM_MTRR		= 0x0021,
+	LB_TAG_DMA			= 0x0022,
+	LB_TAG_RAM_OOPS			= 0x0023,
+	LB_TAG_ACPI_GNVS		= 0x0024,
+	LB_TAG_BOARD_ID			= 0x0025,
+	LB_TAG_VERSION_TIMESTAMP	= 0x0026,
+	LB_TAG_WIFI_CALIBRATION		= 0x0027,
+	LB_TAG_RAM_CODE			= 0x0028,
+	LB_TAG_SPI_FLASH		= 0x0029,
+	LB_TAG_SERIALNO			= 0x002a,
+	LB_TAG_MTC			= 0x002b,
+	LB_TAG_VPD			= 0x002c,
+	LB_TAG_SKU_ID			= 0x002d,
+	LB_TAG_BOOT_MEDIA_PARAMS	= 0x0030,
+	LB_TAG_CBMEM_ENTRY		= 0x0031,
+	LB_TAG_TSC_INFO			= 0x0032,
+	LB_TAG_MAC_ADDRS		= 0x0033,
+	LB_TAG_VBOOT_WORKBUF		= 0x0034,
+	LB_TAG_MMC_INFO			= 0x0035,
+	LB_TAG_TCPA_LOG			= 0x0036,
+	LB_TAG_CMOS_OPTION_TABLE	= 0x00c8,
+	LB_TAG_OPTION			= 0x00c9,
+	LB_TAG_OPTION_ENUM		= 0x00ca,
+	LB_TAG_OPTION_DEFAULTS		= 0x00cb,
+	LB_TAG_OPTION_CHECKSUM		= 0x00cc,
+};
+
 /* Since coreboot is usually compiled 32bit, gcc will align 64bit
  * types to 32bit boundaries. If the coreboot table is dumped on a
  * 64bit system, a uint64_t would be aligned to 64bit boundaries,
@@ -97,9 +149,6 @@ struct lb_record {
 	uint32_t size;		/* size of record (in bytes) */
 };
 
-#define LB_TAG_UNUSED		0x0000
-
-#define LB_TAG_MEMORY		0x0001
 
 struct lb_memory_range {
 	struct lb_uint64 start;
@@ -120,14 +169,12 @@ struct lb_memory {
 	struct lb_memory_range map[0];
 };
 
-#define LB_TAG_HWRPB		0x0002
 struct lb_hwrpb {
 	uint32_t tag;
 	uint32_t size;
 	uint64_t hwrpb;
 };
 
-#define LB_TAG_MAINBOARD	0x0003
 struct lb_mainboard {
 	uint32_t tag;
 	uint32_t size;
@@ -136,23 +183,12 @@ struct lb_mainboard {
 	uint8_t  strings[0];
 };
 
-#define LB_TAG_VERSION		0x0004
-#define LB_TAG_EXTRA_VERSION	0x0005
-#define LB_TAG_BUILD		0x0006
-#define LB_TAG_COMPILE_TIME	0x0007
-#define LB_TAG_COMPILE_BY	0x0008
-#define LB_TAG_COMPILE_HOST	0x0009
-#define LB_TAG_COMPILE_DOMAIN	0x000a
-#define LB_TAG_COMPILER		0x000b
-#define LB_TAG_LINKER		0x000c
-#define LB_TAG_ASSEMBLER	0x000d
 struct lb_string {
 	uint32_t tag;
 	uint32_t size;
 	uint8_t  string[0];
 };
 
-#define LB_TAG_VERSION_TIMESTAMP	0x0026
 struct lb_timestamp {
 	uint32_t tag;
 	uint32_t size;
@@ -162,7 +198,6 @@ struct lb_timestamp {
 
 /* 0xe is taken by v3 */
 
-#define LB_TAG_SERIAL		0x000f
 struct lb_serial {
 	uint32_t tag;
 	uint32_t size;
@@ -189,7 +224,6 @@ struct lb_serial {
 	uint32_t uart_pci_addr;
 };
 
-#define LB_TAG_CONSOLE		0x0010
 struct lb_console {
 	uint32_t tag;
 	uint32_t size;
@@ -204,7 +238,6 @@ struct lb_console {
 #define LB_TAG_CONSOLE_EHCI		5
 #define LB_TAG_CONSOLE_SERIAL8250MEM	6
 
-#define LB_TAG_FORWARD		0x0011
 struct lb_forward {
 	uint32_t tag;
 	uint32_t size;
@@ -250,7 +283,6 @@ struct lb_forward {
  * fields described above. It may, however, only implement a subset
  * of the possible color formats.
  */
-#define LB_TAG_FRAMEBUFFER	0x0012
 struct lb_framebuffer {
 	uint32_t tag;
 	uint32_t size;
@@ -270,7 +302,6 @@ struct lb_framebuffer {
 	uint8_t reserved_mask_size;
 };
 
-#define LB_TAG_GPIO	0x0013
 
 struct lb_gpio {
 	uint32_t port;
@@ -290,12 +321,6 @@ struct lb_gpios {
 	struct lb_gpio gpios[0];
 };
 
-#define LB_TAG_VBNV		0x0019
-#define LB_TAG_VBOOT_HANDOFF	0x0020
-#define LB_TAG_VBOOT_WORKBUF	0x0034
-#define LB_TAG_DMA		0x0022
-#define LB_TAG_RAM_OOPS		0x0023
-#define LB_TAG_MTC		0x002b
 struct lb_range {
 	uint32_t tag;
 	uint32_t size;
@@ -306,13 +331,6 @@ struct lb_range {
 
 void lb_ramoops(struct lb_header *header);
 
-#define LB_TAG_TIMESTAMPS	0x0016
-#define LB_TAG_CBMEM_CONSOLE	0x0017
-#define LB_TAG_MRC_CACHE	0x0018
-#define LB_TAG_ACPI_GNVS	0x0024
-#define LB_TAG_TCPA_LOG		0x0036
-#define LB_TAG_WIFI_CALIBRATION	0x0027
-#define LB_TAG_VPD		0x002c
 struct lb_cbmem_ref {
 	uint32_t tag;
 	uint32_t size;
@@ -320,7 +338,6 @@ struct lb_cbmem_ref {
 	uint64_t cbmem_addr;
 };
 
-#define LB_TAG_X86_ROM_MTRR	0x0021
 struct lb_x86_rom_mtrr {
 	uint32_t tag;
 	uint32_t size;
@@ -328,9 +345,6 @@ struct lb_x86_rom_mtrr {
 	uint32_t index;
 };
 
-#define LB_TAG_BOARD_ID		0x0025
-#define LB_TAG_RAM_CODE		0x0028
-#define LB_TAG_SKU_ID		0x002d
 
 struct lb_strapping_id {
 	uint32_t tag;
@@ -338,7 +352,6 @@ struct lb_strapping_id {
 	uint32_t id_code;
 };
 
-#define LB_TAG_SPI_FLASH	0x0029
 struct lb_spi_flash {
 	uint32_t tag;
 	uint32_t size;
@@ -347,7 +360,6 @@ struct lb_spi_flash {
 	uint32_t erase_cmd;
 };
 
-#define LB_TAG_BOOT_MEDIA_PARAMS 0x0030
 struct lb_boot_media_params {
 	uint32_t tag;
 	uint32_t size;
@@ -361,7 +373,6 @@ struct lb_boot_media_params {
 /*
  * There can be more than one of these records as there is one per cbmem entry.
  */
-#define LB_TAG_CBMEM_ENTRY 0x0031
 struct lb_cbmem_entry {
 	uint32_t tag;
 	uint32_t size;
@@ -371,7 +382,6 @@ struct lb_cbmem_entry {
 	uint32_t id;
 };
 
-#define LB_TAG_TSC_INFO 0x0032
 struct lb_tsc_info {
 	uint32_t tag;
 	uint32_t size;
@@ -379,13 +389,11 @@ struct lb_tsc_info {
 	uint32_t freq_khz;
 };
 
-#define LB_TAG_MAC_ADDRS	0x0033
 struct mac_address {
 	uint8_t mac_addr[6];
 	uint8_t pad[2];		/* Pad it to 8 bytes to keep it simple. */
 };
 
-#define LB_TAG_MMC_INFO		0x0035
 struct lb_mmc_info {
 	uint32_t tag;
 	uint32_t size;
@@ -407,11 +415,9 @@ struct lb_macs {
 	struct mac_address mac_addrs[0];
 };
 
-#define LB_TAG_SERIALNO		0x002a
 #define MAX_SERIALNO_LENGTH	32
 
 /* The following structures are for the cmos definitions table */
-#define LB_TAG_CMOS_OPTION_TABLE 200
 /* cmos header record */
 struct cmos_option_table {
 	uint32_t tag;               /* CMOS definitions table type */
@@ -426,7 +432,6 @@ struct cmos_option_table {
  * starts at the beginning of the byte and the length is
  * fills complete bytes.
  */
-#define LB_TAG_OPTION 201
 struct cmos_entries {
 	uint32_t tag;                /* entry type */
 	uint32_t size;               /* length of this record */
@@ -444,7 +449,6 @@ struct cmos_entries {
  * This record is variable length.  The text field may be
  * shorter than CMOS_MAX_TEXT_LENGTH.
  */
-#define LB_TAG_OPTION_ENUM 202
 struct cmos_enums {
 	uint32_t tag;		     /* enumeration type */
 	uint32_t size;		     /* length of this record */
@@ -458,7 +462,6 @@ struct cmos_enums {
 /* cmos defaults record
  * This record contains default settings for the cmos ram.
  */
-#define LB_TAG_OPTION_DEFAULTS 203
 struct cmos_defaults {
 	uint32_t tag;                /* default type */
 	uint32_t size;               /* length of this record */
@@ -468,7 +471,6 @@ struct cmos_defaults {
 	uint8_t default_set[CMOS_IMAGE_BUFFER_SIZE]; /* default settings */
 };
 
-#define LB_TAG_OPTION_CHECKSUM 204
 struct	cmos_checksum {
 	uint32_t tag;
 	uint32_t size;

src/commonlib/storage/bouncebuf.h

@@ -88,7 +88,7 @@ int bounce_buffer_stop(struct bounce_buffer *state);
 #define ALLOC_CACHE_ALIGN_BUFFER(type, name, size)                   \
 	char __##name[ROUND(size * sizeof(type), DMA_MINALIGN) +     \
 		      DMA_MINALIGN - 1];                             \
-	type *name = (type *) ALIGN((uintptr_t)__##name, DMA_MINALIGN)
+	type *name = (type *) ALIGN_UP((uintptr_t)__##name, DMA_MINALIGN)
 #ifndef ARCH_DMA_MINALIGN
 #define ARCH_DMA_MINALIGN (DMA_MINALIGN)
 #endif

src/commonlib/storage/storage.h

@@ -23,7 +23,7 @@
 #define ALLOC_CACHE_ALIGN_BUFFER(type, name, size)                   \
 	char __##name[ROUND(size * sizeof(type), DMA_MINALIGN) +     \
 		      DMA_MINALIGN - 1];                             \
-	type *name = (type *) ALIGN((uintptr_t)__##name, DMA_MINALIGN)
+	type *name = (type *) ALIGN_UP((uintptr_t)__##name, DMA_MINALIGN)
 
 /* NOOPs mirroring ARM's cache API, since x86 devices usually cache snoop */
 #define dcache_invalidate_by_mva(addr, len)

src/console/vtxprintf.c

@@ -16,6 +16,7 @@
  */
 
 #include <console/vtxprintf.h>
+#include <ctype.h>
 #include <string.h>
 
 #define call_tx(x) tx_byte(x, data)

src/cpu/allwinner/a10/clock.c

@@ -22,7 +22,6 @@
 #include <console/console.h>
 #include <delay.h>
 #include <lib.h>
-#include <stdlib.h>
 
 static struct a10_ccm *const ccm = (void *)A1X_CCM_BASE;
 

src/cpu/amd/car/post_cache_as_ram.c

@@ -16,10 +16,12 @@
  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  * GNU General Public License for more details.
  */
+
 #include <string.h>
 #include <console/console.h>
 #include <arch/stages.h>
 #include <arch/early_variables.h>
+#include <commonlib/helpers.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/mtrr.h>
 #include <cpu/amd/car.h>
@@ -45,7 +47,7 @@
 static size_t backup_size(void)
 {
 	size_t car_size = car_data_size();
-	return ALIGN(car_size + 1024, 1024);
+	return ALIGN_UP(car_size + 1024, 1024);
 }
 
 static void memcpy_(void *d, const void *s, size_t len)

src/cpu/amd/family_10h-family_15h/init_cpus.c

@@ -504,10 +504,9 @@ u32 init_cpus(u32 cpu_init_detectedx, struct sys_info *sysinfo)
 		if (is_fam15h()) {
 			/* core 1 on node 0 is special; to avoid corrupting the
 			 * BSP do not alter MTRRs on that core */
-			if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
-				fam15_bsp_core1_apicid = CONFIG_APIC_ID_OFFSET + 1;
-			else
 			fam15_bsp_core1_apicid = 1;
+			if (CONFIG(ENABLE_APIC_EXT_ID) && (CONFIG_APIC_ID_OFFSET > 0))
+				fam15_bsp_core1_apicid += CONFIG_APIC_ID_OFFSET;
 
 			if (apicid == fam15_bsp_core1_apicid)
 				set_mtrrs = 0;

src/cpu/amd/family_10h-family_15h/init_cpus.h

@@ -16,7 +16,6 @@
 #ifndef INIT_CPUS_H
 #define INIT_CPUS_H
 
-#include <stdlib.h>
 #include <cpu/x86/lapic.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/amd/msr.h>

src/cpu/amd/family_10h-family_15h/powernow_acpi.c

@@ -259,8 +259,6 @@ void amd_generate_powernow(u32 pcontrol_blk, u8 plen, u8 onlyBSP)
 	else if (mctGetLogicalCPUID(0) & AMD_FAM15_ALL)
 		boost_count = (dtemp >> 2) & 0x7;
 
-	Pstate_num = 0;
-
 	/* See if the CPUID(0x80000007) returned EDX[7]==1b */
 	cpuid1 = cpuid(0x80000007);
 	if ((cpuid1.edx & 0x80) != 0x80) {

src/cpu/amd/pi/00730F01/Kconfig

@@ -16,6 +16,8 @@
 config CPU_AMD_PI_00730F01
 	bool
 	select X86_AMD_FIXED_MTRRS
+	select SUPPORT_CPU_UCODE_IN_CBFS
+	select MICROCODE_BLOB_UNDISCLOSED
 
 if CPU_AMD_PI_00730F01
 

src/cpu/amd/pi/00730F01/Makefile.inc

@@ -14,10 +14,14 @@
 #
 
 romstage-y += fixme.c
+romstage-y += update_microcode.c
+romstage-y += microcode_fam16h.c
 
 ramstage-y += fixme.c
 ramstage-y += chip_name.c
 ramstage-y += model_16_init.c
+ramstage-y += update_microcode.c
+ramstage-y += microcode_fam16h.c
 
 subdirs-y += ../../mtrr
 subdirs-y += ../../../x86/tsc

src/cpu/amd/pi/00730F01/microcode_fam16h.c

@@ -0,0 +1,169 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2015 Raptor Engineering
+ * Copyright (C) 2019 PC Engines GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <console/console.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/microcode.h>
+#include <cbfs.h>
+#include <arch/io.h>
+#include <smp/spinlock.h>
+
+/*
+ * Values and header structure from:
+ * BKDG for AMD Family 16h Models 30h-3Fh Processors
+ * 52740 Rev 3.06 - March 18, 2016
+ */
+
+#define F16H_MPB_MAX_SIZE 3458
+#define F16H_MPB_DATA_OFFSET 32
+
+ /*
+  * STRUCTURE OF A MICROCODE (UCODE) FILE FOR FAM16h
+  *	Microcode Patch Block
+  *		Microcode Header
+  *		Microcode "Blob"
+  *		...
+  *		...
+  *		(end of file)
+  *
+  *
+  * MICROCODE HEADER (offset 0 bytes from start of file)
+  * Total size = 32 bytes
+  *	[0:3]	Date code		(32 bits)
+  *	[4:7]	Patch level		(32 bits)
+  *	[8:9]	Microcode patch data ID (16 bits)
+  *	[10:15]	Reserved		(48 bits)
+  *	[16:19]	Chipset 1 device ID	(32 bits)
+  *	[20:23]	Chipset 2 device ID	(32 bits)
+  *	[24:25]	Processor Revisions ID	(16 bits)
+  *	[26]	Chipset 1 revision ID	(8 bits)
+  *	[27]	Chipset 2 revision ID	(8 bits)
+  *	[28:31]	Reserved		(32 bits)
+  *
+  * MICROCODE BLOB (offset += 32)
+  * Total size = m bytes
+  *
+  */
+
+struct microcode {
+	uint32_t date_code;
+	uint32_t patch_id;
+
+	uint16_t mc_patch_data_id;
+	uint8_t reserved1[6];
+
+	uint32_t chipset1_dev_id;
+	uint32_t chipset2_dev_id;
+
+	uint16_t processor_rev_id;
+
+	uint8_t chipset1_rev_id;
+	uint8_t chipset2_rev_id;
+
+	uint8_t reserved2[4];
+
+	uint8_t m_patch_data[F16H_MPB_MAX_SIZE-F16H_MPB_DATA_OFFSET];
+
+};
+
+static void apply_microcode_patch(const struct microcode *m)
+{
+	uint32_t new_patch_id;
+	msr_t msr;
+
+	/* apply patch */
+	msr.hi = 0;
+	msr.lo = (uint32_t)m;
+
+	wrmsr(0xc0010020, msr);
+
+	printk(BIOS_DEBUG, "microcode: patch id to apply = 0x%08x\n",
+	       m->patch_id);
+
+	/* patch authentication */
+	msr = rdmsr(0x8b);
+	new_patch_id = msr.lo;
+
+	printk(BIOS_DEBUG, "microcode: updated to patch id = 0x%08x %s\n",
+	       new_patch_id,
+	       (new_patch_id == m->patch_id) ? "success" : "fail");
+}
+
+static void amd_update_microcode(const void *ucode,  size_t ucode_len,
+				uint32_t equivalent_processor_rev_id)
+{
+	const struct microcode *m;
+	const uint8_t *c = ucode;
+
+	m = (struct microcode *)c;
+
+	if (m->processor_rev_id == equivalent_processor_rev_id)
+		apply_microcode_patch(m);
+}
+
+void amd_update_microcode_from_cbfs(uint32_t equivalent_processor_rev_id)
+{
+	const void *ucode;
+	size_t ucode_len;
+
+	if (equivalent_processor_rev_id == 0) {
+		printk(BIOS_DEBUG, "microcode: rev id not found. "
+				   "Skipping microcode patch!\n");
+		return;
+	}
+#ifdef __PRE_RAM__
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+		spin_lock(romstage_microcode_cbfs_lock());
+#endif
+#endif
+	ucode = cbfs_boot_map_with_leak("cpu_microcode_blob.bin",
+					CBFS_TYPE_MICROCODE,
+					&ucode_len);
+	if (!ucode) {
+		printk(BIOS_DEBUG, "cpu_microcode_blob.bin not found. "
+				   "Skipping updates.\n");
+#ifdef __PRE_RAM__
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+			spin_unlock(romstage_microcode_cbfs_lock());
+#endif
+#endif
+		return;
+	}
+
+	if (ucode_len > F16H_MPB_MAX_SIZE ||
+	    ucode_len < F16H_MPB_DATA_OFFSET) {
+		printk(BIOS_DEBUG, "microcode file invalid. Skipping "
+				   "updates.\n");
+#ifdef __PRE_RAM__
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+		spin_unlock(romstage_microcode_cbfs_lock());
+#endif
+#endif
+		return;
+	}
+
+	amd_update_microcode(ucode, ucode_len,
+				equivalent_processor_rev_id);
+
+#ifdef __PRE_RAM__
+#if CONFIG(HAVE_ROMSTAGE_MICROCODE_CBFS_SPINLOCK)
+	spin_unlock(romstage_microcode_cbfs_lock());
+#endif
+#endif
+
+}

src/cpu/amd/pi/00730F01/model_16_init.c

@@ -14,6 +14,7 @@
  */
 
 #include <console/console.h>
+#include <cpu/amd/microcode.h>
 #include <cpu/x86/msr.h>
 #include <cpu/amd/msr.h>
 #include <cpu/x86/mtrr.h>
@@ -98,6 +99,8 @@ static void model_16_init(struct device *dev)
 	msr = rdmsr(HWCR_MSR);
 	msr.lo |= (1 << 0);
 	wrmsr(HWCR_MSR, msr);
+
+	update_microcode(cpuid_eax(1));
 }
 
 static struct device_operations cpu_dev_ops = {

src/cpu/amd/pi/00730F01/update_microcode.c

@@ -0,0 +1,58 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Timothy Pearson <tpearson@raptorengineeringinc.com>, Raptor Engineering
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ * Copyright (C) 2019 PC Engines GmbH
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <stdint.h>
+#include <cpu/amd/microcode.h>
+
+struct id_mapping {
+	uint32_t orig_id;
+	uint16_t new_id;
+};
+
+static u16 get_equivalent_processor_rev_id(u32 orig_id)
+{
+	static const struct id_mapping id_mapping_table[] = {
+		/* Family 16h */
+
+	/* TODO This equivalent processor revisions ID needs verification */
+		{ 0x730f01, 0x7301 },
+
+		/* Array terminator */
+		{ 0xffffff, 0x0000 },
+	};
+
+	u32 new_id;
+	int i;
+
+	new_id = 0;
+
+	for (i = 0; id_mapping_table[i].orig_id != 0xffffff; i++) {
+		if (id_mapping_table[i].orig_id == orig_id) {
+			new_id = id_mapping_table[i].new_id;
+			break;
+		}
+	}
+
+	return new_id;
+}
+
+void update_microcode(u32 cpu_deviceid)
+{
+	u32 equivalent_processor_rev_id =
+				get_equivalent_processor_rev_id(cpu_deviceid);
+	amd_update_microcode_from_cbfs(equivalent_processor_rev_id);
+}

src/cpu/intel/car/romstage.c

@@ -16,6 +16,7 @@
 #include <cpu/intel/romstage.h>
 #include <cpu/x86/mtrr.h>
 #include <arch/symbols.h>
+#include <commonlib/helpers.h>
 #include <program_loading.h>
 #include <timestamp.h>
 

src/cpu/intel/common/fsb.c

@@ -46,6 +46,7 @@ static int get_fsb(void)
 		case 0x3a: /* IvyBridge BCLK fixed at 100MHz */
 		case 0x3c: /* Haswell BCLK fixed at 100MHz */
 		case 0x45: /* Haswell-ULT BCLK fixed at 100MHz */
+		case 0x4d: /* Rangeley BCLK fixed at 100MHz */
 			ret = 100;
 			break;
 		}

src/cpu/intel/haswell/Makefile.inc

@@ -17,6 +17,9 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c
 smm-$(CONFIG_HAVE_SMI_HANDLER) += tsc_freq.c
 
 ifneq ($(CONFIG_TSC_MONOTONIC_TIMER),y)
+bootblock-y += monotonic_timer.c
+romstage-y += monotonic_timer.c
+postcar-y += monotonic_timer.c
 ramstage-y += monotonic_timer.c
 smm-y += monotonic_timer.c
 endif
@@ -25,6 +28,7 @@ bootblock-y += ../car/non-evict/cache_as_ram.S
 bootblock-y += ../car/bootblock.c
 bootblock-y += ../../x86/early_reset.S
 bootblock-y += bootblock.c
+bootblock-y += tsc_freq.c
 
 postcar-y += ../car/non-evict/exit_car.S
 
@@ -39,5 +43,5 @@ subdirs-y += ../microcode
 subdirs-y += ../turbo
 subdirs-y += ../common
 
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306cx/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3c-*)
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_4065x/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-45-*)

src/cpu/intel/haswell/finalize.c

@@ -15,7 +15,6 @@
  */
 
 #include <stdint.h>
-#include <stdlib.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include "haswell.h"

src/cpu/intel/haswell/haswell.h

@@ -34,7 +34,7 @@
 /* Haswell bus clock is fixed at 100MHz */
 #define HASWELL_BCLK			100
 
-#define CORE_THREAD_COUNT_MSR		0x35
+#define MSR_CORE_THREAD_COUNT		0x35
 #define MSR_FEATURE_CONFIG		0x13c
 #define MSR_FLEX_RATIO			0x194
 #define  FLEX_RATIO_LOCK		(1 << 20)

src/cpu/intel/haswell/haswell_init.c

@@ -732,7 +732,7 @@ static int get_cpu_count(void)
 	int num_threads;
 	int num_cores;
 
-	msr = rdmsr(CORE_THREAD_COUNT_MSR);
+	msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	num_threads = (msr.lo >> 0) & 0xffff;
 	num_cores = (msr.lo >> 16) & 0xffff;
 	printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",

src/cpu/intel/haswell/romstage.c

@@ -24,6 +24,7 @@
 #include <device/pci_def.h>
 #include <cpu/x86/lapic.h>
 #include <cbmem.h>
+#include <commonlib/helpers.h>
 #include <program_loading.h>
 #include <romstage_handoff.h>
 #include <vendorcode/google/chromeos/chromeos.h>

src/cpu/intel/model_1067x/Makefile.inc

@@ -4,4 +4,4 @@ subdirs-y += ../../x86/name
 subdirs-y += ../common
 subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
 
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_1067x/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-17-*)

src/cpu/intel/model_106cx/Makefile.inc

@@ -4,4 +4,4 @@ subdirs-y += ../common
 subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
 ramstage-$(CONFIG_PARALLEL_MP) += ../model_1067x/mp_init.c
 
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_106cx/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-1c-*)

src/cpu/intel/model_2065x/Makefile.inc

@@ -23,7 +23,7 @@ romstage-y += stage_cache.c
 ramstage-y += stage_cache.c
 postcar-y += stage_cache.c
 
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_2065x/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-25-*)
 
 cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
 postcar-y += ../car/non-evict/exit_car.S

src/cpu/intel/model_2065x/finalize.c

@@ -15,7 +15,6 @@
  */
 
 #include <stdint.h>
-#include <stdlib.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/speedstep.h>

src/cpu/intel/model_2065x/model_2065x.h

@@ -20,7 +20,7 @@
 /* Nehalem bus clock is fixed at 133MHz */
 #define NEHALEM_BCLK		133
 
-#define CORE_THREAD_COUNT_MSR		0x35
+#define MSR_CORE_THREAD_COUNT		0x35
 #define MSR_FEATURE_CONFIG		0x13c
 #define MSR_FLEX_RATIO			0x194
 #define  FLEX_RATIO_LOCK		(1 << 20)

src/cpu/intel/model_2065x/model_2065x_init.c

@@ -287,7 +287,7 @@ static int get_cpu_count(void)
 	int num_threads;
 	int num_cores;
 
-	msr = rdmsr(CORE_THREAD_COUNT_MSR);
+	msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	num_threads = (msr.lo >> 0) & 0xffff;
 	num_cores = (msr.lo >> 16) & 0xffff;
 	printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",

src/cpu/intel/model_206ax/Makefile.inc

@@ -28,8 +28,8 @@ romstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 postcar-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 ramstage-$(CONFIG_CACHE_RELOCATED_RAMSTAGE_OUTSIDE_CBMEM) += stage_cache.c
 
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_206ax/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-2a-*)
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_306ax/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-3a-*)
 
 cpu_incs-y += $(src)/cpu/intel/car/non-evict/cache_as_ram.S
 postcar-y += ../car/non-evict/exit_car.S

src/cpu/intel/model_206ax/finalize.c

@@ -15,7 +15,6 @@
  */
 
 #include <stdint.h>
-#include <stdlib.h>
 #include <arch/cpu.h>
 #include <cpu/x86/msr.h>
 #include <cpu/intel/speedstep.h>

src/cpu/intel/model_206ax/model_206ax.h

@@ -22,7 +22,7 @@
 /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
 #define SANDYBRIDGE_BCLK		100
 
-#define CORE_THREAD_COUNT_MSR		0x35
+#define MSR_CORE_THREAD_COUNT		0x35
 #define MSR_FEATURE_CONFIG		0x13c
 #define MSR_FLEX_RATIO			0x194
 #define  FLEX_RATIO_LOCK		(1 << 20)

src/cpu/intel/model_206ax/model_206ax_init.c

@@ -513,7 +513,7 @@ static int get_cpu_count(void)
 	int num_threads;
 	int num_cores;
 
-	msr = rdmsr(CORE_THREAD_COUNT_MSR);
+	msr = rdmsr(MSR_CORE_THREAD_COUNT);
 	num_threads = (msr.lo >> 0) & 0xffff;
 	num_cores = (msr.lo >> 16) & 0xffff;
 	printk(BIOS_DEBUG, "CPU has %u cores, %u threads enabled.\n",

src/cpu/intel/model_65x/Makefile.inc

@@ -16,4 +16,4 @@
 
 ramstage-y += model_65x_init.c
 
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_65x/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-05-*)

src/cpu/intel/model_67x/Makefile.inc

@@ -16,4 +16,4 @@
 
 ramstage-y += model_67x_init.c
 
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_67x/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-07-*)

src/cpu/intel/model_68x/Makefile.inc

@@ -17,4 +17,4 @@
 ramstage-y += model_68x_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_68x/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-08-*)

src/cpu/intel/model_6bx/Makefile.inc

@@ -1,4 +1,4 @@
 ramstage-y += model_6bx_init.c
 subdirs-y += ../../x86/name
 
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6bx/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0b-*)

src/cpu/intel/model_6ex/Makefile.inc

@@ -4,4 +4,4 @@ subdirs-y += ../common
 subdirs-$(CONFIG_SMM_TSEG) += ../smm/gen1
 ramstage-y += ../model_1067x/mp_init.c
 
-cpu_microcode_bins += 3rdparty/blobs/cpu/intel/model_6ex/microcode.bin
+cpu_microcode_bins += $(wildcard 3rdparty/intel-microcode/intel-ucode/06-0e-*)