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soc/intel/common: Use SoC specific routine to read/write MTRRs

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The registers associated with the MTRRs for Quark are referenced through
a port on the host bridge.  Support the standard configurations by
providing a weak routines which just do a rdmsr/wrmsr.

Testing:
*  Edit the src/mainboard/intel/galileo/Makefile.inc file
   *  Add "select DISPLAY_MTRRS"
   *  Add "select HAVE_FSP_PDAT_FILE"
   *  Add "select HAVE_FSP_RAW_BIN"
   *  Add "select HAVE_RMU_FILE"
*  Place the FSP.bin file in the location specified by CONFIG_FSP_FILE
*  Place the pdat.bin files in the location specified by
CONFIG_FSP_PDAT_FILE
*  Place the rmu.bin file in the location specified by CONFIG_RMU_FILE
*  Testing is successful if:
   *  The MTRRs are displayed and
   *  The message "FspTempRamExit returned successfully" is displayed

TEST=Build and run on Galileo

Change-Id: If2fea66d4b054be4555f5f172ea5945620648325
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: https://review.coreboot.org/13529
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins)
This commit is contained in:
Lee Leahy
2016-01-29 14:35:13 -08:00
committed by Leroy P Leahy
parent 05c0215ff3
commit 9590992402
5 changed files with 48 additions and 13 deletions
Download Patch File Download Diff File Expand all files Collapse all files

7
src/soc/intel/common/Kconfig
View File

@@ -41,6 +41,13 @@ config SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
bool
default n
config SOC_SETS_MTRRS
bool
default n
help
The SoC needs uses different access methods for reading and writing
the MTRRs. Use SoC specific routines to handle the MTRR access.
config MMA
bool "enable MMA (Memory Margin Analysis) support"
default n

26
src/soc/intel/common/util.c
View File

@@ -1,7 +1,7 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2015 Intel Corporation.
* Copyright (C) 2015-2016 Intel Corporation.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -15,7 +15,6 @@
#include <arch/cpu.h>
#include <console/console.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <soc/intel/common/util.h>
#include <stddef.h>
@@ -25,12 +24,12 @@ uint32_t soc_get_variable_mtrr_count(uint64_t *msr)
union {
uint64_t u64;
msr_t s;
} mttrcap;
} mtrrcap;
mttrcap.s = rdmsr(MTRR_CAP_MSR);
mtrrcap.s = soc_mtrr_read(MTRR_CAP_MSR);
if (msr != NULL)
*msr = mttrcap.u64;
return mttrcap.u64 & MTRR_CAP_VCNT;
*msr = mtrrcap.u64;
return mtrrcap.u64 & MTRR_CAP_VCNT;
}
static const char *soc_display_mtrr_type(uint32_t type)
@@ -84,7 +83,7 @@ static void soc_display_4k_mtrr(uint32_t msr_reg, uint32_t starting_address,
msr_t s;
} msr;
msr.s = rdmsr(msr_reg);
msr.s = soc_mtrr_read(msr_reg);
printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name);
soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x1000);
}
@@ -97,7 +96,7 @@ static void soc_display_16k_mtrr(uint32_t msr_reg, uint32_t starting_address,
msr_t s;
} msr;
msr.s = rdmsr(msr_reg);
msr.s = soc_mtrr_read(msr_reg);
printk(BIOS_DEBUG, "0x%016llx: %s\n", msr.u64, name);
soc_display_mtrr_fixed_types(msr.u64, starting_address, 0x4000);
}
@@ -109,7 +108,7 @@ static void soc_display_64k_mtrr(void)
msr_t s;
} msr;
msr.s = rdmsr(MTRR_FIX_64K_00000);
msr.s = soc_mtrr_read(MTRR_FIX_64K_00000);
printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_FIX64K_00000\n", msr.u64);
soc_display_mtrr_fixed_types(msr.u64, 0, 0x10000);
}
@@ -137,12 +136,13 @@ static void soc_display_mtrr_def_type(void)
msr_t s;
} msr;
msr.s = rdmsr(MTRR_DEF_TYPE_MSR);
msr.s = soc_mtrr_read(MTRR_DEF_TYPE_MSR);
printk(BIOS_DEBUG, "0x%016llx: IA32_MTRR_DEF_TYPE:%s%s %s\n",
msr.u64,
(msr.u64 & MTRR_DEF_TYPE_EN) ? " E," : "",
(msr.u64 & MTRR_DEF_TYPE_FIX_EN) ? " FE," : "",
soc_display_mtrr_type((uint32_t)(msr.u64 & MTRR_DEF_TYPE_MASK)));
soc_display_mtrr_type((uint32_t)(msr.u64 &
MTRR_DEF_TYPE_MASK)));
}
static void soc_display_variable_mtrr(uint32_t msr_reg, int index,
@@ -160,8 +160,8 @@ static void soc_display_variable_mtrr(uint32_t msr_reg, int index,
msr_t s;
} msr_m;
msr_a.s = rdmsr(msr_reg);
msr_m.s = rdmsr(msr_reg + 1);
msr_a.s = soc_mtrr_read(msr_reg);
msr_m.s = soc_mtrr_read(msr_reg + 1);
if (msr_m.u64 & MTRR_PHYS_MASK_VALID) {
base_address = (msr_a.u64 & 0xfffffffffffff000ULL)
& address_mask;

8
src/soc/intel/common/util.h
View File

@@ -17,9 +17,17 @@
#define _INTEL_COMMON_UTIL_H_
#include <arch/cpu.h>
#include <cpu/x86/msr.h>
#include <stdint.h>
asmlinkage void soc_display_mtrrs(void);
uint32_t soc_get_variable_mtrr_count(uint64_t *msr);
#if IS_ENABLED(CONFIG_SOC_SETS_MTRRS)
msr_t soc_mtrr_read(unsigned long index);
void soc_mtrr_write(unsigned long index, msr_t msr);
#else
#define soc_mtrr_read rdmsr
#define soc_mtrr_write wrmsr
#endif /* CONFIG_SOC_SETS_MTRRS */
#endif /* _INTEL_COMMON_UTIL_H_ */