soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)

Boards could choose a high ROM_SIZE that would result in an MTRR config
that conflicts with other resources. Thus, always use the filtered
CACHE_ROM_SIZE.

Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/quark/romstage/fsp2_0.c

@@ -80,8 +80,8 @@ asmlinkage void *car_stage_c_entry(void)
 	postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
 
 	/* Cache SPI flash - Write protect not supported */
-	postcar_frame_add_mtrr(&pcf, (uint32_t)(-CONFIG_ROM_SIZE),
-		CONFIG_ROM_SIZE, MTRR_TYPE_WRTHROUGH);
+	postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
+			       MTRR_TYPE_WRTHROUGH);
 
 	run_postcar_phase(&pcf);
 	return NULL;