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soc/{amd,intel}: Use CACHE_ROM_(BASE|SIZE)

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Boards could choose a high ROM_SIZE that would result in an MTRR config
that conflicts with other resources. Thus, always use the filtered
CACHE_ROM_SIZE.

Change-Id: I66d36b84ce49c1cb98cb36a4731977baaedf3225
Signed-off-by: Nico Huber <nico.h@gmx.de>
Reviewed-on: https://review.coreboot.org/26575
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Nico Huber
2018-05-27 14:01:11 +02:00
parent 654cc2fe10
commit 9593e973fa
6 changed files with 9 additions and 9 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/amd/stoneyridge/romstage.c
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@@ -128,7 +128,7 @@ asmlinkage void car_stage_entry(void)
MTRR_TYPE_WRBACK); MTRR_TYPE_WRBACK);
/* Cache the memory-mapped boot media. */ /* Cache the memory-mapped boot media. */
postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT); MTRR_TYPE_WRPROT);
/* /*

2
src/soc/intel/apollolake/romstage.c
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@@ -234,7 +234,7 @@ asmlinkage void car_stage_entry(void)
/* Cache the memory-mapped boot media. */ /* Cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT); MTRR_TYPE_WRPROT);
/* /*

4
src/soc/intel/cannonlake/romstage/romstage.c
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@@ -142,8 +142,8 @@ asmlinkage void car_stage_entry(void)
postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, top_of_ram, 16*MiB, MTRR_TYPE_WRBACK);
/* Cache the ROM as WP just below 4GiB. */ /* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1, postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); MTRR_TYPE_WRPROT);
run_postcar_phase(&pcf); run_postcar_phase(&pcf);
} }

2
src/soc/intel/denverton_ns/romstage.c
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@@ -173,7 +173,7 @@ asmlinkage void car_stage_entry(void)
/* Cache the memory-mapped boot media. */ /* Cache the memory-mapped boot media. */
if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED)) if (IS_ENABLED(CONFIG_BOOT_DEVICE_MEMORY_MAPPED))
postcar_frame_add_mtrr(&pcf, -CONFIG_ROM_SIZE, CONFIG_ROM_SIZE, postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
MTRR_TYPE_WRPROT); MTRR_TYPE_WRPROT);
#if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER)
/* /*

4
src/soc/intel/quark/romstage/fsp2_0.c
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@@ -80,8 +80,8 @@ asmlinkage void *car_stage_c_entry(void)
postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK); postcar_frame_add_mtrr(&pcf, 0x80000000, 0x80000, MTRR_TYPE_WRBACK);
/* Cache SPI flash - Write protect not supported */ /* Cache SPI flash - Write protect not supported */
postcar_frame_add_mtrr(&pcf, (uint32_t)(-CONFIG_ROM_SIZE), postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
CONFIG_ROM_SIZE, MTRR_TYPE_WRTHROUGH); MTRR_TYPE_WRTHROUGH);
run_postcar_phase(&pcf); run_postcar_phase(&pcf);
return NULL; return NULL;

4
src/soc/intel/skylake/romstage/romstage_fsp20.c
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@@ -186,8 +186,8 @@ asmlinkage void car_stage_entry(void)
} }
/* Cache the ROM as WP just below 4GiB. */ /* Cache the ROM as WP just below 4GiB. */
postcar_frame_add_mtrr(&pcf, 0xFFFFFFFF - CONFIG_ROM_SIZE + 1, postcar_frame_add_mtrr(&pcf, CACHE_ROM_BASE, CACHE_ROM_SIZE,
CONFIG_ROM_SIZE, MTRR_TYPE_WRPROT); MTRR_TYPE_WRPROT);
run_postcar_phase(&pcf); run_postcar_phase(&pcf);
} }