riscv-trap-handling: Add implementation for trap calls in riscv
RISCV requires the bios/bootloader to set up an interface by which it can get information about memory, talk to host devices, etc. Put implementation for spike in src/mainboard/emulation/spike-riscv/spike_util.c, and src/arch/riscv/trap_handler.c Change-Id: Ie1d5f361595e48fa6cc1fac25485ad623ecdc717 Signed-off-by: Thaminda Edirisooriya <thaminda@google.com> Reviewed-on: http://review.coreboot.org/11368 Tested-by: build bot (Jenkins) Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>
This commit is contained in:
Thaminda Edirisooriya
committed by
Ronald G. Minnich
Ronald G. Minnich
parent
b094583c6f
commit
95ba4c87f5
193
src/arch/riscv/trap_handler.c
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193
src/arch/riscv/trap_handler.c
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/*
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* Early initialization code for riscv
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*
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* Copyright 2015 Google Inc.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; version 2 of
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* the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc.
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*/
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#include <console/console.h>
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#include <arch/exception.h>
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#include <spike_util.h>
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#include <string.h>
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#define HART_ID 0
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#define CONSOLE_PUT 1
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#define SEND_DEVICE_REQUEST 2
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#define RECEIVE_DEVICE_RESPONSE 3
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#define SEND_IPI 4
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#define CLEAR_IPI 5
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#define SHUTDOWN 6
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#define SET_TIMER 7
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#define QUERY_MEMORY 8
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int loopBreak2 = 1;
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void handle_supervisor_call(trapframe *tf) {
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uintptr_t call = tf->gpr[17];
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uintptr_t arg0 = tf->gpr[10];
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uintptr_t arg1 = tf->gpr[11];
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uintptr_t returnValue;
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switch(call) {
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case HART_ID:
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printk(BIOS_DEBUG, "Getting hart id...\n");
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returnValue = mcall_hart_id();
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break;
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case CONSOLE_PUT:
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returnValue = mcall_console_putchar(arg0);
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break;
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case SEND_DEVICE_REQUEST:
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printk(BIOS_DEBUG, "Sending device request...\n");
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returnValue = mcall_dev_req((sbi_device_message*) arg0);
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break;
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case RECEIVE_DEVICE_RESPONSE:
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printk(BIOS_DEBUG, "Getting device response...\n");
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returnValue = mcall_dev_resp();
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break;
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case SEND_IPI:
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printk(BIOS_DEBUG, "Sending IPI...\n");
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returnValue = mcall_send_ipi(arg0);
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break;
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case CLEAR_IPI:
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printk(BIOS_DEBUG, "Clearing IPI...\n");
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returnValue = mcall_clear_ipi();
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break;
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case SHUTDOWN:
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printk(BIOS_DEBUG, "Shutting down...\n");
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returnValue = mcall_shutdown();
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break;
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case SET_TIMER:
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printk(BIOS_DEBUG, "Setting timer...\n");
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returnValue = mcall_set_timer(arg0);
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break;
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case QUERY_MEMORY:
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printk(BIOS_DEBUG, "Querying memory, CPU #%lld...\n", arg0);
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returnValue = mcall_query_memory(arg0, (memory_block_info*) arg1);
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break;
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default:
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printk(BIOS_DEBUG, "ERROR! Unrecognized system call\n");
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returnValue = 0;
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break; // note: system call we do not know how to handle
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}
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tf->gpr[10] = returnValue;
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write_csr(mepc, read_csr(mepc) + 4);
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asm volatile("j supervisor_call_return");
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}
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void trap_handler(trapframe *tf) {
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write_csr(mscratch, tf);
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int cause = 0;
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void* epc = 0;
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void* badAddr = 0;
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// extract cause
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asm("csrr t0, mcause");
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asm("move %0, t0" : "=r"(cause));
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// extract faulting Instruction pc
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epc = (void*) tf->epc;
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// extract bad address
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asm("csrr t0, mbadaddr");
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asm("move %0, t0" : "=r"(badAddr));
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switch(cause) {
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case 0:
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printk(BIOS_DEBUG, "Trap: Instruction address misaligned\n");
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break;
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case 1:
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printk(BIOS_DEBUG, "Trap: Instruction access fault\n");
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printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc);
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printk(BIOS_DEBUG, "Address: %p\n", badAddr);
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break;
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case 2:
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printk(BIOS_DEBUG, "Trap: Illegal instruction\n");
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printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc);
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printk(BIOS_DEBUG, "Address: %p\n", badAddr);
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break;
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case 3:
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printk(BIOS_DEBUG, "Trap: Breakpoint\n");
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break;
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case 4:
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printk(BIOS_DEBUG, "Trap: Load address misaligned\n");
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//handleMisalignedLoad(tf);
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break;
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case 5:
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printk(BIOS_DEBUG, "Trap: Load access fault\n");
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break;
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case 6:
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printk(BIOS_DEBUG, "Trap: Store address misaligned\n");
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printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc);
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printk(BIOS_DEBUG, "Store Address: %p\n", badAddr);
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handle_misaligned_store(tf);
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break;
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case 7:
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printk(BIOS_DEBUG, "Trap: Store access fault\n");
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printk(BIOS_DEBUG, "Bad instruction pc: %p\n", epc);
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printk(BIOS_DEBUG, "Store Address: %p\n", badAddr);
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break;
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case 8:
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printk(BIOS_DEBUG, "Trap: Environment call from U-mode\n");
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break;
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case 9:
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// Don't print so we make console putchar calls look the way they should
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// printk(BIOS_DEBUG, "Trap: Environment call from S-mode\n");
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handle_supervisor_call(tf);
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break;
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case 10:
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printk(BIOS_DEBUG, "Trap: Environment call from H-mode\n");
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break;
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case 11:
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printk(BIOS_DEBUG, "Trap: Environment call from M-mode\n");
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break;
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default:
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printk(BIOS_DEBUG, "Trap: Unknown cause\n");
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break;
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}
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printk(BIOS_DEBUG, "Stored ra: %p\n", (void*) tf->gpr[1]);
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printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
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printk(BIOS_DEBUG, "looping...\n");
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while(1);
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}
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void handle_misaligned_store(trapframe *tf) {
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printk(BIOS_DEBUG, "Trapframe ptr: %p\n", tf);
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printk(BIOS_DEBUG, "Stored sp: %p\n", (void*) tf->gpr[2]);
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insn_t faultingInstruction = 0;
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uintptr_t faultingInstructionAddr = tf->epc;
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asm("move t0, %0" : /* No outputs */ : "r"(faultingInstructionAddr));
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asm("lw t0, 0(t0)");
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asm("move %0, t0" : "=r"(faultingInstruction));
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printk(BIOS_DEBUG, "Faulting instruction: 0x%x\n", faultingInstruction);
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insn_t widthMask = 0x7000;
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insn_t memWidth = (faultingInstruction & widthMask) >> 12;
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insn_t srcMask = 0x1F00000;
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insn_t srcRegister = (faultingInstruction & srcMask) >> 20;
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printk(BIOS_DEBUG, "Width: 0x%x\n", memWidth);
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if (memWidth == 3) {
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// store double, handle the issue
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void* badAddress = (void*) tf->badvaddr;
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long valueToStore = tf->gpr[srcRegister];
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memcpy(badAddress, &valueToStore, 8);
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} else {
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// panic, this should not have happened
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printk(BIOS_DEBUG, "Code should not reach this path, misaligned on a non-64 bit store/load\n");
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while(1);
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}
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// return to where we came from
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write_csr(mepc, read_csr(mepc) + 4);
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asm volatile("j machine_call_return");
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}
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