soc/intel/alderlake/hsphy: Add possibility to cache HSPHY in flash

The patch adds a possibility to cache the PCIe 5.0 HSPHY firmware in
the SPI flash. New flashmap region is created for that purpose. The
goal of caching is to reduce the dependency on CSME and the HECI IP
LOAD command which may fail when the CSME is disabled, e.g. soft
disabled by HECI command or HAP disabled. This change allows to
keep PCIe 5.0 root ports functioning even if CSME/HECI is not
functional.

TEST=Boot Ubuntu 22.04 on MSI PRO Z690-A and notice PCIe 5.0 port
is functional after loading the HSPHY from cache.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I5a37f5b06706ff30d92f60f1bf5dc900edbde96f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68987
Reviewed-by: Krystian Hebel <krystian.hebel@3mdeb.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

util/cbfstool/default-x86.fmd

@@ -14,6 +14,7 @@ FLASH@##ROM_BASE## ##ROM_SIZE## {
 		##SMMSTORE_ENTRY##
 		##SPD_CACHE_ENTRY##
 		##VPD_ENTRY##
+		##HSPHY_FW_ENTRY##
 		FMAP@##FMAP_BASE## ##FMAP_SIZE##
 		COREBOOT(CBFS)@##CBFS_BASE## ##CBFS_SIZE##
 	}