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nb/intel/nehalem: Rename to ironlake

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The code is for Arrandale CPUs, whose System Agent is Ironlake.

This change simply replaces `nehalem` with `ironlake` and `NEHALEM`
with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as
changing some of them would impact the resulting binary.

Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and packardbell/ms2290 does not change.

Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2020-02-17 13:08:53 +01:00
committed by Patrick Georgi
parent 2aff3005e0
commit 95de2317c6
47 changed files with 77 additions and 77 deletions
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2
src/cpu/intel/Makefile.inc
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@@ -10,7 +10,7 @@ subdirs-$(CONFIG_CPU_INTEL_SOCKET_FCBGA559) += socket_FCBGA559
subdirs-$(CONFIG_CPU_INTEL_SOCKET_M) += socket_m
subdirs-$(CONFIG_CPU_INTEL_SOCKET_P) += socket_p
subdirs-$(CONFIG_CPU_INTEL_SOCKET_MPGA604) += socket_mPGA604
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_NEHALEM) += model_2065x
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_IRONLAKE) += model_2065x
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_SANDYBRIDGE) += model_206ax
subdirs-$(CONFIG_NORTHBRIDGE_INTEL_HASWELL) += haswell
subdirs-$(CONFIG_CPU_INTEL_SLOT_1) += slot_1

4
src/cpu/intel/model_2065x/acpi.c
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@@ -216,7 +216,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
/* Max Non-Turbo Ratio */
ratio_max = (msr.lo >> 8) & 0xff;
}
clock_max = ratio_max * NEHALEM_BCLK + ratio_max / 3;
clock_max = ratio_max * IRONLAKE_BCLK + ratio_max / 3;
/* Calculate CPU TDP in mW */
power_max = 25000;
@@ -277,7 +277,7 @@ static void generate_P_state_entries(int core, int cores_per_package)
/* Calculate power at this ratio */
power = calculate_power(power_max, ratio_max, ratio);
clock = ratio * NEHALEM_BCLK + ratio / 3;
clock = ratio * IRONLAKE_BCLK + ratio / 3;
acpigen_write_PSS_package(
clock, /*MHz*/

2
src/cpu/intel/model_2065x/model_2065x.h
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@@ -16,7 +16,7 @@
#define _CPU_INTEL_MODEL_2065X_H
/* Nehalem bus clock is fixed at 133MHz */
#define NEHALEM_BCLK 133
#define IRONLAKE_BCLK 133
#define MSR_CORE_THREAD_COUNT 0x35
#define MSR_FEATURE_CONFIG 0x13c

2
src/cpu/intel/model_2065x/model_2065x_init.c
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@@ -197,7 +197,7 @@ static void set_max_ratio(void)
wrmsr(IA32_PERF_CTL, perf_ctl);
printk(BIOS_DEBUG, "model_x06ax: frequency set to %d\n",
((perf_ctl.lo >> 8) & 0xff) * NEHALEM_BCLK);
((perf_ctl.lo >> 8) & 0xff) * IRONLAKE_BCLK);
}
static void set_energy_perf_bias(u8 policy)