nb/intel/nehalem: Rename to ironlake

The code is for Arrandale CPUs, whose System Agent is Ironlake.

This change simply replaces `nehalem` with `ironlake` and `NEHALEM`
with `IRONLAKE`. The remaining `Nehalem` cases are handled later, as
changing some of them would impact the resulting binary.

Tested with BUILD_TIMELESS=1 without adding the configuration options
into the binary, and packardbell/ms2290 does not change.

Change-Id: I8eb96eeb5e69f49150d47793b33e87b650c64acc
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38941
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/southbridge/intel/common/firmware/Kconfig

@@ -59,7 +59,7 @@ config ME_BIN_PATH
 config CHECK_ME
 	bool "Verify the integrity of the supplied ME/TXE firmware"
 	default n
-	depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \
+	depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \
 		NORTHBRIDGE_INTEL_SANDYBRIDGE || \
 		NORTHBRIDGE_INTEL_HASWELL || \
 		SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \
@@ -71,7 +71,7 @@ config CHECK_ME
 
 config USE_ME_CLEANER
 	bool "Strip down the Intel ME/TXE firmware"
-	depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_NEHALEM || \
+	depends on HAVE_ME_BIN && (NORTHBRIDGE_INTEL_IRONLAKE || \
 		NORTHBRIDGE_INTEL_SANDYBRIDGE || \
 		NORTHBRIDGE_INTEL_HASWELL || \
 		SOC_INTEL_BROADWELL || SOC_INTEL_SKYLAKE || \

src/southbridge/intel/ibexpeak/early_cir.c

@@ -14,7 +14,7 @@
 #include <console/console.h>
 #include <device/pci_ops.h>
 #include <device/pci_def.h>
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 #include "pch.h"
 
 /* This sets up magic Chipset Initialization Registers */
@@ -53,7 +53,7 @@ void pch_setup_cir(int chipset_type)
 
 	/* Intel 5 Series Chipset and Intel 3400 Series Chipset
 	   External Design Specification (EDS) 13.8.1.1 */
-	if (chipset_type == NEHALEM_DESKTOP)
+	if (chipset_type == IRONLAKE_DESKTOP)
 		pci_or_config32(PCH_LPC_DEV, GEN_PMCON_1, 1 << 3);
 
 	pci_write_config8(PCH_LPC_DEV, CIR4, 0x45);

src/southbridge/intel/ibexpeak/early_pch.c

@@ -19,7 +19,7 @@
 #include <stdint.h>
 #include <device/pci_ops.h>
 #include <device/smbus_host.h>
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 #include <southbridge/intel/ibexpeak/pch.h>
 #include <southbridge/intel/common/gpio.h>
 
@@ -47,7 +47,7 @@ void early_pch_init(void)
 	early_gpio_init();
 	enable_smbus();
 	/* TODO, make this configurable */
-	pch_setup_cir(NEHALEM_MOBILE);
+	pch_setup_cir(IRONLAKE_MOBILE);
 	southbridge_configure_default_intmap();
 	pch_default_disable();
 	early_usb_init(mainboard_usb_ports);

src/southbridge/intel/ibexpeak/smihandler.c

@@ -34,7 +34,7 @@
  *  1. the chipset can do it
  *  2. we don't need to worry about how we leave 0xcf8/0xcfc behind
  */
-#include <northbridge/intel/nehalem/nehalem.h>
+#include <northbridge/intel/ironlake/ironlake.h>
 #include <southbridge/intel/common/gpio.h>
 #include <southbridge/intel/common/pmutil.h>
 
@@ -185,6 +185,6 @@ void southbridge_finalize_all(void)
 {
 	intel_me_finalize_smm();
 	intel_pch_finalize_smm();
-	intel_nehalem_finalize_smm();
+	intel_ironlake_finalize_smm();
 	intel_model_2065x_finalize_smm();
 }