From 9648106683ab348acaa9cff6d4eb801915081418 Mon Sep 17 00:00:00 2001 From: Subrata Banik Date: Sun, 27 Mar 2022 20:15:50 +0530 Subject: [PATCH] Documentation: gpio: Update table as per coreboot guidelines MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit This patch fixes the table issue in markdown file introduced with commit 5338a16b (Documentation: gpio: Fix table). BUG=b:211573253, b:211950520 Signed-off-by: Subrata Banik Change-Id: Ic4f27f46a9d219098612d8b7747ae26116506fce Reviewed-on: https://review.coreboot.org/c/coreboot/+/63126 Tested-by: build bot (Jenkins) Reviewed-by: Michael Niewöhner --- Documentation/getting_started/gpio.md | 81 ++++++++++++++++++--------- 1 file changed, 55 insertions(+), 26 deletions(-) diff --git a/Documentation/getting_started/gpio.md b/Documentation/getting_started/gpio.md index 5f30ea7c38..216ba5d3bb 100644 --- a/Documentation/getting_started/gpio.md +++ b/Documentation/getting_started/gpio.md @@ -167,32 +167,61 @@ could cause catastrophic failures, up to and including your mainboard! As per Intel Platform Controller Hub (PCH) EDS since Skylake, a GPIO PAD register supports four different types of GPIO reset as: -| PAD Reset Config | Platform Reset | GPP | GPD | -|-------------------------------------------------|----------------|-----|-----| -| 00 - Power Good (GPP: RSMRST, GPD: DSW_PWROK) | Warm Reset | N | N | -| | Cold Reset | N | N | -| | S3/S4/S5 | N | N | -| | Global Reset | N | N | -| | Deep Sx | Y | N | -| | G3 | Y | N | -| 01 - Deep | Warm Reset | Y | Y | -| | Cold Reset | Y | Y | -| | S3/S4/S5 | N | N | -| | Global Reset | Y | Y | -| | Deep Sx | Y | Y | -| | G3 | Y | Y | -| 10 - Host Reset/PLTRST | Warm Reset | Y | Y | -| | Cold Reset | Y | Y | -| | S3/S4/S5 | Y | Y | -| | Global Reset | Y | Y | -| | Deep Sx | Y | Y | -| | G3 | Y | Y | -| 11 - Resume Reset (GPP: Reserved, GPD: RSMRST) | Warm Reset | - | N | -| | Cold Reset | - | N | -| | S3/S4/S5 | - | N | -| | Global Reset | - | N | -| | Deep Sx | - | Y | -| | G3 | - | Y | +```eval_rst ++------------------------+----------------+-------------+-------------+ +| | | PAD Reset ? | ++ PAD Reset Config + Platform Reset +-------------+-------------+ +| | | GPP | GPD | ++========================+================+=============+=============+ +| | 00 - Power Good | Warm Reset | N | N | +| | (GPP: RSMRST, +----------------+-------------+-------------+ +| | GPD: DSW_PWROK) | Cold Reset | N | N | +| |----------------+-------------+-------------+ +| | S3/S4/S5 | N | N | +| +----------------+-------------+-------------+ +| | Global Reset | N | N | +| +----------------+-------------+-------------+ +| | Deep Sx | Y | N | +| +----------------+-------------+-------------+ +| | G3 | Y | Y | ++------------------------+----------------+-------------+-------------+ +| 01 - Deep | Warm Reset | Y | Y | +| +----------------+-------------+-------------+ +| | Cold Reset | Y | Y | +| +----------------+-------------+-------------+ +| | S3/S4/S5 | N | N | +| +----------------+-------------+-------------+ +| | Global Reset | Y | Y | +| +----------------+-------------+-------------+ +| | Deep Sx | Y | Y | +| +----------------+-------------+-------------+ +| | G3 | Y | Y | ++------------------------+----------------+-------------+-------------+ +| 10 - Host Reset/PLTRST | Warm Reset | Y | Y | +| +----------------+-------------+-------------+ +| | Cold Reset | Y | Y | +| +----------------+-------------+-------------+ +| | S3/S4/S5 | Y | Y | +| +----------------+-------------+-------------+ +| | Global Reset | Y | Y | +| +----------------+-------------+-------------+ +| | Deep Sx | Y | Y | +| +----------------+-------------+-------------+ +| | G3 | Y | Y | ++------------------------+----------------+-------------+-------------+ +| | 11 - Resume Reset | Warm Reset | - | N | +| | (GPP: Reserved, +----------------+-------------+-------------+ +| | GPD: RSMRST) | Cold Reset | - | N | +| +----------------+-------------+-------------+ +| | S3/S4/S5 | - | N | +| +----------------+-------------+-------------+ +| | Global Reset | - | N | +| +----------------+-------------+-------------+ +| | Deep Sx | - | Y | +| +----------------+-------------+-------------+ +| | G3 | - | Y | ++------------------------+----------------+-------------+-------------+ +``` Each GPIO Community has a Pad Configuration Lock register for a GPP allowing locking specific register fields in the PAD configuration register.