nb/intel/sandybridge: Clean up stepping logic

Do not combine the host bridge device ID with the CPU stepping because
it is confusing. Although Sandy/Ivy Bridge processors incorporate both
CPU and northbridge components into the same die, it is best to treat
them separately. Plus, this change enables moving CPU stepping macros
from northbridge code into the CPU scope, which is done in a follow-up.

Change-Id: I27ad609eb53b96987ad5445301b5392055fa4ea1
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48408
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Nico Huber <nico.h@gmx.de>

src/cpu/intel/model_206ax/model_206ax.h

@@ -3,6 +3,7 @@
 #ifndef _CPU_INTEL_MODEL_206AX_H
 #define _CPU_INTEL_MODEL_206AX_H
 
+#include <arch/cpu.h>
 #include <stdint.h>
 
 /* SandyBridge/IvyBridge bus clock is fixed at 100MHz */
@@ -88,4 +89,9 @@ void set_power_limits(u8 power_limit_1_time);
 int cpu_config_tdp_levels(void);
 int get_platform_id(void);
 
+static inline u8 cpu_stepping(void)
+{
+	return cpuid_eax(1) & 0xf;
+}
+
 #endif