flashrom: Move the SPI #defines from spi.c to spi.h
This patch has no code changes. Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net> Acked-by: Peter Stuge <peter@stuge.se> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3302 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -27,70 +27,11 @@
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#include <stdint.h>
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#include <string.h>
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#include "flash.h"
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#include "spi.h"
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#define ITE_SUPERIO_PORT1 0x2e
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#define ITE_SUPERIO_PORT2 0x4e
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/* Read Electronic ID */
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#define JEDEC_RDID 0x9f
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#define JEDEC_RDID_OUTSIZE 0x01
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#define JEDEC_RDID_INSIZE 0x03
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/* Write Enable */
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#define JEDEC_WREN 0x06
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#define JEDEC_WREN_OUTSIZE 0x01
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#define JEDEC_WREN_INSIZE 0x00
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/* Write Disable */
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#define JEDEC_WRDI 0x04
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#define JEDEC_WRDI_OUTSIZE 0x01
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#define JEDEC_WRDI_INSIZE 0x00
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/* Chip Erase 0x60 is supported by Macronix/SST chips. */
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#define JEDEC_CE_60 0x60
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#define JEDEC_CE_60_OUTSIZE 0x01
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#define JEDEC_CE_60_INSIZE 0x00
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/* Chip Erase 0xc7 is supported by ST/EON/Macronix chips. */
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#define JEDEC_CE_C7 0xc7
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#define JEDEC_CE_C7_OUTSIZE 0x01
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#define JEDEC_CE_C7_INSIZE 0x00
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/* Block Erase 0x52 is supported by SST chips. */
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#define JEDEC_BE_52 0x52
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#define JEDEC_BE_52_OUTSIZE 0x04
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#define JEDEC_BE_52_INSIZE 0x00
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/* Block Erase 0xd8 is supported by EON/Macronix chips. */
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#define JEDEC_BE_D8 0xd8
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#define JEDEC_BE_D8_OUTSIZE 0x04
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#define JEDEC_BE_D8_INSIZE 0x00
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/* Sector Erase 0x20 is supported by Macronix/SST chips. */
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#define JEDEC_SE 0x20
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#define JEDEC_SE_OUTSIZE 0x04
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#define JEDEC_SE_INSIZE 0x00
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/* Read Status Register */
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#define JEDEC_RDSR 0x05
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#define JEDEC_RDSR_OUTSIZE 0x01
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#define JEDEC_RDSR_INSIZE 0x01
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#define JEDEC_RDSR_BIT_WIP (0x01 << 0)
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/* Write Status Register */
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#define JEDEC_WRSR 0x01
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#define JEDEC_WRSR_OUTSIZE 0x02
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#define JEDEC_WRSR_INSIZE 0x00
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/* Read the memory */
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#define JEDEC_READ 0x03
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#define JEDEC_READ_OUTSIZE 0x04
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/* JEDEC_READ_INSIZE : any length */
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/* Write memory byte */
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#define JEDEC_BYTE_PROGRAM 0x02
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#define JEDEC_BYTE_PROGRAM_OUTSIZE 0x05
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#define JEDEC_BYTE_PROGRAM_INSIZE 0x00
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uint16_t it8716f_flashport = 0;
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/* use fast 33MHz SPI (<>0) or slow 16MHz (0) */
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